AN210403 Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD USB Type C Controllers.pdf

AN210403
Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB
Type-C Controllers
Author: Madhura Tapse
Associated Part Family: CYPD212x, CYPD3125, CYPD4x25
Related Application Notes: Click here
To get the latest version of this application note, please visit http://www.cypress.com/AN210403.
AN210403 provides hardware design and PCB layout guidelines for designing a Dual Role Port (DRP) application
(for example, a notebook with a Type-C port) using EZ-PD CCG2, EZ-PD CCG3, and EZ-PD CCG4 USB Type-C
controllers. The application note also demonstrates DRP application examples using Cypress evaluation kits as a
reference.
Contents
1
2
Introduction ...............................................................2
USB Power Delivery Specification ............................3
2.1
Type-C Signal Definition ..................................5
2.2
Type-C Ports....................................................6
3
CCG2/CCG3/CCG4 Overview ..................................7
3.1
Type-C PD Controller Power Subsystem .........8
4
Dual Type-C Port DRP Application Using CCG4 .... 10
4.1
Power Supply Design .................................... 11
2
4.2
I C Communication with
Embedded Controller ..................................... 13
4.3
Dead Battery Charging .................................. 14
4.4
Power Provider/Consumer Role .................... 15
4.5
DisplayPort Connections................................ 23
4.6
Electrical Design Considerations ................... 27
5
Single Type-C Port DRP Application
Using CCG4 ........................................................... 28
5.1
Power Supply Design .................................... 29
2
5.2
I C Communication with
Embedded Controller ..................................... 29
5.3
Dead Battery Charging .................................. 29
5.4
Power Provider/Consumer Role .................... 29
5.5
DisplayPort Connections................................ 29
5.6
Electrical Design Considerations ................... 30
www.cypress.com
6
Single Type-C Port DRP Application
Using CCG3 ........................................................... 31
6.1
Power Supply Design .................................... 32
2
6.2
I C Communication with
Embedded Controller ..................................... 33
6.3
Dead Battery Charging .................................. 33
6.4
Power Provider/Consumer Role .................... 34
6.5
DisplayPort Connections ............................... 35
6.6
Electrical Design Considerations ................... 36
7
Single Type-C Port DRP Application
Using CCG2 ........................................................... 36
7.1
Power Supply Design .................................... 37
2
7.2
I C Communication with
Embedded Controller ..................................... 38
7.3
Dead Battery Charging .................................. 38
7.4
Power Provider/Consumer Role .................... 38
7.5
DisplayPort Connections ............................... 38
7.6
Electrical Design Considerations ................... 38
8
Electrical Design Considerations ............................ 38
9
Schematic and Layout Review Checklist ................ 44
Document History............................................................ 48
Worldwide Sales and Design Support ............................. 49
Document No. 002-10403 Rev. **
1
Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
1
Introduction
The USB Power Delivery (PD) Specification Revision 2.0, Version 1.1 defines power delivery up to 100 W (20 V at
5 A) over existing USB standards. The USB Type-C Cable and Connector Specification Revision 1.1 details a new
reversible and sub-3-mm slim connector design that supports 100 W of power along with USB and non-USB signals
such as DisplayPort.
Cypress provides a portfolio of USB Type-C and PD controllers, including EZ-PD CCG1, EZ-PD CCG2,
EZ-PD CCG3, and EZ-PD CCG4.
CCG1 is Cypress’s first-generation Type-C and PD controller, which supports up to two USB ports with PD. CCG1
has 32 KB flash and 4 KB SRAM memory. CCG1 is a fixed-function part and the functionality is implemented in the
CCG1 device’s firmware. CCG1 provides a USB Type-C and Power Delivery solution for notebooks, monitors,
docking stations, power adapters and USB Type-C cables.
CCG2 is Cypress’s second-generation Type-C and PD controller, integrating one Type-C transceiver and termination
resistors Rp, Rd, and Ra. CCG2 has 32 KB of flash and 4 KB of SRAM memory. It provides a complete USB Type-C
and Power Delivery solution for Type-C notebook and cable designs.
CCG3 is Cypress’s third-generation USB Type-C and PD controller, integrating one Type-C transceiver and
termination resistors Rp, Rd, and Ra. CCG3 provides additional features such as a crypto engine for authentication,
two integrated pairs of gate drivers to control the VBUS provider and consumer path, integrated VCONN and VBUS
discharge FETs, integrated overvoltage and overcurrent protection, and USB 2.0 Billboard support. In addition, CCG3
has 128 KB of flash and 8 KB of SRAM memory.
CCG4 is Cypress’s fourth-generation Type-C and PD controller, which includes two Type-C transceivers and
termination resistors Rp and Rd. CCG4 has integrated VCONN FETs, 128 KB of flash, and 8 KB of SRAM memory.
CCG4 provides a complete solution for dual Type-C port notebook and power adapter designs.
These Type-C and PD controllers are fully compliant with the USB PD and Type-C standards. Table 1 summarizes
the differences among them.
Table 1. Feature Comparison of Cypress's USB Type-C and PD Controllers
Features
CCG1
CCG2
CCG3
CCG4
Number of Type-C and PD ports
1
1
1
2
Integrated ARM® Cortex®-M0 MCU at 48 MHz
Yes
Yes
Yes
Yes
Memory (Flash, SRAM)
32 KB, 4 KB
32 KB, 4 KB
128 KB, 8 KB
128 KB, 8 KB
Integrated Type-C Transceiver (Number)
Yes (1)
Yes (1)
Yes (1)
Yes (2)
Integrated Type-C Resistors
No
Yes (Ra, Rp, Rd)
Yes (Ra, Rp, Rd)
Yes (Rp, Rd)
Number of GPIOs
Up to 30
Up to 14
Up to 20
Up to 30
Number of Serial Communication Blocks
(I2C/SPI/UART)
1
2
4
4
Number of TCPWM Blocks
2
6
4
4
Integrated USB Billboard Device Class Full Speed
USB 2.0 Device
No
No
Yes
No
Hardware Authentication Block (Crypto)
No
No
Yes
No
Integrated VCONN FETs
No
No
Yes (1 pair)
Yes (2 pairs)
Integrated VBUS discharge FETs
No
No
Yes
No
Integrated 20-V VBUS NFET/PFET Gate Drivers
No
No
Yes (2 pairs)
No
Integrated SBU/AUX analog switch
No
No
Yes
No
Supply Voltage
1.8 V – 5.5 V
2.7 V – 5.5 V
2.7 V – 21.5 V
2.7 V – 5.5 V
(Each block can be configured as timer, counter, or
pulse width modulator)
www.cypress.com
Document No. 002-10403 Rev. **
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Features
CCG1
CCG2
CCG3
CCG4
VBUS Overvoltage Protection (OVP), Undervoltage
Protection (UVP) and Overcurrent Protection (OCP)
Yes
Yes
Yes
Yes
(Using
external
hardware
circuitry)
(Using external
hardware
circuitry)
(Integrated)
(Using
external
hardware
circuitry)
Integrated ADCs for OVP, UVP, OCP Detection and
other voltage or current measurements
1 channel
1 channel
2 channels
4 channels
(12-bit SAR)
(8-bit SAR)
(8-bit SAR)
(8-bit SAR)
USB Battery Charger (BC) Revision 1.2 and Legacy
Apple Charger Detection and Emulation
No
No
Yes
No
ESD Protection
Yes
Yes
Yes
Yes
(Up-to 2.2 kV)
(Up-to ± 8-kV
contact
discharge and
up-to ±15-kV air
discharge)
(Up-to ± 8-kV
contact
discharge and
up-to ±15-kV air
discharge)
(Up-to ± 8-kV
contact
discharge and
up-to ±15-kV
air discharge)
40-QFN,
24-QFN,
40-QFN,
40-QFN
16-SOIC,
14-DFN,
42-CSP,
35-CSP
20-CSP
16-SOIC
Packages
This application note provides information on designing USB Type-C DRP applications using CCG2, CCG3, and
CCG4. CCG2, CCG3 and CCG4 controllers have more integrated features as compared to CCG1, which help to
reduce the BOM cost of DRP application design. See AN96527 – Designing USB Type-C Products Using Cypress’s
CCG1 Controllers for detailed information on USB Type-C designs using CCG1. This application note gives a brief
overview of CCG2, CCG3, and CCG4, and explains the power subsystem required to kick start the design. It provides
hardware guidelines for a successful notebook design with a single or dual Type-C port using Cypress’s Type-C and
PD controllers. The application note provides information on how to use the CCG4 Evaluation Kit (refer to Table 2 for
Type-C PD controller evaluation kits) to demonstrate the DRP application.
Table 2. Type-C and PD Controller Evaluation Kits
Type-C PD Controller
Type-C PD Controller Evaluation Kit
CCG3
CY4531 EZ-PD CCG3 Evaluation Kit
CCG4
CY4541 EZ-PD CCG4 Evaluation Kit
This application note references the CY4541 EZ-PD CCG4 Evaluation Kit and is intended as supplemental
information to the respective kit guide.
2
USB Power Delivery Specification
This section reviews the basics of USB power delivery. The USB PD specification defines how a PD-enabled USB
port can get the required power from VBUS by negotiating with external power sources (such as wall warts).
A USB port providing power is known as a source, and a USB port consuming power is known as a sink. There is
only one source port and one sink port in each PD connection. In the legacy USB specification, the USB port on host
computer (such as a notebook or a PC) was always a source and the USB peripheral device was always a sink. The
USB PD specification allows the source and sink to interchange their roles so that a USB peripheral device (such as
an external self-powered hard disk or monitor) can supply power to a USB Host. These new power roles are
independent of the USB data transfer roles between the USB Host and USB device. An example is a self-powered
USB peripheral such as a monitor that can charge the battery of a notebook or PC, which is a USB Host.
Figure 1 shows logical block diagram of the Type-C and PD architecture.
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Document No. 002-10403 Rev. **
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Figure 1. Type-C and PD Architecture for Dual Role Port Applications










System Policy Manager: The PD Specification defines a System Policy Manager that is implemented on the
USB Host running as an operating system stack. For more details of System Policy, see the PD Specification.
Device Policy Manager: The Device Policy Manager is the module running in the Power Provider or Power
Consumer, which applies a Local Policy to each Port in the device via the Policy Engine.
Source Port: The Source Port is the power provider port, which supplies power over VBUS. It is, by default, a
USB port on the Host or Hub.
Sink Port: The Sink Port is the USB power consumer port, which consumes power over VBUS. It is, by default,
a USB port on a device.
Policy Engine: The Policy Engine interprets the Device Policy Manager’s input to implement the Policy for the
port. It also directs the Protocol Layer to send messages.
Protocol: The Protocol Layer creates the messages for communication between Port Partners.
Physical Layer: The Physical Layer sends and receives messages over either VBUS or the configuration
channel (CC) between Port Pairs.
Power Source: The ability of a Power Delivery (PD) port to source power over VBUS. This refers to a Type-C
port with Rp asserted on CC.
Power Sink: The ability of a Power Delivery (PD) port to sink power from VBUS. This refers to a Type-C port
with Rd asserted on CC.
Cable Detection Module: The Cable Detection Module detects the presence of an Electronically Marked Cable
Assembly (EMCA) cable attached to a Type-C port.
Dual-role devices can be developed by combining both provider and consumer elements in a single device.
When a USB Host and USB device are interconnected, they form a USB link pair, and each link partner has a
configuration channel (CC) controller. Messages are then logically exchanged among Device Policy Managers within
each PD controller. These messages are physically transferred over the CC, and a PD contract is set up between the
link pair, and then power is delivered over VBUS.
The CC is a new signal pair in the Type-C signal definition—see Type-C Signal Definition.
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Document No. 002-10403 Rev. **
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
2.1
Type-C Signal Definition
Figure 2 shows the USB Type-C Receptacle, Plug, and Flipped-Plug signals. Table 3 and Table 4 show the signals
used on the USB Type-C receptacle and plug.
Figure 2. USB Type-C Plug, Receptacle, and Flipped-Plug Signals
Plug
Receptacle
Flipped
Plug
Table 3. USB Type-C Receptacle Signals
Signal Group
Signal
Description
USB 3.1
TX1p, TX1n,
RX1p, RX1n,
TX2p, TX2n,
RX2p, RX2n
The SuperSpeed USB serial data interface defines a differential transmit pair and a
differential receive pair. On a USB Type-C receptacle, two pairs of SuperSpeed USB
signal pins are defined to enable the plug-flipping feature.
USB 2.0
Dp1, Dn1
Dp2, Dn2
The USB 2.0 serial data interface defines a differential pair. On a USB Type-C
receptacle, two sets of USB 2.0 signal pins are defined to enable plug-flipping.
Configuration Channel
CC1, CC2
The CC in the receptacle detects the signal orientation and channel configuration.
Auxiliary signals
SBU1, SBU2
Sideband use. Refer to the USB Type-C Cable and Connector Specification Revision
1.1 for more details.
Power
VBUS
USB cable bus power
GND
USB cable return current path
Table 4. USB Type-C Plug Signals
Signal Group
Signal
Description
USB 3.1
TX1p, TX1n
RX1p, RX1n
TX2p, TX2n
RX2p, RX2n
The SuperSpeed USB serial data interface defines a differential transmit pair and a
differential receive pair. On a USB Type-C plug, two pairs of SuperSpeed USB signal
pins are defined to enable the plug-flipping feature.
USB 2.0
Dp, Dn
On a USB Type-C plug, the USB 2.0 serial data interface defines differential pair.
Configuration Channel
CC
The CC in the plug is used for connection detection and interface configuration.
Auxiliary signals
SBU1, SBU2
Sideband use. Refer to the USB Type-C Cable and Connector Specification Revision
1.1 for more details.
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Document No. 002-10403 Rev. **
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Signal Group
Power
Signal
Description
VBUS
USB cable bus power
VCONN
Type-C cable plug power
GND
USB cable return current path
As shown in Figure 2, the USB Type-C receptacle has USB 3.1 (TX and RX pairs) and USB 2.0 (Dp and Dn) data
buses, USB power (VBUS), ground (GND), CC signals (CC1 and CC2), and two sideband use (SBU) signal pins. As
listed in Table 3 and Table 4, the descriptions of the USB Type-C plug and receptacle signals are the same, except
for the CC and VCONN signals. The two sets of USB 2.0 and USB 3.1 signal locations in this layout facilitate the
mapping of the USB signals independent of the plug orientation in the receptacle.
When a cable with the Type-C plug is inserted into the receptacle, one CC pin is used to establish signal orientation,
and the other CC pin is repurposed as VCONN for powering the electronics in the USB Type-C cable (plug).
2.2
Type-C Ports
2.2.1
Downstream Facing Port and Upstream Facing Port
A Type-C downstream facing port (DFP) is by default a USB Host and a power source, whereas a Type-C upstream
facing port (UFP) is by default a USB Device and a power sink. A DFP exposes Rp terminations on its CC pins (CC1
and CC2), while a UFP exposes Rd terminations on its CC pin, as shown in Figure 3.
Figure 3. Direct Connection of a Downstream Facing Port and Upstream Facing Port
DFPs, specifically those associated with the flow of data in a USB connection, are typically the USB ports on a Host
such as a PC or a hub. In its default state, the DFP sources VBUS and VCONN. On the other hand, UFP sinks
VBUS.
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Document No. 002-10403 Rev. **
6
Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
2.2.2
USB PD Dual Role Port
PD-enabled USB products (such as a notebook with a Type-C port) operate as a power provider and a power
consumer. The USB PD specification refers to such USB Type-C ports as Dual Role Ports (DRPs).
DRP devices have the capability to detect the presence of the Rp and Rd resistors on the CC lines. A typical DRP
device can perform the roles listed in Table 5.
Table 5. Roles of DRP Device
3
No.
Data Port Role
(USB Host or Device)
Power Port Role
(Power Provider or Power Consumer)
1
DFP (Connect Rp and disconnect Rd)
Source (Power Provider)
2
DFP (Disconnect Rp and connect Rd)
Sink (Power Consumer)
3
UFP (Connect Rp and disconnect Rd)
Source (Power Provider)
4
UFP (Disconnect Rp and connect Rd)
Sink (Power Consumer)
CCG2/CCG3/CCG4 Overview
Table 6 lists the available part numbers for CCG2, CCG3, and CCG4 Type-C and PD controllers with their respective
applications.
Table 6. Type-C PD Controller MPNs and Applications
Type-C PD Controller
Manufacturing Part Number
CCG2
CYPD2122-24LQXIT
DRP
Notebooks
24-pin QFN
CYPD2122-20FNXIT
DRP
Tablets
20-ball CSP
CYPD2121-24LQXIT
DRP
Dock/Monitor Upstream Port
24-pin QFN
CYPD2134-24LQXIT
DFP
Power Adapter
24-pin QFN
CYPD2125-24LQXIT
DFP
Dock/Monitor Downstream Port
24-pin QFN
CYPD2103-20FNXIT
Cable
Cable
20-ball CSP
CYPD2119-24LQXIT
C-DP
UFP
24-pin QFN
CYPD2120-24LQXIT
C-HDMI
UFP
24-pin QFN
CYPD2103-14LHXIT
Cable
Cable
14-pin DFN
CYPD2105-20FNXIT
Active Cable
Active Cable
20-ball CSP
CYPD2104-20FNXIT
Accessory
Accessory
20-ball CSP
CYPD3125-40LQXIT
DRP
Notebooks
40-pin QFN
CYPD3121-40LQXIT
DFP
Monitor/Dock
40-pin QFN
CYPD3135-40LQXIT
DFP
Power Adapter
40-pin QFN
CYPD3122-40LQXIT
UFP
Monitor/Dock
40-pin QFN
CYPD3120-40LQXIT
UFP
Dongle
40-pin QFN
CYPD3105-42FNXIT
Cable
Thunderbolt Active Cable
42-pin CSP
CYPD4225-40LQXIT
DRP
Dual Type-C port Notebooks,
Docking Stations
40-pin QFN
CYPD4125-40LQXIT
DRP
Single Type-C port Notebooks,
Docking Stations
40-pin QFN
CYPD4235-40LQXIT
DFP
Power Adapters
40-pin QFN
CYPD4135-40LQXIT
DFP
Power Adapters
40-pin QFN
CCG3
CCG4
www.cypress.com
Role
Document No. 002-10403 Rev. **
Application
Package
7
Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
3.1
Type-C PD Controller Power Subsystem
Table 7 provides the power domain details of Type-C and PD controllers and the recommended values of bypass
capacitors to be used on the respective power supply pins.
Table 7. Type-C and PD Controller Power Subsystem
Type-C and PD
Controller
Power
Supply Pin
VDDD
Power Supply
Domain
Supply to the core
Role
Value of Bypass
Capacitor to GND
Valid Input Voltage Level
DRP
3.0 V to 5.5 V
DFP
3.0 V to 5.5 V
UFP
2.7 V to 5.5 V
1 µF
DRP
VDDIO
Supply to I/Os
DFP
1.71 V to VDDD
1 µF
UFP
CCG2
VCCD
The core voltage of the device is brought out to the pin. This pin
cannot be used as voltage source and is intended to connect only
a decoupling capacitor.
1 µF
NA (This is an output pin.)
DRP
VCONN1 and
VCONN2
Supply to power
VCONN FETs
DFP
VSYS
VDDD
Supply to the core
DRP
Note: Either VBUS
or VSYS can be
provided.
DFP
Supply to the core
DRP
Note: Either VBUS
or VSYS can be
provided.
DFP
Supply to the
analog blocks in
chip
CCG3
Supply to the I/Os
NA
NA
4.0 V to 5.5 V
1 µF
4.0 V to 21.5 V
1 µF
2.7 V to 5.5 V
1 µF
VDDD is an output pin, which is
intelligently switched between
output of the VBUS regulator
and unregulated VSYS.
1 µF
UFP
UFP
DRP
DFP
UFP
DRP
VDDIO
4.0 V to 5.5 V
UFP
Cable
VBUS
NA
DFP
UFP
1.71 V to VDDD
Note that, VDDIO pin can be
shorted to VDDD pin.
VCCD
The core voltage of the device is brought out to the pin. This pin
cannot be used as voltage source and is intended to connect only
a decoupling capacitor.
V5V
Supply to power
VCONN FETs
1 µF
1 µF
DRP
DFP
2.7 V to 5.5 V
1 µF
UFP
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Document No. 002-10403 Rev. **
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Type-C and PD
Controller
Power
Supply Pin
VDDD
Power Supply
Domain
Supply to the core
Role
Value of Bypass
Capacitor to GND
Valid Input Voltage Level
DRP
3.0 V to 5.5 V
DFP
3.0 V to 5.5 V
UFP
2.7 V to 5.5 V
1 µF
DRP
VDDIO
Supply to I/Os
DFP
1.71 V to VDDD
1 µF
UFP
CCG4
VCCD
The core voltage of the device is brought out to the pin. This pin
cannot be used as voltage source and is intended to connect only
a decoupling capacitor.
V5V_P1 and
V5V_P2
Supply to power
VCONN FETs
0.1 µF
DRP
DFP
4.85 V to 5.5 V
0.1 µF
UFP
www.cypress.com
Document No. 002-10403 Rev. **
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
4
Dual Type-C Port DRP Application Using CCG4
CCG4 controller (CYPD4225-40LQXIT) is used here as a reference.
CCG4 integrates two Type-C transceivers and facilitates a dual Type-C port notebook design with a reduced BOM
compared to CCG2 and CCG3, which integrate only one Type-C transceiver. In this application, both Type-C ports
can be either power providers or power consumers at the same or different times. Similarly, both Type-C ports can
play the role of DFP or DRP at any point of time. Figure 4 shows the logical connections between CCG4 and the
components in a notebook design.
Figure 4. Dual Type-C Port Notebook Design Using CCG4
VBUS_SOURCE
2 x FETs
and Gate
Driver
5
2 x FETs
and Gate
Driver
DC/DC
VBUS_SOURCE
4
BAT
2 x FETs
and Gate
Driver
VBUS_SINK
BCC
I2 C
VBUS_MON_P2
VBUS_P
_CTRL_
P1
CC1_2, CC2_2
VBUS_MON_P1
1
2
VBUS_P VBUS_C
_CTRL_ _CTRL_
P2
P2
I2 C
2
CC1_1, CC2_1
EZ-PD ™ CCG4
2
USB Type-C
Receptacle
For Port 2
V5V_2
V5V_1
HPD_2
I2 C
HPD_1
USB Type-C
Receptacle
For Port 1
2
EC
VBUS_C
_CTRL_
P1
2 x FETs VBUS_SINK
and Gate
Driver
2
2 I2 C
VCONN
Supply
DP/DM
2
6
SS
3
3
8
AUX
SBU
2
1] BCC - Battery Charge Controller
2] EC - Embedded Controller
3] ML – Main Link
4] BAT – Battery
5] DC/DC – DC to DC Converter
6] SS -- SuperSpeed
2
6
4
6
DISPLAY
PORT
CONTROLLER
8
AUX
2
3
SS / ML_LANES
ML_LANES
HPD_2
MUX
2
SS
3
ML_LANES
SS / ML LANES
8
4
HPD_1
6
DP/DM
USB 3.1 HOST
CONTROLLER
MUX
8
SBU
2
Critical sections of the dual Type-C notebook design using CCG4 are described below:



Power Supply Design
I2C Communication with Embedded Controller
Dead Battery Charging
www.cypress.com
Document No. 002-10403 Rev. **
10
Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers



Power Provider or Consumer (DRP) Role
Display Port Connections
Electrical Design Considerations
Cypress provides the CY4541 EZ-PD CCG4 EVK (Evaluation Kit) to evaluate the dual Type-C notebook design using
CCG4 as shown in Figure 5. A notebook or a PC with two USB 3.0 ports and a DisplayPort along with the CY4541
EZ-PD CCG4 EVK is equivalent to a PD-enabled dual Type-C-port notebook. The CY4541 EZ-PD CCG4 EVK
consists of two CCG base boards and one CCG4 daughter card. See section 3.1 of the CY4541 EZ-PD CCG4 EVK
kit guide for more details on kit architecture.
Figure 5. CY4541 EZ-PD CCG4 EVK
CCG Base Board 1
4.1
CCG4
Daughter Card CCG Base Board 2
Power Supply Design
Cypress’s Type-C PD Controller CCG4 operates with two supply voltages; the voltage supply VDDD powers the device
core and two Type-C transceivers. The VDDIO supply powers the device I/Os as referred in Table 8. CCG4 has an
integrated voltage regulator as shown in Figure 6. VCCD is the output voltage from the core regulator and this pin is
intended to connect only a decoupling capacitor. The VCCD pin cannot be used as a voltage source. CCG4 has
power supply inputs V5V_P1 and V5V_P2 pins for providing power to EMCA cables through integrated VCONN
FETs. There are two VCONN FETs in CCG4 per Type-C port to power CC1_P1/P2 and CC2_P1/P2 pins. These
FETs are capable of providing a minimum of 1 W on the CC1 and CC2 pins for EMCA cables.
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Figure 6. CCG4 Power Subsystem
CC1_P2
CC2_P2
V5V_P2
CC1_P1
CC2_P1
VDDD
V5V_P1
Core Regulator
(SRSS-Lite)
VDDIO
VCCD
GPIOs
2 x CC
Tx/Rx
Core
VSS
Table 8. CCG4 Operating Voltage Range
4.1.1
Parameter
Min
(V)
Typical
(V)
Max
(V)
VDDD
3
--
5.5
VDDIO
1.71
--
VDDD
V5V_P1
4.85
--
5.5
V5V_P2
4.85
--
5.5
D e c o u p l i n g C a p a c i t o r s i n P o w e r S u b s ys t e m
Power supply noise can be suppressed by using decoupling capacitors to power supply pins VDDD, VDDIO, VCCD,
V5V_P1, and V5V_P2 as shown in Figure 7. A 330-pF decoupling capacitor should also be connected to the CC lines
(CC1_P1, CC2_P1, CC1_P2, and CC2_P2) to maintain the signal quality at the signaling rate of 300 kHz.
Figure 7. Noise Suppression Using Decoupling Capacitors
31
V5V_P1
VDDD
1uF C23
8
0.1uF C45
32
1uF C26
VDDIO
V5V_P2
C24
C48
0.1uF C28
1uF C46
CC1_P1 7
33
0.1uF
1uF
23
0.1uF C44
VCCD
0.1uF C27
EZ-PD™ CCG4
330pF C41
9
CC2_P1
330pF C42
VDDIO
100 KΩ R68
1uF
10
XRES
CC1_P2
24
C29
330pF C39
22
CC2_P2
330pF C40
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
4.1.2
Reset and Clock
CCG4 supports a power-on-reset (POR) mechanism and it also has an active LOW external reset (XRES) pin The
XRES pin can be used by external devices to reset the CCG4 device. The XRES pin should be held LOW for a
minimum of 1 µs to reset the CCG4 device. This XRES pin should be tied through an RC circuit as shown in Figure 7.
The recommended values for R and C are 100 kΩ and 1 µF respectively to meet the 1-µs pulse-width requirement,
CCG4 has integrated clock circuitry and any external components such as a crystal or oscillator are not required.
4.2
I2C Communication with Embedded Controller
This section is applicable to CCG2, CCG3, and CCG4 devices.
2
Serial Communication Blocks (SCBs) in CCG2, CCG3, and CCG4 can be reconfigured as I C
(master/slave)/UART/SPI (master/slave). In a typical notebook design, the internal battery’s charging or discharging
is controlled by the Battery Charger Controller (BCC), which is managed by the Embedded Controller (EC). The
2
CCG2/CCG3/CCG4 device is interfaced with the EC over I C as shown in Figure 8.
Consider a scenario in which a Type-C port in a notebook is capable of providing 5 V at 3 A to a connected device
when the battery is full. If the charge in the battery goes below a threshold level, then the EC communicates with the
2
CCG2/CCG3/CCG4 device over the I C interface to negotiate the current (for example, 5 V, 900 mA) with the
connected device.
2
Figure 8. Connection Between CCG Device I C Lines and Embedded Controller
VDDIO
2.2 kΩ
2.2 kΩ
2.2 kΩ
Embedded
Controller
I2C_INT
I2C_SCL
I2C_SDA
GPIO
I2C_SCL
EZ-PD™ CCG2/3/4
I2C_SDA
The SCL and SDA lines are required to be pulled up with a 2.2-kΩ resistor. While any CCG2 device’s GPIO can be
2
configured as an I C interrupt pin, care should be taken to ensure that the application firmware and bootloader utilize
2
the same GPIO as an interrupt pin. Pin#15 of the CCG4 device is a fixed-function I/O, which is configured as an I C
2
interrupt pin. The application firmware running on the CCG2/CCG3/CCG4 device (I C slave) triggers the interrupt line
LOW to indicate the start of a Type-C or PD event (for example, Type-C port connect or disconnect, power role swap
2
from provider to consumer, and so on) to the EC (I C master).
2
In the CY4541 EZ-PD CCG4 EVK, the CCG4 device’s I C lines are present on jumper headers J9 and J10 on the
CCG baseboards. See the CY4541 CCG EVK baseboard schematics for details.
2
Note: See the respective Type-C and PD controller’s datasheet to learn more about the I C pin numbers for each
SCB.
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
4.3
Dead Battery Charging
This section is applicable to CCG2, CCG3, and CCG4 devices.
If the battery of a Type-C notebook design using a CCG2/CCG3/CCG4 device is completely dead, it can still be
charged by connecting a DFP (such as a power adapter) or DRPs (such as a monitor or external hard disk) to its
Type-C port.
By default, a DFP or DRP presents an Rp resistor. Upon connection, the CC line on the CCG2/CCG3/CCG4 device
in a notebook with a dead battery is pulled HIGH. This turns FET Q2 ON through resistor R1, and the
CCG2/CCG3/CCG4 device (in the notebook with the dead battery) presents a dead battery Rd resistor on the CC line
(CC1 and CC2), as shown in Figure 9.
Figure 9. Dead Battery Charging of Type-C Notebook
VBUS
Rp
CC
CC
Rd
R1
1 MΩ
Q2
To MCU
Q1
EZ-PD™ CCG2/3/4
Dead Battery Notebook
DFP or DRP
By presenting the Rd resistor, a Type-C connection is established between the CCG2/CCG3/CCG4 device (in the
notebook with the dead battery) and the DFP or DRP. Now, the notebook with the dead battery is a power consumer
and receives a default 5 V on VBUS, which charges the dead battery. FET Q1 is turned OFF once the
CCG2/CCG3/CCG4 device is powered. After 5 V is available on VBUS, the CCG2/CCG3/CCG4 device in the
notebook is powered and starts negotiating with the connected DFP or charging UFP for a higher VBUS, depending
on the application configuration.
CCG3 and CCG4 have integrated dead battery termination resistors (Rd) on both CC1 and CC2 lines. CCG2 has an
integrated termination resistor (Rd) on the CC2 line and a dedicated RD1 resistor pin that needs to be shorted with
the CC1 line of CCG2. The dead battery Rd resistors are disabled by the application firmware once the device is
powered up. CCG2/CCG3/CCG4 devices have internal active Rd terminations that are used after the dead battery Rd
resistors are disabled.
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Document No. 002-10403 Rev. **
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Dead battery charging of CCG4 can be demonstrated by using the CY4541 EZ-PD CCG4 EVK as shown in Figure
10. See Chapter 4 (DRP Kit Operation) of the CY4541 EZ-PD CCG4 EVK kit guide for details on hardware
connections of this setup.
Figure 10. Dead Battery Charging Demo Using CY4541 EZ-PD CCG4 EVK
USB
J12
J7
Type-C Power Adapter
Connected to CCG
Base Board 1
J3
Type-C Port 1
J3
J12
J7
Type-C Port 2
SuperSpeed Type-A to Type-B
Cable connected to
CCG Base Board 2
A notebook or a PC with two USB 3.0 ports along with the CY4541 EZ-PD CCG4 EVK is equivalent to a PD-enabled
dual Type-C port notebook. Because a DC power adapter is not connected to the EVK, the onboard CCG4 is not
powered, which emulates a dual-Type-C notebook with dead battery. CCG4 can be powered by connecting a Type-C
power adapter to one of the EVK’s Type-C ports as shown in Figure 10. Once CCG4 in the EVK is powered, it
establishes a power contract with the Type-C power adapter and starts consuming power. This can be verified by
connecting a digital multimeter to the power output header (J7) of the CCG base board (where the Type-C power
adapter is connected) to measure the output voltage in the dead-battery charging scenario. This demonstrates that a
CCG4-enabled dual Type-C notebook can be charged even from a dead battery condition.
4.4
Power Provider/Consumer Role
This section explains the recommended external hardware circuitry for VBUS control, and overvoltage and
overcurrent protection in a notebook design. This applies only to CCG2 and CCG4 devices because CCG3 has
integrated gate drivers to control VBUS and a 20-V tolerant VBUS regulator for overvoltage and overcurrent
protection. Refer to the section 6.4 Power Provider/Consumer role for CCG3.
A notebook design using a CCG2/CCG4 device is a power provider when running from its internal battery and a
power consumer when being charged from a DFP (such as a power adapter) or a DRP (such as a monitor or
external, self-powered hard disc).
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Document No. 002-10403 Rev. **
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
4.4.1
C o n t r o l o f V B U S P r o vi d e r P a t h a n d V B U S C o n s u m e r P a t h
A Battery Charger Controller (BCC) controls the charging (sinking of VBUS) or discharging (sourcing of VBUS) of the
battery. A CCG2/CCG4 device consists of two I/Os per Type-C port, namely, VBUS_P_CTRL and VBUS_C_CTRL,
to control the VBUS provider (sourcing of power) or consumer (sinking of power) path connected to the BCC. Figure
11 shows the recommended implementation of FETs to control this VBUS path.
Figure 11. VBUS Provider and Consumer Path Control
BATTERY
CHARGER
CONTROLLER
VBUS_SINK
(VBUS CONSUMER PATH)
Current Flow
VBUS_SOURCE
(VBUS PROVIDER PATH)
Current Flow
Q2A
Q2B
DC/DC CONVERTER
4.7 uF
49.9KΩ
100 KΩ
10 Ω
VBUS_C_CTRL_P1
OVP_TRIP_P1
OVP_TRIP
Q6A
100 KΩ
Q16A
10 Ω
100 KΩ
Q1A
Q1B
VBUS (5-20V)
VBUS
VBUS
EZ-PD™ CCG2/4
100KΩ
10KΩ
VBUS_P_CTRL_P1
Q16B
Rd
Rd
4.7 uF
100 KΩ
10 Ω
Vx
VBUS_MON
49.9KΩ
0.1 μF
100 KΩ
TYPE-C PORT
100 KΩ
VBUS_P_CTRL_P1
10 Ω
4.7 uF
Q6B
100 KΩ
VBUS_P_CTRL_P1
200Ω
VBUS_DISCHARGE_P1 10 Ω
VBUS_C_CTRL_P1
VBUS_DISCHARGE_P1
VBUS_C_CTRL_P1
Q5
100 KΩ
VBUS_DISCHARGE_P1
VBUS_C_CTRL and VBUS_P_CTRL are active HIGH pins. As shown in Figure 11, when VBUS_C_CTRL is LOW,
FET Q6A turns OFF. This FET controls Q2A and Q2B, and turns them OFF. Thus, a CCG2/CCG4 device will not be
able to consume power from the DFP or charging UFP, as its power consumer path is OFF. When VBUS_C_CTRL is
HIGH, FET Q6A is ON, which turns ON FETs Q2A and Q2B, and thus the VBUS consumer path is ON.
When the VBUS_P_CTRL pin is HIGH, FETs Q6B, Q1A, and Q1B are ON, and thus the VBUS provider path turns
ON. When VBUS_P_CTRL is LOW, FETs Q6B, Q1A, and Q1B are OFF.
The diodes between the source and drain terminals of FETs Q2A and Q2B turn OFF the VBUS consumer path
completely when the VBUS provider path is active. Similarly, the diodes between the source and drain terminals of
FETs Q1A and Q1B turn OFF the VBUS provider path completely when the VBUS consumer path is active. This
capability of CCG4 to switch the power role from provider to consumer or vice-a-versa can be demonstrated by using
the CY4541 EZ-PD CCG4 EVK as shown in the Figure 11. The CY4541 EZ-PD CCG4 EVK along with a USB 3.0enabled notebook or a PC emulates a CCG4-enabled Type-C notebook. See Chapter 4 (DRP Kit Operation) of the
CY4541 EZ-PD CCG4 EVK kit guide for details on hardware connections of this setup.
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Document No. 002-10403 Rev. **
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Figure 12. Switching Between Power Provider and Power Consumer Roles of CCG4 Using CY4541 EZ-PD CCG4 EVK
(Example 1)
USB
J12
J7
Type-C Power Adapter
Connected to CCG
Base Board 1
J3
Type-C Port 1
Type-C to
Type-A Dongle USB Pen-drive
J3
J12
J7
Type-C Port 2
SuperSpeed Type-A to Type-B
Cable connected to
CCG Base Board 2
As shown in Figure 12, when the Type-C power adapter is connected to Type-C port 1 of the CY4541 EZ-PD CCG4
EVK, CCG4 starts consuming power from the Type-C power adapter. This can be verified by measuring the voltage
on the power output header (J7) of the CCG base board 1 (where the Type-C power adapter is connected) using a
digital multimeter. This emulates the charging of a CCG4-enabled Type-C notebook in which the Type-C port 1 of the
notebook consumes power from the power adapter to charge its internal battery. However, if a USB pen drive is
connected to the Type-C port 2 of the CCG4-enabled Type-C notebook, the CCG4 device provides negotiated power
to the connected USB pen drive from the Type-C power adapter. In this scenario, the Type-C port 1 of the CCG4
enabled notebook is a power consumer and Type-C port 2 is a power provider.
www.cypress.com
Document No. 002-10403 Rev. **
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Figure 13. Switching Between Power Provider and Power Consumer Roles of CCG4 Using CY4541 EZ-PD CCG4 EVK
(Example 2)
USB
SuperSpeed Type-A to Type-B
Cable connected to
CCG Base Board 1
J7
USB Pen-drive
J12
Type-C to
Type-A Dongle
Type-C Power Adapter
Connected to CCG
Base Board 2
J3
Type-C Port 1 J12
J3
J7
Type-C Port 2
The Type-C power adapter and a USB pen drive can be interchanged between Type-C port 1 and Type-C port 2 as
shown in Figure 13. In this scenario, the Type-C port 1 of the CCG4-enabled notebook provides power to the USB
pen drive and Type-C port 2 consumes power from Type-C power adapter. In this scenario, the Type-C port 1 of the
CCG4-enabled notebook is a power provider and Type-C port 2 is a power consumer. This demonstrates that CCG4
can switch its power role from provider to consumer and vice-versa.
4.4.2
Control of VBUS Discharge Path
This section explains the critical need of the VBUS discharge circuitry. Depending on the connected downstream
device, the VBUS voltage varies as illustrated by the following example scenarios:

Example scenario 1: A UFP device sinking 100 W of power (20 V, 5 A) is disconnected from a Type-C port, and
immediately another UFP device sinking 25 W of power (5 V, 5 A) is connected to the same Type-C port.

Example scenario 2: A notebook changes its power role from provider (sourcing 100 W of power) to consumer
(sinking 45 W of power).
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Document No. 002-10403 Rev. **
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Figure 14. VBUS Discharge Control Circuitry
VBUS (5-20V)
VBUS
EZ-PD™ CCG2/4
TYPE-C PORT
200 Ω,
3W
R16
4.7 uF
Q5
VBUS_
DISCHARGE_P1
100 KΩ
R19
In scenario 1, the VBUS capacitor shown in Figure 14 may not have discharged fully from the original 20 V when the
second UFP device is connected. This could cause an overvoltage on the second UFP device, which requires 5 V on
VBUS.
In scenario 2, a similar overvoltage could occur when the power role is swapped.
To prevent this scenario, the CCG2/CCG4 device provides a discharge path to the VBUS capacitor by triggering the
VBUS Discharge pin. VBUS Discharge is an active HIGH signal, which turns ON FET Q5 causing a discharge of the
VBUS capacitor through a resistor as shown in Figure 14. It is necessary to use a series resistor (200 Ω) with a
minimum 2.5-W power rating, as the power dissipation during VBUS discharge is high.
VBUS discharge circuitry is implemented in CY4541 the CCG4 EVK as shown in Figure 14. See CY4541 EZ-PD
CCG4 Daughter Board schematics for details.
4.4.3
O ve r vo l t a g e P r o t e c t i o n ( O V P ) f o r V B U S
Overvoltage Protection (OVP) circuitry is required on VBUS to prevent damage to the system if VBUS exceeds the
maximum voltage negotiated by the CCG2/CCG4 controller.
OVP for CCG4:
Figure 15 shows the external circuitry required to monitor the VBUS in a notebook design using CCG4.
Figure 15. OVP/UVP Circuitry
VBUS
EZ-PD™ CCG4
100 KΩ
R63
Rd
Vx
VBUS_MON
10 KΩ
R66
C34
Rd
0.1 μF
Per the USB PD specification, the maximum voltage at VBUS can be 20 V. Table 9 provides the value of voltage VX
(shown in Figure 15) and OVP trip voltage (1.2 times Vx) for the possible VBUS voltages.
Table 9. Values of Vx Voltage at Different VBUS Voltages
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VBUS Voltage (V)
VX Voltage (V)
OVP Trip Voltage (V)
4
0.363
0.435
5
0.454
0.544
9
0.818
0.981
15
1.363
1.635
20
1.818
2.181
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
A CCG4 device has a built-in comparator. The VBUS_MON pin is an input to the comparator as shown in Figure 15.
CCG4 device’s firmware configures the OVP trip voltage for the respective negotiated VBUS voltage (defined in
Table 9) as the second input of the comparator. The comparator compares the Vx voltage with OVP trip voltage for
the respective VBUS voltage, as shown in Table 9. The capacitor (0.1 µF) on the VBUS_MON pin (Figure 15) acts as
a low-pass filter and prevents glitches on the ADC input pin.
Consider a scenario in which the notebook and the DFP device connected to its Type-C port establish a power
contract, and the notebook starts receiving 15 V of VBUS from the DFP. The voltage generated at the VBUS_MON
pin would be 1.363 V, which is an input to the CCG4 device’s comparator. The CCG4 device’s firmware sets the OVP
trip voltage to 1.635 V for the 15-V VBUS. The comparator compares this OVP trip voltage with the Vx voltage
(1.363 V for the 15-V VBUS, as listed in Table 9). The output of the comparator is connected to one of the CCG4
device’s fixed-function I/O, which is called the OVP trip pin (OVP_TRIP_P1) as shown in Figure 11. This pin becomes
LOW in the overvoltage scenario (if Vx exceeds the OVP trip voltage), and the CCG4 device turns OFF the VBUS
consumer path by turning OFF FETs Q2A and Q2B as shown in Figure 11. The CCG4 device also disconnects itself
from the Type-C port.
The overvoltage protection feature is implemented in the CY4541 EZ-PD CCG4 EVK as shown in Figure 15. See
CY4541 EZ-PD CCG4 EVK Daughter Board schematics for more details.
OVP for CCG2:
Figure 18 shows the implementation of OVP for the 5-V VBUS using a comparator IC (LM339) for CCG2. Input 1 of
the comparator IC is the negotiated VBUS voltage through a resistor divider network. Per the circuit shown in Figure
16, this voltage is 0.454 V for the 5-V VBUS through the resistor divider network. Input 2 of the comparator IC is the
OVP trip voltage, which is set based on the overvoltage limit of the system. For example, a system may have an
overvoltage limit of 5.5 V. Accordingly, the resistor divider circuit at input 2 terminal generates 0.5 V for 5.5 V VBUS,
which gets compared with the voltage at input 1 terminal (0.454 V for 5 V VBUS) of the comparator IC. The 5 V
voltage supply to the resistor divider circuitry at input 2 terminal is an output voltage of the 5 V VBAT regulator in the
system. VBAT is the battery voltage, which comes from the internal battery in a notebook. The output of the
comparator is connected to one of the CCG2’s I/O, which is configurable in FW. See the firmware configuration and
programming details on EZ-PD™ CCG2 Firmware webpage. This I/O becomes LOW in the overvoltage scenario, and
the CCG2 device turns OFF VBUS by turning OFF the power consumer FETs Q2A and Q2B as shown in Figure 11.
The CCG2 also disconnects itself from the Type-C port.
The LM339 voltage comparator outputs a logic LOW or high-impedance (logic HIGH with pull-up) based on the input
differential polarity. Thus, a 10-kΩ pull-up resistor needs to be connected on output terminal of LM339 comparator IC.
See the LM339 datasheet for further details.
Figure 16. External Hardware Required for OVP
5V
100 KΩ
Rd
10
RdKΩ
11 KΩ
Rd
OVP_DET
(Connect to
CCG2's GPIO)
INPUT 2
VBUS
100 KΩ
Rd
OUTPUT 1
COMPARATOR
INPUT 1
10 KΩ
Rd
LM339
4.4.4
Undervoltage Protection (UVP) for VBUS
Undervoltage Protection (UVP) circuitry is required on VBUS to detect a Type-C disconnect event when a
CCG2/CCG4-enabled notebook is consuming power from the DFP (such as a power adapter) or charging UFP (such
as a monitor or external hard disk) over the Type-C interface.
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
UVP for CCG4:
Figure 15 shows the external RC circuitry required to implement this feature for VBUS in a notebook design using
CCG4 (the same circuit as used for OVP). The voltage generated at the VBUS_MON pin is an input to two built-in
CCG4 comparators, which facilitate both UVP and OVP at the same time. The first comparator is used for OVP
whereas the second comparator is used for UVP. The CCG4 device’s firmware configures the UVP trip voltage as the
second input of the UVP comparator. Existing CCG4 FW implements UVP only for 5-V VBUS. The UVP trip voltage
for 5-V VBUS is set to 4 V (0.8 times VBUS).
Consider a scenario in which the notebook and the DFP device connected to its Type-C port establish a power
contract, and the notebook starts receiving 5 V of VBUS from the DFP. The voltage generated at the VBUS_MON pin
would be 0.454 V (Vx, as defined in Table 9), which is the first input to the CCG4 device’s UVP comparator. The
CCG4 device’s firmware has set the VBUS undervoltage detection threshold to 4 V. The value of Vx for 4-V VBUS
would be 0.363 V (as defined in Table 9), which is configured by the CCG4 device’s firmware as the UVP trip voltage.
This UVP trip voltage is the second input to the UVP comparator. The UVP comparator compares this UVP trip
voltage (0.363 V) with the Vx voltage for the 5-V VBUS (0.454 V, as listed in Table 9). The output of the
comparator is connected to one of the CCG4’s device’s fixed-function I/Os, which is called the VBUS_C_CTRL_P1
pin as shown in Figure 11. This I/O becomes LOW in the undervoltage scenario (if VBUS goes below 4 V), and the
CCG4 device turns OFF the VBUS consumer path by turning OFF FETs Q2A and Q2B as shown in Figure 11. The
CCG4 device also disconnects itself from the Type-C port.
The capacitor (0.1 µF) on the VBUS_MON pin (Figure 15) acts as a low-pass filter and prevents glitches on the ADC
input pin.
The undervoltage detection feature is implemented in the CY4541 EZ-PD CCG4 EVK as shown in Figure 15. See
CY4541 EZ-PD CCG4 EVK Daughter Board schematics for more details.
UVP for CCG2:
Figure 18 shows the implementation of UVP using a comparator IC (LM339) for CCG2. Input 2 of the comparator IC
is the negotiated Type-C VBUS voltage through a resistor divider network. Existing CCG2 FW implements UVP only
for 5-V VBUS. Per the circuit shown in the Figure 17, this voltage is 0.45 V for the 5-V VBUS through the resistor
divider network. The CCG2 device’s firmware has set the VBUS undervoltage detection threshold to 4 V. Input 1 of
the comparator IC is the UVP trip voltage, which is 0.3636 V for the 4-V VBUS through a resistor divider network. The
5-V supply to the resistor divider circuitry at input 2 terminal is an output voltage of the 5-V VBAT regulator in a system.
VBAT is the battery voltage, which comes from the internal battery in a notebook design. The comparator IC compares
this UVP trip voltage (0.3636 V for the 4-V VBUS) with the voltage at input 2 terminal (0.45 V for the 5-V VBUS). The
output of the comparator is connected to one of the CCG2’s I/Os, which is configurable in firmware. See the firmware
configuration and programming details on EZ-PD™ CCG2 Firmware webpage. This I/O becomes LOW in the
undervoltage scenario, and the CCG2 device turns OFF VBUS by turning OFF power consumer FETs Q2A and Q2B
as shown in Figure 11. The CCG2 device also disconnects itself from the Type-C port.
The LM339 voltage comparator outputs a logic LOW or high-impedance (logic HIGH with pull-up) based on the input
differential polarity. Thus, a 10-kΩ pull-up resistor needs to be connected on output terminal of the LM339 comparator
IC. See the LM339 datasheet for further details.
Figure 17. External Hardware Required for UVP
VBUS
100 KΩ
Rd
10
RdKΩ
10 KΩ
Rd
OVP_DET
(Connect to
CCG2's GPIO)
INPUT 2
5V
100 KΩ
Rd
OUTPUT 1
COMPARATOR
INPUT 1
8 KΩ
Rd
LM339
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
4.4.5
O ve r c u r r e n t P r o t e c t i o n ( O C P ) f o r V B U S
Overcurrent protection (OCP) circuitry is required on VBUS to prevent damage to the system if the VBUS current
exceeds the maximum current negotiated by the CCG2/CCG4 controller. Figure 18 shows the external components
(current sense monitor and comparator) required to implement OCP for VBUS in a notebook design using
CCG2/CCG4. Refer to section 6.4.4 for OCP implementation in CCG3.
Figure 18. OCP Circuitry
5V
100 KΩ
Rd
10
RdKΩ
75 KΩ
Rd
VBUS_SOURCE
(VBUS PROVIDER PATH)
S+
DC/DC CONVERTER
Rsense
10 mΩ,
2W
Rd
10 pF
S-
OCP_DET
(Connect to
CCG2/4's GPIO)
INPUT 2
CURRENT
SENSE
MONITOR
OUT
INPUT 1
12.4 KΩ
Rd
OUTPUT 1
COMPARATOR
270 pF
TSX3702IQ2T
ZXCT1109
OVP_TRIP_P1
OVP_TRIP
VBUS
EZ-PD™ CCG2/4
Q16B
VBUS
100KΩ
10 Ω
Rd
100 KΩ
Vx
VBUS_MON
10KΩ
Rd
Q1A
Q1B
VBUS (5-20V)
49.9KΩ
4.7 uF
100 KΩ
TYPE-C PORT
100 KΩ
VBUS_P_CTRL_P1
10 Ω
4.7 uF
Q6B
100 KΩ
0.1 μF
200Ω
VBUS_DISCHARGE_P1 10 Ω
VBUS_DISCHARGE_P1
Q5
100 KΩ
VBUS_DISCHARGE_P1
The Rsense resistor connected between the S+ and S- terminals of the current sense monitor IC converts the current
through the Rsense resistor into a voltage to be measured by the comparator. The comparator IC compares the
output voltage from the current sense monitor IC with the reference voltage set using resistor divider circuitry at input
2 terminal. This reference voltage is set based upon the OCP limit of the system. The circuit shown in Figure 18 has
set the OCP to 5.35 A with 100-kΩ and 75-kΩ resistor divider circuitry at input 2 terminal. See the respective
datasheet of the comparator to choose the appropriate resistor and capacitor values, which define the reference
voltage and OCP current limit. The 5-V supply to the resistor divider circuitry at input 2 terminal is an output voltage of
the 5-V VBAT regulator in a system. VBAT is the battery voltage, which comes from the internal battery in a notebook.
The output of the comparator is connected to one of the CCG2/CCG4’s I/Os, which is configurable in firmware. For
CCG4, this is a fixed-function I/O, which is called OCP_DET_P1. For CCG2, see the firmware configuration and
programming details on EZ-PD™ CCG2 Firmware webpage. This I/O becomes LOW in the overcurrent scenario and
the CCG2/CCG4 device turns OFF the VBUS by turning OFF power provider FETs Q1A and Q1B as shown in Figure
11. The CCG2/CCG4 also disconnects itself from the Type-C port.
Figure 18 shows a reference schematic of the OCP circuitry using a current sense monitor IC (ZXCT1109) and a
comparator (TSX3702IQ2T). The voltage comparator outputs a logic LOW or high-impedance (logic HIGH with pullup) based on the input differential polarity. Thus, a pull-up resistor needs to be connected on output terminal of the
voltage comparator IC. See the datasheet of current sense monitor IC and voltage comparator for further details.
The overcurrent protection feature on the CCG4 daughter card is implemented using current a sense monitor IC
(ZXCT1109) and comparator (TSX3702IQ2T) as shown in Figure 18. See the CY4541 EZ-PD CCG4 EVK Daughter
Board schematic for more details.
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
4.4.6
O ve r c u r r e n t P r o t e c t i o n ( O C P ) f o r V C O N N
In a notebook design, VCONN supplies power to the electronically marked cable attached to it. VCONN FETs on the
CC lines can handle a current up to 0.5 A. Overcurrent Protection (OCP) circuitry is required on VCONN to prevent
damage to the system if VCONN current exceeds 0.5 A. Figure 19 shows the external components required to
implement OCP for VCONN in a notebook design using CCG2/CCG3/CCG4.
Figure 19. OCP for VCONN
5V
VIN
EN
Rd
10 KΩ
4.7 uF
VOUT
VCONN/V5V
POWER
SWITCH-0.5A
FLAG
GND
EZ-PD™ CCG2/3/4
1 uF
AP2822AKATR-G1
The VCONN power switch (AP2822AKATR-G1) has an overcurrent detection limit of 0.5 A. Output of the switch
(VOUT) is connected to VCONN of CCG2/CCG3 or V5V_P1 or V5V_P2 of CCG4. The 5-V supply (VIN) to the
VCONN power switch is an output voltage of the 5-V VBAT regulator in a system. VBAT is the battery voltage, which
comes from the internal battery in a notebook. If VCONN current exceeds the overcurrent detection limit of 0.5 A,
VOUT (5 V) power supply is shut down by the power switch, preventing any damage to the system. See the
respective datasheet of the power switch to choose the appropriate resistor and capacitor values.
4.5
DisplayPort Connections
This section is applicable only to the dual Type-C port CCG4 controller (CY4225-40LQXIT) for notebook application.
Type-C is a versatile connector, which also supports DisplayPort signals by repurposing one of the SuperSpeed
lanes and two sideband signals. These repurposed signals act in a new mode, called “alternate mode.” One example
of using a Type-C interconnection in alternate mode is DisplayPort. See the VESA specification for more details on
DisplayPort Alt Mode on the USB Type-C Standard.
In a Type-C notebook design, a display monitor can be connected directly to the notebook over the Type-C interface
using a CCG4 and a display mux controller. Figure 20 shows the connections between CCG4 and two display mux
controllers in a notebook design having two USB 3.0 Host controllers and one DisplayPort Source.
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Figure 20. CCG4 and Dual Display Mux Controller Connections
DP/DM
USB 3.0 Host
Controller
2
1
SS Lanes
4
Tx/Rx
3
ML Lanes
8
Display Mux
(PS8740B)
SBU
8
5
2
Type-C
Port 1
CC 2
2
AUX Lanes
HPD
2
4
I2C 2
3
ML Lanes
Display Port
Source
HPD
2
AUX Lanes
8
2
Display Splitter
EZ-PD™ CCG4
4
2
I2C
HPD
3
ML Lanes
4
CC 2
8
2
AUX Lanes
1
SS Lanes
USB 3.0 Host
Controller
2
Tx/Rx
Display Mux
(PS8740B)
4
DP/DM
SBU
8
5
2
Type-C
Port 2
2
1] SS – SuperSpeed
2] ML Lanes – Main Link
3] AUX Lines – Auxilliary Lines
4] HPD – Hot Plug Detect
5] SBU – Side Band Use
Whenever a display monitor is connected to the Type-C port on a notebook, CCG4 discovers that it has a device
attached with alternate mode supported. Through PD communication, CCG4 identifies the display monitor’s Standard
ID (SID) or Vendor ID (VID) (so SVID = SID or VID). The display monitor reports an SVID of 0xFF01 (per the VESA
specification), which is assigned to a DisplayPort connection.
CCG4 initiates an alternate mode sequence and asserts the Hot Plug Detect (HPD) signal to the DisplayPort source
and display mux controller. The DisplayPort source detects that the display monitor is connected to the notebook.
The display monitor can have two or four Main Link (Display Port) lanes. The 2-lane Main Link configuration supports
a raw bit rate up to 10.8 Gbps, and the 4-lane Main Link configuration supports a raw bit rate up to 21.6 Gbps.
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
CCG4 checks the DisplayPort status, and if it receives an ACK, CCG4 configures the display mux controller in either
2
2-lane or 4-lane mode. CCG4 communicates with the display mux controller either over the I C interface (such as the
display mux controller from Parade, PS8740B) or over a GPIO interface (such as the display mux controller from
Pericom, PI3DBS12412AZHE), depending on the type of display mux controller used in the system. See the
respective mux controller’s datasheet for more details.
The display mux controller switches its output lines (TX/RX) between the USB SuperSpeed lanes and the Main Link
(Display Port) lanes from the DisplayPort source.
Consider a scenario in which a 4-lane display monitor is connected to the notebook, and no other USB 3.0 device is
connected. In this case, the display mux controller connects four Main Link (Display Port) lanes to the Type-C port,
and the display appears on the screen. Now if a USB 3.0 device is connected to the notebook, it enumerates as a
USB 2.0 device because all the SuperSpeed lanes on the Type-C port are repurposed as DisplayPort lanes. USB 2.0
enumeration occurs because USB 2.0 (DP/DM) lines are directly connected from the USB Host controller to the
Type-C port.
The USB Host controller detects the presence of the SuperSpeed device (enumerated as a USB 2.0 device) and
communicates it to the EC. The system may decide to switch from 4-lane to 2-lane display to enable SuperSpeed
device enumeration or it may continue to be in 4-lane mode. This is implementation-specific. If the system wants to
switch to 2-lane mode, the EC sends a message to CCG4 to reconfigure the display mux controller from 4-lane to 2lane display mode to enable connection of the USB SuperSpeed lane to the Type-C port. Now, the display appears
on the monitor, and the USB 3.0 device is detected as a SuperSpeed device. Note that the display monitor’s
resolution in the 2-lane mode will be lower than in the 4-lane mode. The Type-C port also receives auxiliary signals
from the DisplayPort Source through the display mux controller that carry either the audio signals or the control
signals for display.
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
The recommended part for display mux controller with redriver circuitry is from Parade Technologies (PS8740B),
which compensates for the PC board, connector, and cable losses and maintains signal quality by adjusting the gain
of the redriver circuitry. See the datasheet of mux controller to learn more about the configuration of controller. Figure
21 shows the connections between Display mux controller, Display Port Source, Type-C port and USB host in the
CY4541 EZ-PD CCG4 EVK schematic. Refer to the CY4541 CCG EVK Base Board schematics for details.
Figure 21. Display Port Connections in CY4541 EZ-PD CCG4 EVK Schematic
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Dual DisplayPort control of CCG4 can be demonstrated by using the CY4541 EZ-PD CCG4 EVK as shown in the
Figure 22. See Chapter 4 (DRP Kit Operation) of the CY4541 EZ-PD CCG4 EVK kit guide for details on hardware
connections of this setup.
Figure 22. Dual DisplayPort Connection Demo Using CY4541 EZ-PD CCG4 EVK
DisplayPort
DisplayPort to
DisplayPort
Cable
DisplayPort to
DisplayPort
Cable
Display Splitter
DisplayPort to
Display Port
Cable
J4
DisplayPort
J3
Cable Type-C
J3
Type-C
to DP
Dongle
to DP
Dongle
DisplayPort
Cable
J4
DC Power Adapter
(Connected to CCG
Base Board 1)
The CY4541 EZ-PD CCG4 EVK along with a USB 3.0- and DisplayPort-enabled notebook or a PC emulates a
CCG4-enabled Type-C notebook. In this scenario, the DP splitter receives DisplayPort signals from a notebook or a
PC having a DisplayPort interface. A DP splitter performs internal demultiplexing of DisplayPort signals and routes
these signals to both the Display Ports (J4) of the CCG baseboards as shown in Figure 20. CCG4 delivers
DisplayPort video from the host (notebook or PC) to the Display monitors connected to both Type-C port 1 and TypeC port 2 using the onboard display mux controllers and Type-C to DP dongles. This demonstrates the CCG4’s
capability to control two display ports simultaneously. See the CY4541 EZ-PD CCG4 EVK kit guide for recommended
Display splitter boards.
4.6
Electrical Design Considerations
See section 8 Electrical Design Considerations for more details.
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
5
Single Type-C Port DRP Application Using CCG4
CCG4 controller (CYPD4125-40LQXIT) is used here as a reference.
This section describes the design of a typical single Type-C port DRP application, such as a Type-C notebook, using
the EZ-PD CCG4 controller. Figure 23 shows the logical connections between the CCG4 and the components in a
notebook. This design is similar to the dual Type-C port application discussed in section 4 Dual Type-C port DRP
application using CCG4.
Figure 23. Single Type-C Port Notebook Design Using CCG4
2 x FETs
and Gate
Driver
1
BCC
7
BAT
VBUS_Source
2 x FETs
and Gate
Driver
8
DC/DC
VBUS_Sink
VBUS_MON
I2 C
2
VBUS_C VBUS_P
_CTRL _CTRL
I2 C 2
2
EZ-PD ™ CCG4
EC
USB
Type-C
Receptacle
VCONN/CC
2
I C_INTR
V5V
VCONN
Supply
9
HPD
I2 C
USB Host on
Motherboard
SS
3
2
4
2
DP/DM
4
3
8 ML_Lanes/SS
4
Display Port
Source on
Motherboard
9
HPD
ML_Lanes Display
8
MUX
AUX
2
SBU
6
5
2
1] BCC - Battery Charge Controller
2] EC - Embedded Controller
3] SS - SuperSpeed
4] ML – Main Link
5] AUX - Auxiliary signals
6] SBU – Side Band Use
7] BAT – Battery
8] DC/DC – DC to DC Converter
9] HPD – Hot Plug Detect
Critical sections of this Type-C notebook design using CCG4 are described below:





Power Supply Design
Dead Battery Charging
Power Provider/Consumer
DisplayPort Connection
Electrical Design Considerations
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
5.1
Power Supply Design
See Power Supply Design.
5.2
I2C Communication with Embedded Controller
See I2C Communication with Embedded Controller.
5.3
Dead Battery Charging
See Dead Battery Charging.
5.4
Power Provider/Consumer Role
See the Power Provider/Consumer Role.
5.5
DisplayPort Connections
This section is applicable to CCG2, CCG3 and CCG4 (only single Type-C port CCG4 controller, CY4125-40LQXIT).
Type-C is a versatile connector, which also supports DisplayPort signals by repurposing one of the SuperSpeed
lanes and two sideband signals. These repurposed signals act in a new mode, called an “alternate mode.” One
example of using a Type-C interconnection in the alternate mode is DisplayPort. See the VESA specification for more
details on the DisplayPort Alt Mode on the USB Type-C Standard.
In a Type-C notebook design, a display monitor can be connected directly to the notebook over the Type-C interface
using CCG2/CCG3/CCG4 and a display mux controller. Figure 24 shows the connections between
CCG2/CCG3/CCG4 and the display mux controller in a notebook design.
Figure 24. CCG2/CCG3/CCG4 and Display Mux Controller Connections
DP/DM
USB 3.0 Host
Controller
1
SS Lanes
2
4
Tx/Rx
3
ML Lanes
Display Port
Source
2
AUX Lanes
HPD
8
Display Mux
(PS8740B)
SBU
8
5
2
Type-C
Port
CC 2
2
4
I2C 2
EZ-PD™
CCG2/3
1] SS – SuperSpeed
2] ML Lanes – Main Link
3] AUX Lines – Auxilliary Lines
4] HPD – Hot Plug Detect
5] SBU – Side Band Use
Whenever a display monitor is connected to the Type-C port on a notebook, the CCG2/CCG3/CCG4device discovers
that it has a device attached with alternate mode supported. Through PD communication, the CCG2/CCG3/CCG4
device identifies the display monitor’s Standard ID (SID) or Vendor ID (VID) (so SVID = SID or VID). The display
monitor reports an SVID of 0xFF01 (per the Type-C specification), which is assigned to a DisplayPort connection.
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
The CCG2/CCG3/CCG4 device initiates an alternate mode sequence and asserts the Hot Plug Detect (HPD) signal
to the DisplayPort source and display mux controller. The DisplayPort source detects that the display monitor is
connected to the notebook. The display monitor can have two or four Main Link (Display Port) lanes. The 2-lane Main
Link configuration supports a raw bit rate up to 10.8 Gbps, and the 4-lane Main Link configuration supports a raw bit
rate up to 21.6 Gbps.
The CCG2/CCG3/CCG4 device checks the DisplayPort status, and if it receives an ACK, the CCG2/CCG3/CCG4
device configures the display mux controller in either 2-lane or 4-lane mode. The CCG2/CCG3/CCG4 device
2
communicates with the display mux controller either over an I C interface (such as the display mux controller from
Parade, PS8740B) or over a GPIO interface (such as the display mux controller from Pericom, PI3DBS12412AZHE),
depending on the type of display mux controller used in the system. See the respective mux controller’s datasheet for
more details.
The display mux controller switches its output lines (TX/RX) between the USB SuperSpeed lanes and the Main Link
(Display Port) lanes from the DisplayPort source.
Consider a scenario in which a 4-lane display monitor is connected to the notebook, and no other USB 3.0 device is
connected. In this case, the display mux controller connects four Main Link (DisplayPort) lanes to the Type-C port,
and a display appears on the screen. Now, if a USB 3.0 device is connected to the notebook, it enumerates as a USB
2.0 device because all the SuperSpeed lanes on the Type-C port are repurposed as DisplayPort lanes. The USB 2.0
enumeration occurs because the USB 2.0 (DP/DM) lines are directly connected from the USB Host controller to the
Type-C port.
The USB Host controller detects the presence of the SuperSpeed device (enumerated as a USB 2.0 device) and
communicates it to the EC. The system may decide to switch from 4-lane to 2-lane mode to enable SuperSpeed
device enumeration or it may continue to be in 4-lane mode. This is implementation-specific. If the system wants to
switch to 2-lane mode, the EC sends a message to the CCG2/CCG3/CCG4 device to reconfigure the display mux
controller from 4-lane to 2-lane display mode to enable connection of the USB SuperSpeed lane to the Type-C port.
Now, the display appears on the monitor, and the USB 3.0 device is detected as a SuperSpeed device. Note that the
display monitor’s resolution in the 2-lane mode will be lower than in the 4-lane mode. The Type-C port also receives
auxiliary signals from the DisplayPort source through the display mux controller that carry either the audio signals or
the control signals for the display.
The recommended part for display mux controller with redriver circuitry is from Parade Technologies (PS8740B),
which compensates for the PC board, connector, and cable losses and maintains signal quality by adjusting the gain
of the redriver circuitry. See the datasheet of mux controller to learn more about the configuration of controller.
5.6
Electrical Design Considerations
See the Electrical Design Considerations.
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
6
Single Type-C Port DRP Application Using CCG3
CCG3 controller (CYPD3125-40LQXIT) is used here as a reference.
CCG3 includes integrated 20-V VBUS NFET/PFET gate drivers, VCONN FETs, VBUS Discharge FETs, OVP, and
OCP, which facilitate the single-port Type-C notebook design with a reduced BOM compared to EZ-PD CCG2. Figure
25 shows the logical connections between CCG3 and the components in a notebook design.
Figure 25. Single Type-C Port Notebook Design Using CCG3
VBUS_SINK
2 FETs
BCC
I2 C
1
3
5
VBUS_SOURCE
6
BAT
DC/DC
2 FETs
VCONN
SUPPLY
VBUS_P_CTRL
2
V5V
3
VBUS_C_CTRL
EZ-PD ™ CCG3
EC
USB
Type-C
Receptacle
VCONN/CC
I2 C
9
I2 C
HPD
USB Host on
Motherboard
9
HPD
2 DP/DM
7
SS
6
3
Display Port
Source on
Motherboard
2
ML_Lanes
8
3
7
8 ML_Lanes/SS
MUX
4
2 SBU
8
AUX
2
1] BCC -- Battery Charge Controller
2] EC -- Embedded Controller
3] ML -- Main Link
4] SBU -- Side Band Use
5] BAT – Battery
6] DC/DC – DC to DC Converter
7] SS – SuperSpeed
8] AUX – Auxiliary Signals
9] HPD – Hot Plug Detect
Critical sections of this Type-C notebook design using CCG3 are described below:






Power Supply Design
2
I C Communication with Embedded Controller
Dead Battery Charging
Power Provider/Consumer Role
Display Port Connection
Electrical Design Considerations
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
6.1
Power Supply Design
Cypress’s Type-C PD Controller CCG3 operates with two possible external supply voltages, VBUS or VSYS as
referred in Table 10. The VBUS supply is regulated inside the chip with a low-dropout regulator (LDO). The chip’s
internal VDDD rail is intelligently switched between the output of the VBUS regulator and unregulated VSYS. The
switched supply, VDDD is either used directly inside some analog blocks or further regulated down to VCCD which
powers the majority of the core using regulators as shown in Figure 26. VCCD is the output voltage from the core
regulator and this pin is intended to connect only a decoupling capacitor. The VCCD pin cannot be used as a voltage
source. CCG3 has the power supply input VCONN pin for providing power to electronically marked cables through
integrated VCONN FETs. There is a VCONN FET in CCG3 to power the CC1 and CC2 pins. This FET is capable of
providing a maximum of 500-mA current on the CC1 and CC2 pins for EMCA cables.
Figure 26. CCG3 Power Subsystem
VSYS
Switch
VBUS
Regulator
VDDD
VCONN
RA
Regulator
VCCD
VDDIO
CC
Tx/Rx
Core
GPIO
FS-USB
TX/RX
VSS
DP, DM
CC1, CC2
VSS
CCG3
Table 10. CCG3 Operating Voltage Range
Parameter
www.cypress.com
Min
(V)
Typical
(V)
Max
(V)
VBUS
4
--
21.5
VSYS
4.5
--
5.5
VCONN
2.7
--
5.5
VDDD
2.7
VDDIO
1.71
5.5
1.80
VDDD
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
6.1.1
Noise Suppression Using Decoupling Capacitors
Power supply noise can be suppressed by using decoupling capacitors to power supply pins VBUS, VSYS, VDDD,
VDDIO, VCCD, and VCONN pins as shown in Figure 27. A 390-pF decoupling capacitor should be connected to CC
lines (CC1, CC2) to maintain the signal quality at the signaling rate of 300 kHz.
Figure 27. Noise Suppression Using Decoupling Capacitors
17
VBUS
VDDD
1uF C10
31
0.1uF C24
18
1uF C10'
C5
1uF
C4
0.1uF C22
1uF
C8
0.1uF
1uF
C6
0.1uF
VDDIO
VSYS
20
0.1uF C24
19
VCCD
1.3 uF C11
V5V
4
EZ-PD™ CCG3
(40-QFN)
C7
VDDIO
100 KΩ R68
1uF
26
XRES
CC1
5
C29
390pF C39
CC2
3
390pF C40
6.1.2
Reset and Clock Circuit
CCG3 supports a power-on-reset (POR) mechanism and it also has an active LOW external reset (XRES) pin. The
XRES (active LOW) pin can be used by external devices to reset the CCG3. The XRES pin should be held LOW for a
minimum of 1us to reset the CCG3. This XRES pin should be tied through an RC circuit as shown in Figure 27 .The
recommended values for R and C are 100 kΩ and 1 µF respectively to meet the 1-µs pulse-width requirement.
CCG3 has integrated clock circuitry and any external components such as crystal or oscillator are not required.
6.2
I2C Communication with Embedded Controller
This section is applicable to CCG3. See I2C Communication with Embedded Controller.
6.3
Dead Battery Charging
This section is applicable to CCG3. See Dead Battery Charging
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
6.4
Power Provider/Consumer Role
This section is applicable to CCG3.
A notebook design using CCG3 (with DRP capabilities) will be a power provider when running from its internal battery
and a power consumer when being charged from the DFP (or a charging UFP such as a power adapter, monitor, or
any external power provider such as a hard disk).
A BCC controls the charging (sinking of VBUS) or discharging (sourcing of VBUS) of the battery. CCG3 consists of
gate drivers and four I/Os, namely VBUS_P_CTRL_P1, VBUS_P_CTRL_P0, VBUS_C_CTRL_P1, and
VBUS_C_CTRL_P0, to control the VBUS provider or consumer path connected to the BCC. Figure 28 shows the
recommended implementation of FETs to control this VBUS path.
Figure 28. VBUS Provider and Consumer Path Control Circuitry
BATTERY
CHARGER
CONTROLLER
VBUS_SINK
(VBUS CONSUMER PATH)
Q4
Q3
4.7 uF
VBUS_C_CTRL_P1
DC/DC
CONVERTER
VBUS_C_CTRL_P0
Q2
VBUS_SOURCE
(VBUS PROVIDER PATH)
Q1
VBUS (5-20V)
VBUS
4.7 uF
TYPE-C PORT
VBUS_P_CTRL_P1
VBUS_DISCHARGE
200 Ω,
2.5 W
VBUS_DISCHARGE
EZ-PD™ CCG3
VBUS_C_CTRL_P1
VBUS_C_CTRL_P0
VBUS_P_CTRL_P1
VBUS_P_CTRL_P0
4.7 uF
VBUS_P_CTRL_P0
VBUS_C_CTRL_P1
VBUS_C_CTRL_P0
VBUS_P_CTRL_P1
VBUS_P_CTRL_P0
VBUS_P_CTRL_P1 and VBUS_P_CTRL_P0 are active HIGH pins. FETs Q1 and Q2 turn ON when both the pins are
HIGH. This turns ON the VBUS provider path. Similarly, when VBUS_C_CTRL_P1 and VBUS_C_CTRL_P0 are
HIGH, FETs Q3 and Q4 turn ON, which turns ON the VBUS consumer path.
The diodes between the source and drain terminals of FETs Q1 and Q2 turn OFF the VBUS provider path completely
when the VBUS consumer path is active. Similarly, the diodes between the source and drain terminals of FETs Q3
and Q3 turn OFF the VBUS consumer path completely when the VBUS provider path is active.
6.4.1
Control of VBUS Discharge Path
Depending on the connected downstream device, the VBUS voltage varies, as illustrated by the following example
scenarios:

Example scenario 1: A UFP device sinking 100 W of power (20 V, 5 A) is disconnected from the Type-C port and
immediately another UFP device sinking 25 W of power (5 V, 5 A) is connected to the same Type-C port.

Example scenario 2: A notebook changes its power role from provider (sourcing 100 W of power) to consumer
(sinking 45 W of power).
In scenario 1, the VBUS capacitor shown in Figure 28 may not have discharged fully from the original 20 V when the
second UFP device was connected. This could cause an overvoltage on the second UFP device, which requires 5 V
on VBUS.
In scenario 2, a similar overvoltage could occur when the power role is swapped. To prevent this scenario, CCG3
provides a discharge path to the VBUS capacitor by triggering the VBUS Discharge pin. VBUS Discharge is an active
HIGH signal, which turns ON the integrated VBUS discharge FET in CCG3, causing a discharge of the VBUS
capacitor through a resistor, as shown in Figure 28. It is necessary to use a series resistor (200 Ω) with a minimum
2.5-W power rating because the power dissipation during VBUS discharge will be high.
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6.4.2
O ve r vo l t a g e P r o t e c t i o n ( O V P ) f o r V B U S
CCG3 includes integrated OVP circuits to sense overvoltage conditions on VBUS.
Consider a scenario in which the notebook and the DFP device connected to its Type-C port establish the power
contract, and the notebook starts receiving 13 V of VBUS from the DFP. Once the power contract is established for a
13-V VBUS, CCG3 device’s firmware configures the OVP trip voltage, which is 1.2 times the negotiated VBUS
voltage. If the VBUS voltage exceeds the OVP trip voltage, CCG3 detects the overvoltage at VBUS and turns OFF
the VBUS from the external power supply. CCG3 also turns OFF power consumer FETs Q3 and Q4 as shown in
Figure 28 and disconnects itself from the Type-C port.
6.4.3
Undervoltage Protection
Undervoltage Protection (UVP)
enabled notebook is consuming
or an external hard disk) over
conditions on VBUS.
(UVP) for VBUS
circuitry is required on VBUS to detect Type-C disconnect events when CCG3power from the DFP (such as a power adapter) or charging UFP (such as a monitor
Type-C interface. CCG3 includes integrated UVP circuits to sense undervoltage
Consider a scenario in which the notebook and the DFP device connected to its Type-C port establish the power
contract, and the notebook starts receiving 5 V of VBUS from the DFP. The CCG3 device has set undervoltage
detection threshold to 4 V in its firmware. If the VBUS voltage goes below 4 V, then CCG3 detects the undervoltage
at VBUS and turns OFF VBUS from the external power supply. CCG3 also turns OFF power consumer FETs Q3 and
Q4 as shown in Figure 28 and disconnects itself from the Type-C port.
6.4.4
O ve r c u r r e n t P r o t e c t i o n ( O C P ) f o r V B U S
CCG3 includes integrated OCP circuits to sense overcurrent conditions on VBUS. Consider a scenario in which the
notebook and the UFP device connected to its Type-C port establish the power contract, and the notebook starts
providing 5 A of VBUS current to the UFP. Once the power contract is established for 5 A of VBUS, CCG3 device’s
firmware configures the OCP trip current, which can be set to 1.2 times the negotiated VBUS current. If the VBUS
current exceeds the OCP trip current (e.g., due to a hardware fault in the UFP device), CCG3 detects the overcurrent
at VBUS and turns OFF the VBUS by turning OFF gate drivers in order to turn OFF power provider FETs Q1 and Q2.
CCG3 also disconnects itself from the Type-C port.
The OC pin is the overcurrent sensor input pin to CCG3. This pin is connected to the VBUS_P pin of CCG3 through a
10-mΩ resistor to sense the input current, as shown in Figure 29.
Figure 29. OCP Circuitry
DC/DC
CONVERTER
VBUS_SOURCE
(VBUS PROVIDER PATH)
OCP detect signal
connected to the the
gate drivers
controlling VBUS
provider FETs
VBUS_P
Integrated Current
Sense Amplifier and
Comparator
for OCP
10 mΩ
OC
Q2
Q1
VBUS
VBUS
EZ-PD™ CCG3
VBUS_P_CTRL_P1
Gate
Drivers
VBUS_P_CTRL_P0
6.4.5
O ve r c u r r e n t P r o t e c t i o n ( O C P ) f o r V C O N N
See Overcurrent Protection (OCP) for VCONN.
6.5
DisplayPort Connections
This section is applicable to CCG3. See DisplayPort Connections .
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
6.6
Electrical Design Considerations
See Electrical Design Considerations.
7
Single Type-C Port DRP Application Using CCG2
This section describes the design of a typical single Type-C port DRP application, such as a Type-C notebook, using
CCG2 Type-C PD Controller (CYPD2122-24LQXIT). Figure 30 shows the logical connections between CCG2 and the
components in a notebook.
Figure 30. Single Type-C Port Notebook Design Using CCG2
2 x FETs
and Gate
Driver
1
BCC
7
BAT
VBUS_Source
2 x FETs
and Gate
Driver
8
DC/DC
VBUS_Sink
VBUS_MON
I2 C
2
VBUS_C VBUS_P
_CTRL _CTRL
I 2C 2
2
EZ-PD ™ CCG2
EC
USB
Type-C
Receptacle
VCONN/CC
2
I C_INTR
VCONN_CTRL
9
HPD
VCONN
Supply
I2 C
USB Host on
Motherboard
SS
3
2
4
2 FETs
2
DP/DM
4
3
8 ML_Lanes/SS
4
Display Port
Source on
Motherboard
9
HPD
ML_Lanes Display
8
MUX
AUX
2
SBU
6
5
2
1] BCC - Battery Charge Controller
2] EC - Embedded Controller
3] SS - SuperSpeed
4] ML – Main Link
5] AUX - Auxiliary signals
6] SBU – Side Band Use
7] BAT – Battery
8] DC/DC – DC to DC Converter
9] HPD – Hot Plug Detect
Critical sections of this Type-C notebook design using CCG2 are described below:






Power Supply Design
2
I C Communication with Embedded Controller
Dead Battery Charging
Power Provider/Consumer
DisplayPort Connection
Electrical Design Considerations
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
7.1
Power Supply Design
Cypress’s Type-C PD Controller CCG2 operates with two supply voltages; the first voltage supply, VDDD, powers the
device core and two Type-C transceivers. The other supply, VDDIO, powers the device I/Os as referred in Table 11.
CCG2 has an integrated voltage regulator as shown in Figure 31. The core regulator powers the core logic and
VCCD is an output of the regulator. The VCCD pin is intended to connect only a decoupling capacitor. It cannot be
used as a voltage source. CCG2 has power supply inputs VCONN1 and VCONN2, which can be used as
connections to the VCONN pins on a Type-C plug of a cable or VCONN-powered accessory. CCG2 can be used in
Electronically Marked Cable Applications (EMCA) with only one or both VCONN pins as power sources.
Figure 31. CCG2 Power Subsystem
VCONN1
VCONN2
Regulator
VDDD
Regulator
VCCD
VDDIO
GPIO
CC
Tx/Rx
Core
VSS
CCG2
Table 11. CCG2 Operating Voltage Range
Parameter
7.1.1
Min
(V)
Typical
(V)
Max
(V)
VDDD
3
--
5.5
VDDIO
1.71
--
VDDD
Noise Suppression Using Decoupling Capacitors
Power supply noise can be suppressed by using decoupling capacitors to power supply pins VDDD, VDDIO, VCCD,
VCONN1, and VCONN2 as shown in Figure 32. A 390-pF decoupling capacitor should be connected to the CC lines
(CC1 and CC2) to maintain signal quality at the signaling rate of 300 kHz.
Figure 32. Noise Suppression Using Decoupling Capacitors
9
1uF C1
6
32
VCONN1
VDDD
5
1uF
VDDD
VDDIO
VCONN2
4
1uF C1'
1uF
7
VCCD
1 uF
C2
EZ-PD™ CCG2
(24-QFN)
CC1
2
390 pF C5
VDDIO
4.7 KΩ
1uF
www.cypress.com
R1
16
XRES
CC2
1
390 pF C6
C7
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7.1.2
Reset and Clock Circuit
CCG2 supports a power-on-reset (POR) mechanism; it also has an active LOW external reset (XRES) pin. The
XRES (active LOW) pin can be used by external devices to reset the CCG2 device. The XRES pin should be held
LOW for a minimum of 1 µs to reset the CCG2 device. This XRES pin should be tied through an RC circuit as shown
in Figure 32. The recommended values for R and C are 100 kΩ and 1 µF respectively to meet the 1-µs pulse-width
requirement.
CCG2 has an integrated internal clock; external components such as crystals or oscillators are not required.
7.2
I2C Communication with Embedded Controller
This section is applicable to CCG2. See I2C Communication with Embedded Controller.
7.3
Dead Battery Charging
This section is applicable to CCG2. See Dead Battery Charging.
7.4
Power Provider/Consumer Role
This section is applicable to CCG2. See Power Provider/Consumer Role.
7.5
DisplayPort Connections
This section is applicable to CCG2. See DisplayPort Connections.
7.6
Electrical Design Considerations
See Electrical Design Considerations.
8
Electrical Design Considerations
This section explains PCB design guidelines for routing power signals and USB signals. It provides recommendations
for placing components on the board.
8.1.1
ESD and EMI/EMC Protection
Ferrite beads are not mandatory for all Type-C applications but are recommended to be connected between the USB
Type-C connector’s Shield and the system’s GND pin (in the place of resistor R81, as shown in Figure 33, to prevent
the transmission of electrical stress from the Type-C connector to the CCG2/CCG3/CCG4 device.
Figure 33. ESD and EMC Protection
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
CCG2/CCG4 has built-in ESD protection of 2 kV on VBUS line whereas CCG3 has on VBUS, USBD+ and USBDlines. ESD protection diodes (D15, D16, and D17) are recommended to be connected to VBUS, USBD+, and USBDlines for protection above 2 kV as shown in Figure 33. CCG2/CCG3/CCG4 has been tested to work with ESD
protection diode model ESD105_B1_02EL.
8.1.2
Power Domain
Consider the following while designing the power system network for DRP applications:



Placement of bulk and decoupling capacitors
Placement of power and ground planes
Power domain routing
Placement of bulk and decoupling capacitors

Place decoupling capacitors close to the power pins of the respective CCG controller for high- and low-frequency
noise filtering as shown in Figure 34.

Place the bulk capacitor, which acts as a local power supply, close to the power supply input and output headers
and voltage regulators. Filter power inputs and outputs near the power headers to reduce the electrical noise.
Ceramic or tantalum capacitors are recommended; electrolytic capacitors are not suitable for bulk capacitance.
Figure 34. Placement of Bulk and Decoupling Capacitors
Placement of power and ground planes

Use a high-performance substrate material for PCBs. Per the USB-PD specification, the system may carry
current up to 5 A. Thus, it is required to construct PCBs with 2 ounce (oz) copper thickness. Minimum
recommended space between copper elements is 8 mil (0.203 mm).

Use dedicated planes for power and ground. Use of dedicated planes reduces jitter on USB signals and helps
minimize the susceptibility to EMI and RFI.

Use cutouts on the power
5.0 V).

Place the power plane near the ground plane for good planar capacitance. Planar capacitance that exists
between the planes acts as a distributed decoupling capacitor for high-frequency noise filtering, thereby reducing
the electromagnetic radiation.

Do not split or cut the ground plane. Splitting it increases the electrical noise and jitter on USB signals. Ground
planes should be continuous. A discontinuous ground plane leads to larger inductance due to longer return
current paths, which can increase EMI radiation. Also, multiple split grounds can cause increased crosstalk.
www.cypress.com
plane
if more than one voltage is required on the board (for example, 2.5 V, 3.3 V,
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Voltage regulation
The following points must be considered while selecting voltage regulators to reduce electrical emissions and prevent
regulation problems during USB suspend:

Select voltage regulators that have minimum load current less than the board’s load current during USB
suspend. If the current drawn on the regulator is less than the regulator’s minimum load current, then the output
voltage may change.

Place voltage regulators so they straddle split VCC planes; this reduces emissions.
Power domain routing
8.1.3




Power traces should be routed with a minimum of 40 mils trace width to reduce inductance.

CCG2/CCG3/CCG4 devices have an EPAD (Exposed PAD), which needs to be soldered onto an exposed
ground pad provided in the PCB.

If a switched-mode power supply is used, power traces should be far away from signal traces to avoid addition of
power noise on signal or keep ground traces in between the signal traces.
Keep the power traces short.
Use larger vias (at least 30-mil pad, 15-mil hole) on power traces.
Make the power trace width the same dimension as the power pad. To connect power pins to the power plane,
keep the vias very close to the power pads. This helps in minimizing the stray inductance and IR drop on the line.
R o u t i n g o f T yp e - C ( U S B D a t a a n d C C ) L i n e s
USB SuperSpeed lines from the Host controller are connected to the Type-C port of the notebook through a display
multiplexer. Care should be taken while routing USB data and CC lines to achieve good signal quality and reduced
emission. Improper layouts lead to poor signal quality especially on the USB signaling, which may lead to
enumeration failure of SuperSpeed USB devices connected at Type-C port of the notebook. Follow these guidelines
while routing USB data and CC lines during the PCB design phase.
Guidelines for routing USB data lines

Keep USB SuperSpeed traces as short as possible. Ensure that these traces have a nominal differential
characteristic impedance of 90 Ω.



Match the differential SS pair trace lengths within 0.12 mm (5 mils).


Adjust the High-Speed signal trace lengths near the USB receptacle, if necessary.

Select a grounded coplanar waveguide (CPWG) system as a transmission line method as shown in Figure 35.
Match the High-Speed (Dp and Dn) signal trace lengths within 1.25 mm (50 mils).
Ensure that the differential pairs (Dp , Dn, SSTxp1, SSTxn1, SSRxp1, and SSRxn1) have a minimum pair-to-pair
separation of 0.5 mm.
Make adjustments for SS Rx signal trace lengths near the USB receptacle. Make adjustments for SS Tx signal
trace lengths near the device if necessary.
Figure 35. PWG Example

Minimize the use of vias.
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
G u i d e l i n e s f o r r o u t i n g T yp e - C ( V B U S , G N D a n d C C ) l i n e s

Group the VBUS pins together (all VBUS pins are brought out to the same plane using vias) as shown in Figure
36.
Figure 36. All VBUS Pins are Grouped Together


8.1.4
8.1.5
Similarly, group the GND pins together (all GND pins are brought out to the same plane using vias).
Place GND plane adjacent and below CC (CC1, CC2) lines.
R o u t i n g o f D i s p l a yP o r t L i n e s

Keep DisplayPort traces (MLLane[3:0] , AUX_CH_N, and AUX_CH_P) as short as possible. Ensure that these
traces have a nominal differential characteristic impedance of 90 Ω.


Match the differential DisplayPort and AUXCH pair trace lengths within 0.12 mm (5 mils).
Ensure that the differential pairs (MLLane[3:0] , AUX_CH_N and AUX_CH_P) have a minimum pair-to-pair
separation of 0.5 mm.
T yp i c a l 3 2 - m i l , S i x - L a ye r P C B E x a m p l e f o r D R P Ap p l i c a t i o n
Figure 37 shows the recommended stack up for a standard 32-mil-(0.8 mm) thick PCB. When this stack up is used
with two parallel traces, each with a width (W) of ‘x’ mils and a spacing (S) of ‘y’ mils., the calculated differential
impedance is 90 Ω. Figure 37 shows the values of width (W) and spacing (S) for CY4541 EZ-PD CCG4 EVK’s PCBs.
Figure 37. PCB Stack-Up
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
8.1.6
1.
Impedance Matching
Maintain a constant trace width and spacing in differential pairs to avoid impedance mismatches, as shown in Figure
38. Keep minimum 25-mils distance between USB SuperSpeed signals and the adjacent copper pour. Copper pour
affects their differential impedance when it is placed too close to USB signals.
Figure 38. Differential Pair Placement in CY4541 EZ-PD CCG4 EVK Layout
‘g’ is the minimum gap between the trace and other planes (8 mils)
‘W’ is the width of the signal trace
‘S’ is the gap between the differential pair signals
2.
Keep the trace length of USB SuperSpeed signals to less than 3 inches (75 mm). A 1.5-inch trace length (25–30
mm) or less is preferred. Match the lengths of USB traces to be within 50 mils (1.25 mm) of each other to avoid
skewing the signals and affecting the crossover voltage. Keep minimum 5-mil distance between USB
SuperSpeed signals (SSTx+,SSTx-) and other nonstatic traces wherever possible.
3.
On USB signal lines, use as few bends as possible. Do not use a 90-degree bend. Use 45-degree or rounded
(curved) bends if necessary, as illustrated in Figure 39.
Figure 39. Differential Pair Impedance Matching Techniques in CY4541 EZ-PD CCG4 EVK Layout
Not recommended
Not recommended
Recommended
4.
SuperSpeed (SS) signals should be routed in a single layer. Vias introduce discontinuities in the signal line and
affect the SS signal quality. If you need to route the SS signal to another layer, maintain continuous grounding to
ensure uniform impedance throughout. To do so, place ground vias next to signal vias, as shown in Figure 40.
The distance between the signal and ground vias should be at least 40 mils. Voids for vias on the SS signal
traces should be common for the differential pair. A common void, shown in Figure 40 helps to match the
impedance better than separate vias.
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Figure 40. Ground Vias and Void Vias Placement for SS Traces
Ground vias
Differential impedance
should be maintained
at 90 ohms in these
sections
Distance between each
via should be about 40
mils (center to center)
Void in plane
for vias
These four sections should
be routed as a single ended
trace. The impedance of
each individual trace should
be maintained at 45 ohms.
5.
SS signal vias
Distance between each
via pair should be about
40 mils.
All SS signal lines should be routed over an adjacent ground plane layer to provide a good return current path.
Splitting the ground plane underneath the SS signals introduces an impedance mismatch, thereby increasing the
loop inductance and electrical emissions. Figure 41 shows a recommended solid ground plane under the SS
signal.
Figure 41. Solid Ground Plane under SS Signal
SS trace
Signal layer
Ground layer
6.
Whenever two pairs of USB traces cross each other in different layers, a ground layer should run all the way
between the two USB signal layers, as Figure 41 shows.
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
9
Schematic and Layout Review Checklist
The following is a list of items that are critical for successful Type-C notebook design using Type-C PD controllers.
The ideal answer to each of the checklist items below should be “Yes”. Go through this checklist before creating a
PCB using the Type-C PD Controller. If a board has already been built and is not behaving as expected, go through
this list to verify that all the items are being implemented correctly on the target.
No.
Answer
(Yes/No/NA)
Schematic Checklist
1
Are the decoupling capacitors and bulk capacitors connected on power supply and CC pins as shown in
Figure 7 for CCG4, Figure 27 for CCG3, and Figure 32 for CCG2?
2
Do the power-on-reset RC components meet the minimum reset time (1 µs) as shown in Figure 7 for CCG4,
Figure 27 for CCG3, and Figure 32 for CCG2?
3
Are the I C lines provided with pull-up resistors (2.2 KΩ) as shown in Figure 8? Is the GPIO for I C interrupt
pin is same in both bootloader and application firmware?
4
Is the recommended arrangement of FETs present on VBUS to control power provider and consumer path as
shown in Figure 11for CCG2/CCG4 and Figure 29 for CCG3?
5
Is VBUS discharge circuitry present in the design as shown in Figure 14 for CCG2/CCG4?
6
Is overvoltage and undervoltage protection circuitry for VBUS present in the design as shown in Figure 15
and Figure 18 for CCG2/CCG4?
7
Is overcurrent protection circuitry for VBUS and VCONN present in the design as shown in Figure 19 for
CCG2/CCG3/CCG4?
9
Is Hot Plug Detect (HPD) signal connected from Type-C PD controller to DisplayPort source as shown in
Figure 24 for CCG2/CCG3/CCG4?
2
2


No.
Layout Checklist
1
Are the decoupling capacitors and bulk capacitors placed close to the Type-C PD controller power pins?
2
Is a 1-µF decoupling capacitor placed close to VCCD pin?
3
Are the vias placed close to the Type-C PD controller power pins?
4
Are the power traces routed away from the High-Speed (HS) and SuperSpeed (SS) data lines?
5
Is the capacitor in the RC reset circuitry placed close to the reset pin of the Type-C PD controller?
6
Has a dedicated and continuous GND plane been used?
7
Are all VBUS pins on the Type-C connector brought on the same plane using vias?
8
Are all GND pins on the Type-C connector brought on the same plane using vias?
9
Is GND present adjacent to and below CC lines?
10
Do the differential DisplayPort signal lines match in length?
11
Do the USB SS and HS signal lines match in length?
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Answer
(Yes/No/NA)
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
No.
Layout Checklist
12
Are the USB SS and HS signal lines provided with a solid ground plane underneath?
13
Are the USB traces kept short?
14
Do the USB traces have minimum bends and no 90-degree bends?
15
Is it ensured that there are no vias on SS traces?
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Answer
(Yes/No/NA)
45
Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
A.
Cypress Design Resources
Cypress CCG design resources include datasheets, application notes, evaluation kits, reference designs, firmware
and software tools. The resources are summarized in Table 8.
Table 12. CCG Design Resources
Design
Hardware
Available Resources
Where To Find Resources
Development Board – Schematic, Board files and documentation
Development Kit (DVK) Schematic
Board files available with
CY4501 CCG1 DVK (For CCG1)
CY4502 CCG2 DVK (For CCG2)
CY4531 CCG3 EVK (For CCG3)
CY4541 CCG4 EVK (For CCG4)
Technical
Reference
Manual
Code
Example
Host PC
Software
Hardware design guidelines including recommendations for resistors, decoupling
capacitors for power supplies and PCB layout
Application note – AN95599
IBIS model
IBIS model files
The programming reference manual gives the information necessary to program
the nonvolatile memory of the CYPD1xxx/CYPD2xxx devices.
Technical Reference Manual
The programming reference manual gives the information necessary to program
the nonvolatile memory of the CYPD3xxx devices.
Technical Reference Manual
The programming reference manual gives the information necessary to program
the nonvolatile memory of the CYPD4xxx devices.
Technical Reference Manual
EZ-PD CCG2 firmware examples
Firmware images
EZ-PD CCG4 firmware examples
Firmware images
GUI-based Windows application to help configure CCG controllers
EZ-PD™ Configuration Utility
Table 13 provides the list of application notes and reference designs for Type-C PD controllers.
Table 13. Application Notes and Reference Designs for Type-C PD Controllers
Application
Product Name
Document Link
Designing USB Type-C Products using Cypress CCG1 controllers
EZ-PD™ CCG1
Application Note
USB Type-C to HDMI/DVI/VGA Adapter design
EZ-PD™ CCG1
Reference Design
USB Type-C to display port solution
EZ-PD™ CCG1
Reference Design
Electronically marked cable assembly (EMCA) paddle card reference design
EZ-PD™ CCG1
Reference Design
USB Type-C to legacy USB device cable paddle reference design
EZ-PD™ CCG1
Reference Design
Designing USB 3.1 Type-C cables using EZ-PD™ CCG2
EZ-PD™ CCG2
Application Note
Hardware Design Guidelines for EZ-PD™ CCG2
EZ-PD™ CCG2
Application Note
Electronically marked cable assembly (EMCA) paddle card reference design
EZ-PD™ CCG2
Reference Design
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Table 14 provides the list of available collaterals for Type-C PD controllers.
Table 14. Available Collaterals for Type-C PD Controllers
Other Collaterals
CCG1 Datasheet
CCG2 Datasheet
CCG3 Datasheet
CCG4 Datasheet
Knowledge Base Articles for Type-C PD Controllers
Qualification report link for Type-C PD Controllers
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Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
Document History
Document Title: AN210403 – Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C
Controllers
Document Number: 002-10403
Revision
**
ECN
5074748
www.cypress.com
Orig. of
Change
Submission
Date
MVTA
03/02/2016
Description of Change
New application note
Document No. 002-10403 Rev. **
48
Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers
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Document No. 002-10403 Rev. **
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