CY7C1386S 18-Mbit (512 K × 36) Pipelined DCD Sync SRAM 18-Mbit (512 K × 36) Pipelined DCD Sync SRAM Features Functional Description ■ Supports bus operation up to 167 MHz ■ Available speed grade is 167 MHz ■ Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ■ Depth expansion without wait state ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 3.4 ns (for 167 MHz device) ■ Provides high-performance 3-1-1-1 access rate ■ User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self timed writes ■ Asynchronous output enable ■ Available in JEDEC-standard Pb-free 100-pin TQFP ■ ZZ sleep mode option The CY7C1386S SRAM integrates 512 K × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self timed write cycle.This part supports byte write operations (see Pin Configurations on page 4 and Truth Table on page 8 for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW writes all bytes. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance. The CY7C1386S operates from a +3.3 V core power supply while all outputs operate with a +3.3 V or +2.5 V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. Selection Guide 167 MHz Unit Maximum Access Time Description 3.4 ns Maximum Operating Current 275 mA Maximum CMOS Standby Current 70 mA Cypress Semiconductor Corporation Document Number: 001-43823 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 22, 2013 CY7C1386S Logic Block Diagram – CY7C1386S A0,A1,A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP BW D DQ D, DQP D BYTE WRITE REGISTER DQ D, DQP D BYTE WRITE DRIVER BW C DQ c ,DQP C BYTE WRITE REGISTER DQ c ,DQP C BYTE WRITE DRIVER DQ B ,DQP B BYTE WRITE REGISTER DQ B ,DQP B BYTE WRITE DRIVER BW B BW A BWE GW CE 1 CE 2 CE 3 OE ZZ SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs DQP A DQP B DQP C DQP D E DQ A, DQP A BYTE WRITE DRIVER DQ A, DQP A BYTE WRITE REGISTER ENABLE REGISTER MEMORY ARRAY PIPELINED ENABLE INPUT REGISTERS CONTROL Document Number: 001-43823 Rev. *E Page 2 of 22 CY7C1386S Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Single Read Accesses ................................................ 6 Single Write Accesses Initiated by ADSP ................... 6 Single Write Accesses Initiated by ADSC ................... 6 Burst Sequences ......................................................... 7 Sleep Mode ................................................................. 7 Interleaved Burst Address Table ................................. 7 Linear Burst Address Table ......................................... 7 ZZ Mode Electrical Characteristics .............................. 7 Truth Table ........................................................................ 8 Truth Table for Read/Write .............................................. 9 Maximum Ratings ........................................................... 10 Operating Range ............................................................. 10 Electrical Characteristics ............................................... 10 Document Number: 001-43823 Rev. *E Capacitance .................................................................... 11 Thermal Resistance ........................................................ 11 AC Test Loads and Waveforms ..................................... 11 Switching Characteristics .............................................. 12 Switching Waveforms .................................................... 13 Ordering Information ...................................................... 17 Ordering Code Definitions ......................................... 17 Package Diagrams .......................................................... 18 Acronyms ........................................................................ 19 Document Conventions ................................................. 19 Units of Measure ....................................................... 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 22 Worldwide Sales and Design Support ....................... 22 Products .................................................................... 22 PSoC Solutions ......................................................... 22 Page 3 of 22 CY7C1386S Pin Configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1386S (512 K × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA MODE A A A A A1 A0 NC/72M NC/36M VSS VDD A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enables) Document Number: 001-43823 Rev. *E Page 4 of 22 CY7C1386S Pin Definitions Name A0, A1, A I/O Description InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the two-bit counter. BWA, BWB, InputByte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. BWC, BWD Synchronous Sampled on the rising edge of CLK. GW InputGlobal Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write Synchronous is conducted (all bytes are written, regardless of the values on BWX and BWE). BWE InputByte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted Synchronous LOW to conduct a byte write. CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. CE3 InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. OE InputOutput Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW, Asynchronous the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputAdvance Input Signal, Sampled on the Rising Edge of Clk, Active LOW. When asserted, it automatSynchronous ically increments the address in a burst cycle. ADSP InputAddress Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputAddress Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ InputZZ Sleep Input, Active High. When asserted HIGH places the device in a non-time critical sleep Asynchronous condition with data integrity preserved. For normal operation, this pin must be LOW. ZZ pin has an internal pull down. DQs, DQPX I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. VDD Power Supply Power Supply Inputs to the Core of the Device. VSS Ground Ground for the Core of the Device. VSSQ I/O Ground Ground for the I/O Circuitry. VDDQ I/O Power Supply Power Supply for the I/O Circuitry. Document Number: 001-43823 Rev. *E Page 5 of 22 CY7C1386S Pin Definitions (continued) Name MODE I/O Description InputStatic Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up. NC – No Connects. Not internally connected to the die NC/(36M, 72M, 144M, 288M, 576M, 1G) – These Pins are not Connected. They are used for expansion to the 36M, 72M, 144M, 288M, 576M, and 1G densities. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1386S supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium® and i486 processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the byte write enable (BWE) and byte write select (BWX) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self timed write circuitry. Synchronous chip selects CE1, CE2, CE3 and an asynchronous output enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the address register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tCO if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. Document Number: 001-43823 Rev. *E The CY7C1386S is a double cycle deselect part. After the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output tri-states immediately after the next clock rise. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, then the write operation is controlled by BWE and BWX signals. The CY7C1386S provides byte write capability that is described in the write cycle description table. Asserting the byte write enable input (BWE) with the selected byte write input, selectively writes to only the desired bytes. Bytes not selected during a byte write operation remains unaltered. A synchronous self timed write mechanism has been provided to simplify the write operations. The CY7C1386S is a common I/O device, the output enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so tri-states the output drivers. As a safety precaution, DQ are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWX) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is Page 6 of 22 CY7C1386S written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation remains unaltered. A synchronous self timed write mechanism has been provided to simplify the write operations. The CY7C1386S is a common I/O device, the output enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so tri-states the output drivers. As a safety precaution, DQX are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the sleep mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) Burst Sequences The CY7C1386S provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise automatically increments the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Fourth Address A1:A0 Linear Burst Address Table (MODE = GND) Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. Accesses pending when First Address A1:A0 Second Address A1:A0 Third Address A1:A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 80 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC – ns tZZI ZZ Active to sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 – ns Document Number: 001-43823 Rev. *E Page 7 of 22 CY7C1386S Truth Table The truth table for CY7C1386S follows. [1, 2, 3, 4, 5] Operation Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK Deselect Cycle, Power Down None H Deselect Cycle, Power Down None L L X L L X X X X L–H Tri-State Deselect Cycle, Power Down None L X H L L X X X X L–H Tri-State Deselect Cycle, Power Down None L L X L H L X X X L–H Tri-State Deselect Cycle, Power Down None L X H L H L X X X L–H Tri-State Sleep Mode, Power Down X X L X L X X X DQ L–H Tri-State None X X X H X X X X X X Tri-State Read Cycle, Begin Burst External L H L L L X X X L L–H Q Read Cycle, Begin Burst External L H L L L X X X H L–H Tri-State Write Cycle, Begin Burst External L H L L H L X L X L–H D Q Read Cycle, Begin Burst External L H L L H L X H L L–H Read Cycle, Begin Burst External L H L L H L X H H L–H Tri-State Read Cycle, Continue Burst Next X X X L H H L H L L–H Read Cycle, Continue Burst Next X X X L H H L H H L–H Tri-State Read Cycle, Continue Burst Next H X X L X H L H L L–H Read Cycle, Continue Burst Next H X X L X H L H H L–H Tri-State Write Cycle, Continue Burst Next X X X L H H L L X L–H D Write Cycle, Continue Burst Next H X X L X H L L X L–H D Read Cycle, Suspend Burst Current X X X L H H H H L L–H Q Read Cycle, Suspend Burst Current X X X L H H H H H L–H Tri-State Read Cycle, Suspend Burst Current H X X L X H H H L L–H Read Cycle, Suspend Burst Current H X X L X H H H H L–H Tri-State Write Cycle, Suspend Burst Current X X X L H H H L X L–H D Write Cycle, Suspend Burst Current H X X L X H H L X L–H D Q Q Q Notes 1. X = Don't Care, H = Logic HIGH, L = Logic LOW. 2. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 001-43823 Rev. *E Page 8 of 22 CY7C1386S Truth Table for Read/Write The read/write truth table for CY7C1386S follows. [6, 7] Function (CY7C1386S) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write Byte A – (DQA and DQPA) H L H H H L Write Byte B – (DQB and DQPB) H L H H L H Write Bytes B, A H L H H L L Write Byte C – (DQC and DQPC) H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQD and DQPD) H L L H H H Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L Write Bytes D, C, B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Notes 6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 7. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is done based on which byte write is active. Document Number: 001-43823 Rev. *E Page 9 of 22 CY7C1386S Maximum Ratings DC Input Voltage ................................ –0.5 V to VDD + 0.5 V Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... –65 °C to +150 °C Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD DC Voltage Applied to Outputs in Tri-State ........................................–0.5 V to VDDQ + 0.5 V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Latch-up Current .................................................... > 200 mA Operating Range Range Ambient Temperature Commercial 0 °C to +70 °C VDD VDDQ 3.3 V– 5% / 2.5 V – 5% to + 10% VDD Electrical Characteristics Over the Operating Range Parameter [8, 9] Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH VOL VIH VIL IX Test Conditions Min 3.135 3.135 2.375 2.4 2.0 – – 2.0 1.7 –0.3 –0.3 –5 for 3.3 V I/O for 2.5 V I/O Output HIGH Voltage for 3.3 V I/O, IOH = –4.0 mA for 2.5 V I/O, IOH = –1.0 mA Output LOW Voltage for 3.3 V I/O, IOL = 8.0 mA for 2.5 V I/O, IOL = 1.0 mA Input HIGH Voltage [8] for 3.3 V I/O for 2.5 V I/O Input LOW Voltage [8] for 3.3 V I/O for 2.5 V I/O Input Leakage Current except ZZ GND VI VDDQ and MODE Input Current of MODE Input Current of ZZ Max Unit 3.6 V VDD V 2.625 V – V – V 0.4 V 0.4 V VDD + 0.3 V V VDD + 0.3 V V 0.8 V 0.7 V 5 A Input = VSS Input = VDD Input = VSS Input = VDD GND VI VDDQ, Output Disabled VDD = Max, IOUT = 0 mA, 6-ns cycle, f = fMAX = 1/tCYC 167 MHz –30 – –5 – –5 – – 5 – 30 5 275 A A A A A mA IOZ IDD [10] Output Leakage Current VDD Operating Supply Current ISB1 Automatic CE Power Down Current – TTL Inputs VDD = Max, Device Deselected, 6-ns cycle, VIN VIH or VIN VIL, 167 MHz f = fMAX = 1/tCYC – 140 mA ISB2 Automatic CE Power Down Current – CMOS Inputs 6-ns cycle, 167 MHz – 70 mA ISB3 Automatic CE Power Down Current – CMOS Inputs 6-ns cycle, 167 MHz – 125 mA ISB4 Automatic CE Power Down Current – TTL Inputs VDD = Max, Device Deselected, VIN 0.3 V or VIN > VDDQ – 0.3 V, f=0 VDD = Max, Device Deselected, VIN 0.3 V or VIN > VDDQ – 0.3 V, f = fMAX = 1/tCYC VDD = Max, Device Deselected, VIN VIH or VIN VIL, f = 0 6-ns cycle, 167 MHz – 80 mA Notes 8. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2). 9. TPower up: assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 10. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-43823 Rev. *E Page 10 of 22 CY7C1386S Capacitance Parameter [11] Description 100-pin TQFP Unit Max Test Conditions TA = 25 C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V CIN Input capacitance CCLK Clock input capacitance CIO Input/Output capacitance 5 pF 5 pF 5 pF Test Conditions 100-pin TQFP Package Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 28.66 °C/W 4.08 °C/W Thermal Resistance Parameter [11] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms 3.3V I/O Test Load R = 317 3.3V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 351 VT = 1.5V INCLUDING JIG AND SCOPE (a) 2.5V I/O Test Load OUTPUT RL = 50 Z0 = 50 INCLUDING JIG AND SCOPE 1 ns 1 ns (c) ALL INPUT PULSES VDDQ GND 5 pF 90% 10% 90% (b) R = 1538 VT = 1.25V (a) 10% R = 1667 2.5V OUTPUT ALL INPUT PULSES VDDQ (b) 10% 90% 10% 90% 1 ns 1 ns (c) Note 11. Tested initially and after any design or process change that may affect these parameters. Document Number: 001-43823 Rev. *E Page 11 of 22 CY7C1386S Switching Characteristics Over the Operating Range Parameter [12, 13] tPOWER Description VDD(Typical) to the First Access [14] -167 Unit Min Max 1 – ms Clock tCYC Clock Cycle Time 6.0 – ns tCH Clock HIGH 2.2 – ns tCL Clock LOW 2.2 – ns Output Times tCO Data Output Valid after CLK Rise – 3.4 ns tDOH Data Output Hold after CLK Rise 1.3 – ns Clock to Low Z [15, 16, 17] 1.3 – ns tCHZ Clock to High Z [15, 16, 17] – 3.4 ns tOEV OE LOW to Output Valid – 3.4 ns 0 – ns – 3.4 ns tCLZ tOELZ tOEHZ OE LOW to Output Low Z [15, 16, 17] OE HIGH to Output High Z [15, 16, 17] Setup Times tAS Address Setup Before CLK Rise 1.5 – ns tADS ADSC, ADSP Setup Before CLK Rise 1.5 – ns tADVS ADV Setup Before CLK Rise 1.5 – ns tWES GW, BWE, BWX Setup Before CLK Rise 1.5 – ns tDS Data Input Setup Before CLK Rise 1.5 – ns tCES Chip Enable Setup Before CLK Rise 1.5 – ns tAH Address Hold After CLK Rise 0.5 – ns tADH ADSP, ADSC Hold After CLK Rise 0.5 – ns tADVH ADV Hold After CLK Rise 0.5 – ns tWEH GW, BWE, BWX Hold After CLK Rise 0.5 – ns tDH Data Input Hold After CLK Rise 0.5 – ns tCEH Chip Enable Hold After CLK Rise 0.5 – ns Hold Times Notes 12. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 13. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted. 14. This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD(minimum) initially before a read or write operation can be initiated. 15. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of Figure 2 on page 11. Transition is measured ±200 mV from steady-state voltage. 16. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z prior to Low Z under the same system conditions. 17. This parameter is sampled and not 100% tested. Document Number: 001-43823 Rev. *E Page 12 of 22 CY7C1386S Switching Waveforms Figure 3. Read Cycle Timing [18] tCYC CLK tCH t ADS tCL tADH ADSP t ADS tADH ADSC t AS ADDRESS tAH A1 A2 t WES GW, BWE,BW A3 Burst continued with new base address tWEH X t CES Deselect cycle tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data Out (DQ) High-Z CLZ t OEHZ Q(A1) t OEV t CO t OELZ t DOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) t CO Single READ BURST READ DON’T CARE Burst wraps around to its initial state UNDEFINED Note 18. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 001-43823 Rev. *E Page 13 of 22 CY7C1386S Switching Waveforms (continued) Figure 4. Write Cycle Timing [19, 20] t CYC CLK tCH t ADS tCL tADH ADSP t ADS ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst t WES tWEH BWE, BW X t WES tWEH GW t CES tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data in (D) High-Z t OEHZ DS t DH D(A1) D(A2) D(A2 + 1) D(A2 + 3) D(A3) D(A3 + 1) Data Out (Q) BURST READ BURST WRITE Single WRITE DON’T CARE Extended BURST WRITE UNDEFINED Notes 19. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 20. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWX LOW. Document Number: 001-43823 Rev. *E Page 14 of 22 CY7C1386S Switching Waveforms (continued) Figure 5. Read/Write Cycle Timing [21, 22, 23] t CYC CLK tCL tCH t ADS tADH t AS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 t WES tWEH BWE, BW X t CES tCEH CE ADV OE t DS tCO Data In (D) t OELZ High-Z tCLZ Data Out (Q) tDH High-Z Q(A1) tOEHZ Q(A2) Back-to-Back READs D(A5) D(A3) Q(A4) DON’T CARE Q(A4+3) BURST READ Single WRITE D(A6) Back-to-Back WRITEs UNDEFINED Notes 21. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 22. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC. 23. GW is HIGH. Document Number: 001-43823 Rev. *E Page 15 of 22 CY7C1386S Switching Waveforms (continued) Figure 6. ZZ Mode Timing [24, 25] CLK t ZZ I t t ZZ ZZREC ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 24. Device must be deselected when entering ZZ sleep mode. See cycle descriptions table for all possible signal conditions to deselect the device. 25. DQs are in high Z when exiting ZZ sleep mode. Document Number: 001-43823 Rev. *E Page 16 of 22 CY7C1386S Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Package Diagram Ordering Code CY7C1386S-167AXC Part and Package Type 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Operating Range Commercial Ordering Code Definitions CY 7 C 1386 S - 167 A X C Temperature Range: C = Commercial Pb-free Package Type: A = 100-pin TQFP Frequency Range: 167 MHz Die Revision Part Identifier: 1386 = DCD, 512 K × 36 (18 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-43823 Rev. *E Page 17 of 22 CY7C1386S Package Diagrams Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 51-85050 *D Document Number: 001-43823 Rev. *E Page 18 of 22 CY7C1386S Acronyms Acronym Document Conventions Description Units of Measure CMOS Complementary Metal Oxide Semiconductor I/O Input/Output °C degree Celcius LSB Least Significant Bit MHz megahertz MSB Most Significant Bit µA microampere OE Output Enable mA milliampere SRAM Static Random Access Memory mm millimeter TQFP Thin Quad Flat Pack ms millisecond TTL Transistor-Transistor Logic mV millivolt WE Write Enable ns nanosecond ohm % percent pF picofarad V volt W watt Document Number: 001-43823 Rev. *E Symbol Unit of Measure Page 19 of 22 CY7C1386S Document History Page Document Title: CY7C1386S, 18-Mbit (512 K × 36) Pipelined DCD Sync SRAM Document Number: 001-43823 Rev. ECN No. Issue Date Orig. of Change ** 1897927 See ECN VKN / AESA New data sheet. *A 2082246 See ECN JASM Changed status from Preliminary to Final. Description of Change *B 2958560 See ECN NJY Updated Ordering Information (Removed inactive part numbers). *C 3219153 04/07/2011 NJY Added Ordering Code Definitions. Updated Package Diagrams. Added Acronyms and Units of Measure. Updated in new template. Document Number: 001-43823 Rev. *E Page 20 of 22 CY7C1386S Document History Page (continued) Document Title: CY7C1386S, 18-Mbit (512 K × 36) Pipelined DCD Sync SRAM Document Number: 001-43823 Rev. ECN No. Issue Date Orig. of Change Description of Change *D 3571224 04/03/2012 PRIT Updated Features (Removed 250 MHz, 200 MHz frequencies related information, removed 119-ball BGA package and 165-ball FBGA package related information). Updated Functional Description (Removed the Note “For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.” and its reference, removed the Note “CE3, CE2 are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in 1 chip enable.” and its reference). Updated Selection Guide (Removed 250 MHz, 200 MHz frequencies related information). Removed Logic Block Diagram – CY7C1387S. Updated Pin Configurations (Removed CY7C1387S related information, removed 119-ball BGA package and 165-ball FBGA package related information). Updated Pin Definitions (Removed the Note “CE3, CE2 are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in 1 chip enable.” and its reference, removed JTAG related information). Updated Functional Overview (Removed the Note “CE3, CE2 are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in 1 chip enable.” and its reference). Updated Truth Table (Removed CY7C1387S related information). Removed Truth Table for Read/Write (Corresponding to CY7C1387S). Removed IEEE 1149.1 Serial Boundary Scan (JTAG). Removed TAP Controller State Diagram. Removed TAP Controller Block Diagram. Removed TAP Timing. Removed TAP AC Switching Characteristics. Removed 3.3 V TAP AC Test Conditions. Removed 3.3 V TAP AC Output Load Equivalent. Removed 2.5 V TAP AC Test Conditions. Removed 2.5 V TAP AC Output Load Equivalent. Removed TAP DC Electrical Characteristics and Operating Conditions. Removed Identification Register Definitions. Removed Scan Register Sizes. Removed Identification Codes. Removed Boundary Scan Order. Updated Operating Range (Removed Industrial Temperature range). Updated Electrical Characteristics (Removed 250 MHz, 200 MHz frequencies related information). Updated Capacitance (Removed 119-ball BGA package and 165-ball FBGA package related information). Updated Thermal Resistance (Removed 119-ball BGA package and 165-ball FBGA package related information). Updated Switching Characteristics (Removed 250 MHz, 200 MHz frequencies related information). Updated Package Diagrams (Removed 119-ball BGA package and 165-ball FBGA package related information). Replaced all instances of IO with I/O across the document. *E 3978170 04/22/2013 PRIT No technical updates. Completing Sunset Review. Document Number: 001-43823 Rev. *E Page 21 of 22 CY7C1386S Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-43823 Rev. *E Revised April 22, 2013 Page 22 of 22 Intel and Pentium are registered trademarks, and i486 is a trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.