CY7C1471BV25, CY7C1475BV25 72-Mbit (2 M × 36/1 M × 72) Flow-Through SRAM with NoBL Architecture Datasheet.pdf

CY7C1471BV25
72-Mbit (2 M × 36)
Flow-Through SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/1 M × 72) Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
■
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
■
Supports up to 133 MHz bus operations with zero wait states
■
Data transfers on every clock
■
Pin compatible and functionally equivalent to ZBT™ devices
■
Internally self timed output buffer control to eliminate the need
to use OE
The CY7C1471BV25, is 2.5 V, 2 M × 36 synchronous flow
through burst SRAMs designed specifically to support unlimited
true back-to-back read or write operations without the insertion
of wait states. The CY7C1471BV25, is equipped with the
advanced No Bus Latency (NoBL) logic required to enable
consecutive read or write operations with data transferred on
every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems that
require frequent write-read transitions.
■
Registered inputs for flow through operation
■
Byte Write capability
■
2.5-V I/O supply (VDDQ)
■
Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■
Clock Enable (CEN) pin to enable clock and suspend operation
■
Synchronous self timed writes
■
Asynchronous Output Enable (OE)
■
CY7C1471BV25 available in JEDEC-standard Pb-free 100-pin
TQFP package.
■
Three Chip Enables (CE1, CE2, CE3) for simple depth
expansion.
■
Automatic power down feature available using ZZ mode or CE
deselect.
■
Burst Capability – linear or interleaved burst order
■
Low standby power
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by two or four Byte Write Select
(BWX) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tristate control. To avoid bus contention, the output
drivers are synchronously tristated during the data portion of a
write sequence.
For a complete list of related documentation, click here.
Selection Guide
Description
133 MHz
Unit
Maximum Access Time
6.5
ns
Maximum Operating Current
305
mA
Maximum CMOS Standby Current
120
mA
Cypress Semiconductor Corporation
Document Number: 001-15013 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 11, 2016
CY7C1471BV25
Logic Block Diagram – CY7C1471BV25
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
BW B
BW C
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
BW D
WE
OE
CE1
CE2
CE3
ZZ
Document Number: 001-15013 Rev. *N
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQP B
DQP C
DQP D
E
E
READ LOGIC
SLEEP
CONTROL
Page 2 of 22
CY7C1471BV25
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 8
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Burst Read Accesses .................................................. 9
Single Write Accesses ................................................. 9
Burst Write Accesses ................................................ 10
Sleep Mode ............................................................... 10
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ............................... 17
2.5 V TAP AC Test Conditions ....................................... 17
2.5 V TAP AC Output Load Equivalent ......................... 17
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 17
Document Number: 001-15013 Rev. *N
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Identification Codes ....................................................... 18
Boundary Scan Exit Order ............................................. 19
Boundary Scan Exit Order ............................................. 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC® Solutions ...................................................... 34
Cypress Developer Community ................................. 34
Technical Support ..................................................... 34
Page 3 of 22
CY7C1471BV25
Pin Configurations
A
40
41
42
43
44
45
46
47
48
49
50
VDD
A
A
A
A
A
A
A
A
A
37
A0
VSS
36
A1
39
35
A
NC/144M
34
A
38
33
A
NC/288M
32
A
Document Number: 001-15013 Rev. *N
81
A
82
83
A
A
84
ADV/LD
90
85
VSS
91
OE
VDD
92
86
CE3
93
CEN
BWA
94
WE
BWB
95
88
BWC
96
CLK
BWD
97
89
CE1
CE2
A
98
87
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1471BV25
31
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) Pinout
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 4 of 22
CY7C1471BV25
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the
Synchronous CLK. A[1:0] are fed to the two-bit burst counter.
InputByte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the
BWA, BWB,
BWC, BWD Synchronous rising edge of CLK.
WE
InputWrite Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
Synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH
Synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a
new address.
CLK
InputClock
Clock Input. Captures all synchronous inputs to the device. CLK is qualified with CEN. CLK is only
recognized if CEN is active LOW.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device.
OE
InputOutput Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block inside
Asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are enabled to behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
CEN
InputClock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.
Synchronous When deasserted HIGH the clock signal is masked. Because deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
ZZ
InputZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with
Asynchronous data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an
internal pull down.
DQs
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPX
I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPX is controlled by BWX correspondingly.
MODE
Input Strap Pin Mode Input. Selects the Burst Order of the Device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved
burst sequence.
VDD
Power Supply Power Supply Inputs to the Core of the Device.
VDDQ
I/O Power
Supply
VSS
Ground
NC
–
Power Supply for the I/O Circuitry.
Ground for the Device.
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion
pins and are not internally connected to the die.
Document Number: 001-15013 Rev. *N
Page 5 of 22
CY7C1471BV25
Functional Overview
The CY7C1471BV25, is synchronous flow through burst SRAMs
designed specifically to eliminate wait states during write read
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the Clock Enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns
(133-MHz device).
Accesses are initiated by asserting all three Chip Enables (CE1,
CE2, CE3) active at the rising edge of the clock. If CEN is active
LOW and ADV/LD is asserted LOW, the address presented to
the device is latched. The access is either a read or write
operation, depending on the status of the Write Enable (WE).
Use Byte Write Select (BWX) to conduct Byte Write operations.
Write operations are qualified by the WE. All writes are simplified
with on-chip synchronous self- timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise:
■
CEN is asserted LOW
■
CE1, CE2, and CE3 are ALL asserted active
■
WE is deasserted HIGH
■
ADV/LD is asserted LOW.
The address presented to the address inputs is latched into the
Address Register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW to drive out the
requested data. On the subsequent clock, another operation
(read/write/deselect) can be initiated. When the SRAM is
deselected at clock rise by one of the chip enable signals, the
output is tristated immediately.
Burst Read Accesses
The CY7C1471BV25, has an on-chip burst counter that enables
the user the ability to supply a single address and conduct up to
four reads without reasserting the address inputs. ADV/LD must
be driven LOW to load a new address into the SRAM, as
described in the Single Read Accesses section. The sequence
of the burst counter is determined by the MODE input signal. A
LOW input on MODE selects a linear burst mode, a HIGH selects
an interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and wraps around when incremented
sufficiently. A HIGH input on ADV/LD increments the internal
burst counter regardless of the state of chip enable inputs or WE.
WE is latched at the beginning of a burst cycle. Therefore, the
Document Number: 001-15013 Rev. *N
type of access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write accesses are initiated when these conditions are satisfied
at clock rise:
■
CEN is asserted LOW
■
CE1, CE2, and CE3 are ALL asserted active
■
WE is asserted LOW.
The address presented to the address bus is loaded into the
Address Register. The write signals are latched into the Control
Logic block. The data lines are automatically tristated regardless
of the state of the OE input signal. This allows the external logic
to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for Byte Write operations, see Truth Table for
Read/Write on page 9 for details) inputs is latched into the device
and
the
write
is
complete.
Additional
accesses
(read/write/deselect) can be initiated on this cycle.
The data written during the write operation is controlled by BWX
signals. The CY7C1471BV25, provides Byte Write capability that
is described in the Truth Table for Read/Write on page 9. The
input WE with the selected BWx input selectively writes to only
the desired bytes. Bytes not selected during a Byte Write
operation remain unaltered. A synchronous self timed write
mechanism is provided to simplify the write operations. Byte
Write capability is included to greatly simplify read/modify/write
sequences, which can be reduced to simple byte write operations.
Because the CY7C1471BV25, is common I/O devices, data
must not be driven into the device while the outputs are active.
The OE can be deasserted HIGH before presenting data to the
DQs and DQPX inputs. This tristates the output drivers. As a
safety precaution, DQs and DQPX are automatically tristated
during the data portion of a write cycle, regardless of the state of
OE.
Burst Write Accesses
The CY7C1471BV25, has an on-chip burst counter that makes
it possible to supply a single address and conduct up to four
Write operations without reasserting the address inputs. Drive
ADV/LD LOW to load the initial address, as described in Single
Write Accesses on page 6. When ADV/LD is driven HIGH on the
subsequent clock rise, the Chip Enables (CE1, CE2, and CE3)
and WE inputs are ignored and the burst counter is incremented.
You must drive the correct BWX inputs in each cycle of the Burst
Write to write the correct data bytes.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. You must
select the device before entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Page 6 of 22
CY7C1471BV25
Interleaved Burst Address Table
Linear Burst Address Table
(MODE = Floating or VDD)
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
00
01
10
11
01
00
11
10
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
ZZ Mode Electrical Characteristics
Min
Max
Unit
IDDZZ
Parameter
Sleep mode standby current
Description
ZZ > VDD– 0.2 V
–
120
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-15013 Rev. *N
Test Conditions
Page 7 of 22
CY7C1471BV25
Truth Table
The truth table for CY7C1471BV25 follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
Deselect Cycle
None
H
X
X
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tristate
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tristate
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tristate
Read Cycle (Begin Burst)
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
Read Cycle (Continue Burst)
L
L
X
X
X
L
L->H
DQ
Tristate
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tristate
Next
X
X
X
L
H
X
X
H
L
L->H
Tristate
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
Write Cycle (Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data In (D)
NOP/Write Abort (Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tristate
Write Abort (Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tristate
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tristate
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write Selects
are asserted, see Truth Table for Read/Write on page 9 for details.
2. Write is defined by BWX, and WE. See Truth Table for Read/Write on page 9.
3. When a write cycle is detected, all IOs are tristated, even during byte writes.
4. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CEN = H, inserts wait states.
6. Device powers up deselected with the IOs in a tristate condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tristate when OE is inactive
or when the device is deselected, and DQs and DQPX = data when OE is active.
Document Number: 001-15013 Rev. *N
Page 8 of 22
CY7C1471BV25
Truth Table for Read/Write
The read-write truth table for CY7C1471BV25 follows. [8, 9, 10]
Function
WE
BWA
BWB
BWC
BWD
Read
H
X
X
X
X
Write No bytes written
L
H
H
H
H
Write Byte A – (DQA and DQPA)
L
L
H
H
H
Write Byte B – (DQB and DQPB)
L
H
L
H
H
Write Byte C – (DQC and DQPC)
L
H
H
L
H
Write Byte D – (DQD and DQPD)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
Notes
8. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write Selects
are asserted, see Truth Table for Read/Write on page 9 for details.
9. Write is defined by BWX, and WE. See Truth Table for Read/Write on page 9.
10. This table is only a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is based on which byte write is active.
Document Number: 001-15013 Rev. *N
Page 9 of 22
CY7C1471BV25
Maximum Ratings
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55C to +125 C
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up Current .................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND .....–0.5 V to +3.6 V
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC Voltage Applied to Outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
Range
Industrial
Ambient
Temperature
VDD
VDDQ
–40 °C to +85 °C 2.5 V – 5% / + 5% 2.5 V – 5%
to VDD
Electrical Characteristics
Over the Operating Range
Parameter [11, 12]
Description
Test Conditions
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
For 2.5 V I/O, IOH =–1.0 mA
VOL
Output LOW Voltage
For 2.5 V I/O, IOL=1.0 mA
For 2.5 V I/O
Min
Max
Unit
2.375
2.625
V
2.375
VDD
V
2.0
–
V
–
0.4
V
Input HIGH Voltage
[11]
For 2.5 V I/O
1.7
VDD + 0.3 V
V
VIL
Input LOW Voltage
[11]
For 2.5 V I/O
–0.3
0.7
V
IX
Input Leakage Current except ZZ GND  VI  VDDQ
and MODE
–5
5
A
Input Current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input Current of ZZ
Input = VSS
–5
–
A
Input = VDD
–
30
A
Output Leakage Current
GND  VI  VDDQ, Output Disabled
–5
5
A
VDD Operating Supply Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
6.5 ns cycle,
133 MHz
–
305
mA
ISB1
Automatic CE Power Down
Current – TTL Inputs
VDD = Max, Device Deselected, 6.5 ns cycle,
133 MHz
VIN  VIH or VIN  VIL,
f = fMAX, inputs switching
–
170
mA
ISB2
Automatic CE Power Down
Current – CMOS Inputs
VDD = Max, Device Deselected, 6.5 ns cycle,
VIN  0.3 V or VIN > VDD – 0.3 V, 133 MHz
f = 0, inputs static
–
120
mA
ISB3
Automatic CE Power Down
Current – CMOS Inputs
VDD = Max, Device Deselected, 6.5 ns cycle,
VIN  0.3 V or VIN > VDDQ – 0.3 V, 133 MHz
f = fMAX, inputs switching
–
170
mA
ISB4
Automatic CE Power Down
Current – TTL Inputs
VDD = Max, Device Deselected, 6.5 ns cycle,
VIN  VDD – 0.3 V or VIN  0.3 V, 133 MHz
f = 0, inputs static
–
135
mA
VIH
IOZ
IDD
[13]
Notes
11. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
12. TPower-up: assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
13. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-15013 Rev. *N
Page 10 of 22
CY7C1471BV25
Capacitance
Parameter [14]
Description
Test Conditions
100-pin TQFP
Max
Unit
6
pF
5
pF
CADDRESS
Address input capacitance
CDATA
Data input capacitance
CCTRL
Control input capacitance
8
pF
CCLK
Clock input capacitance
6
pF
CIO
Input-Output capacitance
5
pF
TA = 25°C, f = 1 MHz,
VDD = 2.5 V, VDDQ = 2.5 V
Thermal Resistance
Parameter [14]
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test
methods
and
procedures
for
measuring
thermal
impedance,
according to EIA/JESD51.
24.63
C/W
2.28
C/W
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
2.5 V I/O Test Load
R = 1667 
2.5 V
OUTPUT
Z0 = 50 
10%
R = 1538 
VL = 1.25 V
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50 
(b)
 1 ns
 1 ns
(c)
Note
14. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-15013 Rev. *N
Page 11 of 22
CY7C1471BV25
Switching Characteristics
Over the Operating Range
Parameter [15, 16]
Description
tPOWER[17]
133 MHz
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock Cycle Time
7.5
–
ns
tCH
Clock HIGH
2.5
–
ns
tC]L
Clock LOW
2.5
–
ns
Output Times
tCDV
Data Output Valid After CLK Rise
–
6.5
ns
tDOH
Data Output Hold After CLK Rise
2.5
–
ns
3.0
–
ns
–
3.8
ns
–
3.0
ns
0
–
ns
–
3.0
ns
[18, 19, 20]
tCLZ
Clock to Low Z
tCHZ
Clock to High Z [18, 19, 20]
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
OE LOW to Output Low Z
[18, 19, 20]
OE HIGH to Output High Z
[18, 19, 20]
Setup Times
tAS
Address Setup Before CLK Rise
1.5
–
ns
tALS
ADV/LD Setup Before CLK Rise
1.5
–
ns
tWES
WE, BWX Setup Before CLK Rise
1.5
–
ns
tCENS
CEN Setup Before CLK Rise
1.5
–
ns
tDS
Data Input Setup Before CLK Rise
1.5
–
ns
tCES
Chip Enable Setup Before CLK Rise
1.5
–
ns
tAH
Address Hold After CLK Rise
0.5
–
ns
tALH
ADV/LD Hold After CLK Rise
0.5
–
ns
tWEH
WE, BWX Hold After CLK Rise
0.5
–
ns
Hold Times
tCENH
CEN Hold After CLK Rise
0.5
–
ns
tDH
Data Input Hold After CLK Rise
0.5
–
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
–
ns
Notes
15. Timing reference level is 1.25 V when VDDQ = 2.5 V.
16. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted.
17. This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD(minimum) initially, before a read or write operation can be initiated.
18. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 11. Transition is measured ±200 mV from steady-state voltage.
19. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z before Low Z under the same system conditions.
20. This parameter is sampled and not 100% tested.
Document Number: 001-15013 Rev. *N
Page 12 of 22
CY7C1471BV25
Switching Waveforms
Figure 3. Read/Write Timing [21, 22, 23]
1
2
3
t CYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW X
A1
ADDRESS
t AS
A2
A4
A3
t CDV
t AH
t DOH
t CLZ
DQ
D(A1)
t DS
D(A2)
Q(A3)
D(A2+1)
t OEV
Q(A4+1)
Q(A4)
t OELZ
W RITE
D(A1)
W RITE
D(A2)
D(A5)
Q(A6)
D(A7)
W RITE
D(A7)
DESELECT
t OEHZ
t DH
OE
COM M AND
t CHZ
BURST
W RITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
t DOH
W RITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes
21. For this waveform ZZ is tied LOW.
22. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.
23. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 001-15013 Rev. *N
Page 13 of 22
CY7C1471BV25
Switching Waveforms (continued)
Figure 4. NOP, STALL and DESELECT Cycles [24, 25, 26]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS
A5
t CHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
t DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
DON’T CARE
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Notes
24. For this waveform ZZ is tied LOW.
25. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.
26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 001-15013 Rev. *N
Page 14 of 22
CY7C1471BV25
Switching Waveforms (continued)
Figure 5. ZZ Mode Timing [27, 28]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
27. Device must be deselected when entering ZZ mode. See Truth Table on page 8 for all possible signal conditions to deselect the device.
28. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-15013 Rev. *N
Page 15 of 22
CY7C1471BV25
Ordering Information
Cypress offers other versions of this type of product in different configurations and features. The following table contains only the
list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products, or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
133
Ordering Code
CY7C1471BV25-133AXI
Package
Diagram
Part and Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
lndustrial
Ordering Code Definitions
CY 7
C 147X B V25 - 133 XX X
X
Temperature Range: X = I
I = Industrial
Pb-free
Package Type: XX = A
A = 100-pin TQFP
Frequency Range: 133 MHz
V25 = 2.5 V
Die Revision
147X = 1471
1471 = FT, 2 Mb × 36 (72 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-15013 Rev. *N
Page 16 of 22
CY7C1471BV25
Package Diagrams
Figure 6. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 001-15013 Rev. *N
Page 17 of 22
CY7C1471BV25
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BWS
Byte Write Select
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
EIA
Electronic Industries Alliance
µA
microampere
FBGA
Fine-Pitch Ball Grid Array
mA
milliampere
I/O
Input/Output
mm
millimeter
JEDEC
Joint Electron Devices Engineering Council
ms
millisecond
MHz
megahertz
LSB
Least Significant Bit
MSB
Most Significant Bit
OE
Output Enable
SRAM
Static Random Access Memory
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 001-15013 Rev. *N
Symbol
Unit of Measure
ns
nanosecond

ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 18 of 22
CY7C1471BV25
Document History Page
Document Title: CY7C1471BV25 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture
Document Number: 001-15013
Orig. of
Change
Rev.
ECN No.
Issue Date
**
1024500
See ECN
*A
1274731
See ECN
VKN /
AESA
Updated Switching Waveforms (Corrected typo in the “NOP, STALL and
DESELECT Cycles” waveform (Figure 4)).
*B
1562503
See ECN
VKN /
AESA
Updated Features (Removed 1.8 V I/O supply information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed 1.8 V I/O
supply information).
Removed the section “1.8 V TAP AC Test Conditions”.
Removed the section “1.8 V TAP AC Output Load Equivalent”.
Updated TAP DC Electrical Characteristics and Operating Conditions
(Removed 1.8 V I/O supply information).
Updated Electrical Characteristics (Removed 1.8 V I/O supply information).
Updated AC Test Loads and Waveforms (Removed 1.8 V I/O supply
information).
Updated Switching Characteristics (Removed 1.8 V I/O supply information).
*C
1897447
See ECN
VKN /
AESA
Updated Electrical Characteristics (Added Note 13 and referred the same note
in IDD parameter).
*D
2082487
See ECN
VKN
*E
2159486
See ECN
VKN /
PYRS
*F
2898501
03/24/2010
NJY
Updated Ordering Information (Removed inactive part numbers).
Updated Package Diagrams.
*G
3207526
03/28/2011
NJY
Updated Ordering Information (Updated part numbers) and added Ordering
Code Definitions.
Updated Package Diagrams.
Updated in new template.
*H
3256583
05/13/2011
NJY
Added Acronyms and Units of Measure.
Document Number: 001-15013 Rev. *N
Description of Change
VKN /
New data sheet.
KKVTMP
Changed status from Preliminary to Final.
Minor Change (Moved to the external web).
Page 19 of 22
CY7C1471BV25
Document History Page (continued)
Document Title: CY7C1471BV25 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture
Document Number: 001-15013
Orig. of
Change
Rev.
ECN No.
Issue Date
*I
3544389
03/07/2012
PRIT / NJY Updated Features (Removed CY7C1473BV25 related information).
Updated Functional Description (Removed CY7C1473BV25 related
information, removed “For best practice recommendations, refer to the
Cypress application note AN1064, SRAM System Guidelines.”).
Updated Selection Guide (Removed 100 MHz related information).
Removed Logic Block Diagram – CY7C1473BV25.
Updated Pin Configurations (Removed CY7C1473BV25 related information).
Updated Functional Overview (Removed CY7C1473BV25 related
information).
Updated Truth Table (Removed CY7C1473BV25 related information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed
CY7C1471BV25 and CY7C1473BV25 related information).
Updated Identification Register Definitions (Removed CY7C1473BV25 related
information).
Updated Scan Register Sizes (Removed Bit Size (× 36) and Bit Size (× 18)
columns).
Removed “Boundary Scan Exit Order (2 M × 36)” and “Boundary Scan Exit
Order (4 M × 18)”.
Updated Electrical Characteristics (Removed 100 MHz related information).
Updated Capacitance (Removed 165-ball FBGA package related information).
Updated Thermal Resistance (Removed 165-ball FBGA package related
information).
Updated Switching Characteristics (Removed 100 MHz related information).
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams.
Replaced IO with I/O in all instances across the document.
*J
3564344
03/28/2012
PRIT / NJY Updated Features (Included 165-ball FBGA package related information).
Updated Pin Configurations (Included 165-ball FBGA package related
information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Included
CY7C1471BV25 related information).
Updated Identification Register Definitions (Included CY7C1471BV25 related
information).
Updated Scan Register Sizes (Included 165-ball FBGA package related
information, included Bit Size (× 36) column).
Included Boundary Scan Exit Order.
Updated Operating Range (Included Commercial Temperature range).
Updated Capacitance (Included 165-ball FBGA package related information).
Updated Thermal Resistance (Included 165-ball FBGA package related
information).
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams.
*K
4396347
06/02/2014
PRIT
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
spec 51-85167 – Changed revision from *B to *C.
Updated to new template.
Completing Sunset Review.
*L
4575272
11/20/2014
PRIT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*M
4785434
06/03/2015
PRIT
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
Spec 51-85165 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
Document Number: 001-15013 Rev. *N
Description of Change
Page 20 of 22
CY7C1471BV25
Document History Page (continued)
Document Title: CY7C1471BV25 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture
Document Number: 001-15013
Rev.
ECN No.
Issue Date
Orig. of
Change
*N
5267388
05/11/2016
PRIT
Document Number: 001-15013 Rev. *N
Description of Change
Removed references to obsolete devices.
Updated the template.
Page 21 of 22
CY7C1471BV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
Technical Support
cypress.com/support
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2007-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-15013 Rev. *N
Revised May 11, 2016
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc.
Page 22 of 22
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