AN96589 DESIGNING WITH CYPRESS 1-MB QUAD SPI nvSRAM.pdf

AN96589
Designing with Cypress 1-Mb Quad SPI nvSRAM
Author: Suhail Zain
Associated Project: No
Associated Part Family: CY14V101xS
Software Version: None
Related Application Notes: AN43593
AN96589 discusses the Quad SPI (QSPI) and shows how to design with Cypress’s 1-Mb QSPI nvSRAM. QSPI is an
enhancement of the standard SPI protocol that provides four times the data throughput while maintaining the
compact form factor of the standard serial SPI. System designs using QSPI devices occupy less board space and
ultimately lower system costs.
Contents
1
2
3
Introduction ...............................................................1
QSPI Overview .........................................................2
QSPI Instruction Protocol .........................................4
3.1
Command Sequence Examples ......................5
4
PCB Layout Guides ................................................ 17
4.1
Power Supply Decoupling .............................. 17
4.2
Clock Routing ................................................ 17
1
4.3
Data Signal Routing ....................................... 17
5
Summary ................................................................ 17
Worldwide Sales and Design Support ............................. 19
Products ..................................................................... 19
®
PSoC Solutions ........................................................ 19
Cypress Developer Community .................................. 19
Technical Support ...................................................... 19
Introduction
Cypress’s 1-Mb QSPI nvSRAM is a high-performance nonvolatile SRAM product that offers truly random memory
accesses (writes and reads). It is a monolithic integrated circuit with a quad SPI, which allows writing and reading the
memory using a single (one I/O channel for one bit per clock cycle), dual (two I/O channels for two bits per clock
cycle), or quad (four I/O channels for four bits per clock cycle) configuration via a function-rich command set..
The QSPI nvSRAM architecture incorporates Cypress’s unique SRAM with silicon-oxide-nitride-oxide semiconductor
(SONOS) nonvolatile elements. It blends the performance characteristics of a high-speed SRAM with a nonvolatile
memory. The quad serial interface in QSPI nvSRAM conforms to the de facto industry-standard Quad Serial
Peripheral Interface. The instruction set includes standard Quad SPI opcodes along with nvSRAM-specific functions
and performance-oriented new features. The QSPI nvSRAM signals include SCK (serial clock), SI, and SO (for
command/response and data input/output) and control signals CS#, HOLD#, and WP#. This hardware interface
creates a low-pin-count device that reduces package size, PCB area, and overall system cost.
This application note discusses the QSPI and demonstrates how to use the 1-Mb QSPI nvSRAM in system designs.
www.cypress.com
Document No. 001-96589 Rev. *A
1
Designing with Cypress 1-Mb Quad SPI nvSRAM
2
QSPI Overview
QSPI is a communications protocol for interfacing a microcontroller (master) and one or more external memories
(slaves). It is based on the popular Serial Peripheral Interface (SPI). SPI has four connections between the master
and slave: Data In, Data Out, Clock (only uses the rising edge), and Chip Select (indicates which slave the SPI
master is using). QSPI has six connections between the master and slave: four bidirectional serial data links, Clock
(which uses either the rising edge or rising and falling edges), and Chip Select. The extra data links allow QSPI to
have approximately four times more data throughput than SPI. With the high clock rate, the QSPI protocol can
generate comparable data transfer rates to legacy parallel memory interfaces with 25 to 35 connections. Reducing
the IC-to-IC connections by this factor of five requires instructions that mix address and data across the four serial
channels.
Figure 1 shows the connectivity configuration with a host (Master SPI/QSPI) for 1-Mb QSPI nvSRAM in the SPI and
QSPI configurations respectively.
Figure 1. SPI/QSPI Connectivity Overview
Single I/O - SPI Mode
SCK
VCC
VCCQ
VSS
SCK
MOSI
CPU
Master
SPI
Hold#
SI
WP#
VCCQ
MISO
VCAP
CS#
HSB#
VCC
1-Mbit Quad SPI
nvSRAM
CY14V101QS
HOLD#
VSS
CS#
WP#
SO
Quad I/O – Quad SPI Mode
VCC
VCCQ
VSS
CPU
Master
QPI
SCK
SCK
I/O0
SI (I/O0)
I/O2
VCCQ
I/O1
VCAP
CS#
HSB#
Hold# (I/O3)
VCC
1-Mbit Quad SPI
nvSRAM
CY14V101QS
I/O3
VSS
WP# (I/O2)
www.cypress.com
Document No. 001-96589 Rev. *A
CS#
SO (I/O1)
2
Designing with Cypress 1-Mb Quad SPI nvSRAM
As can be seen in Figure 1, QSPI nvSRAM provides multiple I/O functionality by switching pin functions to support
both a unidirectional and a bidirectional data bus. In SPI mode, the command, address, and data are serial using the
SI and SO unidirectional channels for communication. In QSPI mode, the command, address, and data are also
serial but use the SI (I/O0), SO (I/O1), WP# (I/O2), and Hold# (I/O3) bidirectional channels to serve x4 I/O
communication. In QSPI mode, the hardware write protect and communication hold features are not present, as the
WP# and HOLD# pins act as I/O2 and I/O3 respectively. QSPI nvSRAM also supports Dual SPI (two data channels)
mode where SI (I/O0) and SO (I/O1) are used in bidirectional mode for command, address, and data communication.
However, in Dual SPI mode, the hardware write protect and communication hold features are maintained.
Table 1 shows the w-x-y-z notation for each instruction supported by 1-Mb QSPI nvSRAM, where “w” specifies the
number of channels for the command, “x” specifies the number of channels for the address, “y” specifies the number
of channels for the mode/dummy, and “z” specifies the number of channels for data.
Table 1. w-x-y-z Instruction Set Notation
Instruction Description
Instruction
Name
Opcode
SPI
DPI
QPI
SPI
Extended
Control
Write Disable
WRDI
04h
[1,-,-,-]
[2,-,-,-]
[4,-,-,-]
Write Enable
WREN
06h
[1,-,-,-]
[2,-,-,-]
[4,-,-,-]
Enable DPI
DPIEN
37h
[1,-,-,-]
Enable QPI
QPIEN
38h
[1,-,-,-]
Enable SPI
SPIEN
FFh
Read
READ
03h
FastRead
FAST_READ
0Bh
Dual Out (Fast) Read
DOR
3Bh
[1,1,1,2]
Quad Out (Fast) Read
QOR
6Bh
[1,1,1,4]
Dual IO (Fast) Read
DIOR
BBh
[1,2,2,2]
Quad IO (Fast) Read
QIOR
EBh
[1,4,4,4]
Write
WRITE
02h
Dual Input Write
DIW
A2h
[1,1,-,2]
Quad Input Write
QIW
32h
[1,1,-,4]
Dual IO Write
DIOW
A1h
[1,2,-,2]
Quad IO Write
QIOW
D2h
[1,4,-,4]
Software Reset Enable
RSTEN
66h
[1,-,-,-]
[2,-,-,-]
[4,-,-,-]
Software Reset
RESET
99h
[1,-,-,-]
[2,-,-,-]
[4,-,-,-]
Read RTC
RDRTC
56h
[1,1,-,1]
[2,2,-,2]
[4,4,-,4]
Write RTC
WRRTC
55h
[1,1,-,1]
[2,2,-,2]
[4,4,-,4]
Fast Read RTC
FAST_RDRTC
57h
[1,1,1,1]
[2,2,2,2]
[4,4,4,4]
Enter Hibernate mode
HIBEN
BAh
[1,-,-,-]
[2,-,-,-]
[4,-,-,-]
Enter Sleep mode
SLEEP
B9h
[1,-,-,-]
[2,-,-,-]
[4,-,-,-]
Exit Sleep mode
EXSLP
ABh
[1,-,-,-]
[2,-,-,-]
[4,-,-,-]
[4,-,-,-]
[2,-,-,-]
[2,-,-,-]
[4,-,-,-]
[1,1,-,1]
[2,2,2,2]
[4,4,4,4]
[1,1,1,1]
[2,2,2,2]
[4,4,4,4]
Memory Read
Memory Write
[1,1,-,1]
[2,2,-,2]
[4,4,-,4]
SR Commands
www.cypress.com
Document No. 001-96589 Rev. *A
3
Designing with Cypress 1-Mb Quad SPI nvSRAM
Instruction
Name
Instruction Description
Opcode
SPI
DPI
QPI
SPI
Extended
Register Commands
Read Status Register
RDSR
05h
[1,-,-,1]
[2,-,-,2]
[4,-,-,4]
Write Status Register
WRSR
01h
[1,-,-,1]
[2,-,-,2]
[4,-,-,4]
Read Configuration Register
RDCR
35h
[1,-,-,1]
[2,-,-,2]
[4,-,-,4]
Write Configuration Register
WRCR
87h
[1,-,-,1]
[2,-,-,2]
Read ID Register
RDID
9Fh
[1,-,-,1]
[2,-,-,2]
[4,-,-,4]
Fast Read ID Register
FAST_RDID
9Eh
[1,-,1,1]
[2,-,2,2]
[4,-,4,4]
Write Serial Number Register
WRSN
C2h
[1,-,-,1]
[2,-,-,2]
[4,-,-,4]
Read Serial Number Register
RDSN
C3h
[1,-,-,1]
[2,-,-,2]
[4,-,-,4]
Fast Read Serial Number Register
FAST_RDSN
C9h
[1,-,1,1]
[2,-,2,2]
[4,-,4,4]
STORE
STORE
8Ch
[1,-,-,-]
[2,-,-,-]
[4,-,-,-]
RECALL
RECALL
8Dh
[1,-,-,-]
[2,-,-,-]
[4,-,-,-]
AutoStore Enable
ASEN
8Eh
[1,-,-,-]
[2,-,-,-]
[4,-,-,-]
AutoStore Disable
ASDI
8Fh
[1,-,-,-]
[2,-,-,-]
[4,-,-,-]
NV specific Commands
Mode Bits
Mode Bit (Set,Reset)
3
Axh, !Axh
QSPI Instruction Protocol
All communication between the host and the 1-Mb QSPI nvSRAM is in the form of instructions. Each instruction
begins with a command that selects the type of information transfer to be performed. Instructions may also have an
address, command modifier (mode bits), latency (dummy cycles), and data transfer to or from the memory or
registers. All instructions are executed serially between the host and 1-Mb QSPI nvSRAM.
The structure of the instructions is as follows:



Each instruction begins with CS# going low and ends with CS# going high.

The command may be standalone, or it may be followed by address bits to select a location within the memory
address space or register map. The address is 24 bits for memory and 8 bits for registers.

Some read instructions may require latency (dummy cycles) after the address bits. SCK continues to toggle, and
data bits are driven at the end of the latency cycle.

Some commands send a command modifier, called “mode bits,” following the address to indicate that the next
instruction will be of the same type with an implied command. Thus, the next instruction will not provide a
command byte, only a new address and mode bits. It is generally referred to as “execute in place (XIP).”


Write or read data follows the address or mode bits.
SCK (serial clock) marks the transfer of each bit or group of bits.
Each instruction begins with an 8-bit command. The command selects the type of device operation to be
performed.
CS# must go high after the instruction. For instructions that do not return data, the CS# signal must go high after
the eighth bit. For write instructions, CS# must go high after the last data byte that is transferred. Otherwise, the
command is rejected.
www.cypress.com
Document No. 001-96589 Rev. *A
4
Designing with Cypress 1-Mb Quad SPI nvSRAM
3.1

SCK continues toggling while CS# is low during any read/write instruction that executes the burst data mode. In
this mode, the address is incremented automatically inside the device while data is continuously shifted in or out
of the device.

All the commands, the address, and mode bits are shifted into the device with the most-significant bits first. The
data bits are shifted in or out of the device with the most significant bits first as well.


All attempts to access the device during STORE/RECALL operations are ignored.
Depending on the instruction, the execution time varies. The Read Status Register instruction can be used to
determine if the device is busy and whether the instruction has completed execution.
Command Sequence Examples
The following sections provide sequences for different instructions. The timing details for each command are
specified in the Cypress 1-Mb QSPI nvSRAM datasheets.
3.1.1
R E A D I n s t r u c t i o n – Ac c e s s t h e M e m o r y A r r a y
Figure 2 shows the memory read instruction sequence in SPI mode. Here, if CS# is not brought high after the first
read data byte and SCK is continuously toggled, burst data mode is executed. To end the instruction, CS# must be
brought high.
Figure 2. READ Functional Flow Chart – SPI Mode
READ – SPI
Start
CS# goes Low
I/O Mode: SPI
Command
1-Byte
READ
Read
03h
Address
3-Bytes
Read Data
1-Byte
Data
Memory Core
No
Yes
BURST
CS# goes High
END
Figure 3 shows the memory read instruction sequence in Dual SPI mode. It is assumed that the device starts in SPI
mode, enables Dual SPI mode, and is brought back to SPI mode after the instruction sequence. Here, a single cycle
of latency is required after the address bits. Again, if CS# is kept low after the first read data byte and SCK is
continuously toggled, the burst data mode is executed. To end the instruction, CS# must be brought high.
www.cypress.com
Document No. 001-96589 Rev. *A
5
Designing with Cypress 1-Mb Quad SPI nvSRAM
Figure 3. READ Functional Flow Chart – Dual SPI Mode
READ – DPI
Start
DPIEN
37h
CS# goes Low
I/O Mode: SPI
Command
1-Byte
Enable DPI
I/O Mode: DPI
CS# goes High
CS# goes Low
Command
1-Byte
READ
Read
03h
Address
3-Bytes
Dummy Clock Cycles
(1)
Read Data
1-Byte
Data
Memory Core
No
Yes
BURST
CS# goes High
CS# goes Low
I/O Mode: SPI
SPIEN
FFh
Command
1-Byte
Disable DPI
CS# goes High
END
Figure 4 shows the memory read instruction sequence in QSPI mode. It is assumed that the device starts in SPI
mode, enables QSPI mode, and is brought back to SPI mode after the instruction sequence. Here, a single cycle of
latency is again required after the address bits. If CS# is not brought high after the first read data byte and SCK is
continuously toggled, the burst data mode is executed. To end the instruction, CS# must be brought high.
www.cypress.com
Document No. 001-96589 Rev. *A
6
Designing with Cypress 1-Mb Quad SPI nvSRAM
Figure 4. READ Functional Flow Chart – QSPI Mode
READ – QPI
Start
CS# goes Low
I/O Mode: SPI
Command
1-Byte
WRCR
WRCR
87h
Write Data
1-Byte
CS# goes High
0x42
Configuration Register
I/O Mode: Quad
CS# goes Low
Command
1-Byte
Enable QPI
QPIEN
38h
Mode: QPI
CS# goes High
CS# goes Low
Command
1-Byte
READ
Read
03h
Address
3-Bytes
Dummy Clock Cycles
(1)
Read Data
1-Byte
Data
Memory Core
No
Yes
BURST
CS# goes High
CS# goes Low
SPIEN
FFh
Command
1-Byte
Disable QPI
CS# goes High
CS# goes Low
WRCR
87h
Command
1-Byte
WRCR
Write Data
1-Byte
CS# goes High
0x40
Configuration Register
I/O Mode: SPI
END
www.cypress.com
Document No. 001-96589 Rev. *A
7
Designing with Cypress 1-Mb Quad SPI nvSRAM
3.1.2
F AS T _ R E A D I n s t r u c t i o n s – Ac c e s s t h e M e m o r y A r r a y
Figure 5 shows the memory fast read instruction sequence in SPI mode. The fast read instruction can be executed up
to 108 MHz. Here, a mode byte option is shown after the address bits to determine whether XIP is being carried out.
Also, if CS# is not brought high after the first read data byte and SCK is continuously toggled, the burst data mode is
executed. To end the instruction, CS# must be brought high.
Figure 5. FAST_READ Functional Flow Chart – SPI Mode
FAST_READ – SPI
Start
CS# goes Low
FAST_READ
0Bh
I/O Mode: SPI
Command
1-Byte
FAST_READ
Yes
No
XIP
Byte Axh
Address
3-Bytes
Address
3-Bytes
Mode Byte
(8 Clock Cycles)
Mode Byte
(8 Clock Cycles)
Read Data
1-Byte
Data
Memory Core
Read Data
1-Byte
No
Yes
Byte !Axh
No
BURST
Yes
BURST
CS# goes High
CS# goes Low
CS# goes High
END
Figure 6 shows the memory fast read instruction sequence in Dual SPI mode. It is assumed that the device starts in
SPI mode, enables Dual SPI mode, and is brought back to SPI mode after the instruction sequence. Here, again a
mode byte option is shown after the address bits to determine whether XIP is being carried out. Also, if CS# is not
brought high after the first read data byte and SCK is continuously toggled, the burst data mode is executed. To end
the instruction, CS# must be brought high.
www.cypress.com
Document No. 001-96589 Rev. *A
8
Designing with Cypress 1-Mb Quad SPI nvSRAM
Figure 6. FAST_READ Functional Flow Chart – Dual SPI Mode
FAST_READ – DPI
Start
CS# goes Low
Command
1-Byte
Enable DPI
DPIEN
37h
I/O Mode: SPI
Mode: DPI
CS# goes High
CS# goes Low
FAST_READ
0Bh
Command
1-Byte
FAST_READ
Yes
No
XIP
Byte Axh
Address
3-Bytes
Address
3-Bytes
Mode Byte
(4 Clock Cycles)
Mode Byte
(4 Clock Cycles)
Read Data
1-Byte
Data
Memory Core
Read Data
1-Byte
No
Yes
Byte !Axh
No
BURST
Yes
BURST
CS# goes High
CS# goes Low
CS# goes High
CS# goes Low
I/O Mode: SPI
SPIEN
FFh
Command
1-Byte
Disable DPI
CS# goes High
END
Figure 7 shows the memory fast read instruction sequence in QSPI mode. It is assumed that the device starts in SPI
mode, enables QSPI mode, and is brought back to SPI mode after the instruction sequence. Here, again a mode byte
option is shown after the address bits to determine whether XIP is being carried out. Also, if CS# is not brought high
after the first read data byte and SCK is continuously toggled, the burst data mode is executed. To end the
instruction, CS# must be brought high.
www.cypress.com
Document No. 001-96589 Rev. *A
9
Designing with Cypress 1-Mb Quad SPI nvSRAM
Figure 7. FAST_READ Functional Flow Chart – QSPI Mode
FAST_READ – QPI
Start
CS# goes Low
I/O Mode: SPI
Command
1-Byte
WRCR
WRCR
87h
Write Data
1-Byte
0x42
Configuration Register
CS# goes High
CS# goes Low
Command
1-Byte
Enable QPI
QPIEN
38h
I/O Mode: Quad
Mode: QPI
CS# goes High
CS# goes Low
FAST_READ
0Bh
Command
1-Byte
FAST_READ
Yes
No
XIP
Byte Axh
Address
3-Bytes
Address
3-Bytes
Mode Byte
(2 Clock Cycles)
Mode Byte
(2 Clock Cycles)
Read Data
1-Byte
Data
Memory Core
Read Data
1-Byte
No
Yes
Byte !Axh
No
BURST
Yes
BURST
CS# goes High
CS# goes Low
CS# goes High
CS# goes Low
SPIEN
FFh
Command
1-Byte
Disable QPI
CS# goes High
CS# goes Low
WRCR
87h
Command
1-Byte
WRCR
Write Data
1-Byte
CS# goes High
0x40
Configuration Register
I/O Mode: SPI
END
www.cypress.com
Document No. 001-96589 Rev. *A
10
Designing with Cypress 1-Mb Quad SPI nvSRAM
3.1.3
WRITE Instruction – Access the Memory Arra y
Figure 8 shows the memory write instruction sequence in SPI mode. First, Write Enable Latch (WEL) must be set
before any WRITE operation to the memory can be performed. Afterward, if CS# is not brought high following the first
write data byte and SCK is continuously toggled, the burst data mode is executed. Finally, WEL should be disabled
since a write command to memory does not reset WEL. To end the instruction, CS# must be brought high.
Figure 8. WRITE Functional Flow Chart – SPI Mode
WRITE – SPI
Start
CS# goes Low
I/O Mode: SPI
Command
1-Byte
Write Enable
WREN
06h
CS# goes High
CS# goes Low
Command
1-Byte
WRITE
WRITE
02h
Address
3-Bytes
Write Data
1-Byte
Data
Memory Core
No
Yes
BURST
CS# goes High
CS# goes Low
WRDI
04h
Command
1-Byte
Write Disable
CS# goes High
END
Figure 9 shows the memory write instruction sequence in Dual SPI mode. It is assumed that the device starts in SPI
mode, enables Dual SPI mode, and is brought back to SPI mode after the instruction sequence. First, Write Enable
Latch (WEL) must be set before any WRITE operation to the memory can be performed. Afterward, if CS# is kept low
after the first write data byte and SCK is continuously toggled, the burst data mode is executed. Finally, WEL should
be disabled since a write command to memory does not reset WEL. To end the instruction, CS# must be brought
high.
www.cypress.com
Document No. 001-96589 Rev. *A
11
Designing with Cypress 1-Mb Quad SPI nvSRAM
Figure 9. WRITE Functional Flow Chart – Dual SPI Mode
WRITE – DPI
Start
DPIEN
37h
CS# goes Low
I/O Mode: SPI
Command
1-Byte
Enable DPI
I/O Mode: DPI
CS# goes High
CS# goes Low
Command
1-Byte
Write Enable
WREN
06h
CS# goes High
CS# goes Low
Command
1-Byte
WRITE
WRITE
02h
Address
3-Bytes
Write Data
1-Byte
Data
Memory Core
No
Yes
BURST
CS# goes High
CS# goes Low
WRDI
04h
Command
1-Byte
Write Disable
CS# goes High
CS# goes Low
I/O Mode: SPI
SPIEN
FFh
Command
1-Byte
Disable DPI
CS# goes High
END
Figure 10 shows the memory write instruction sequence in QSPI mode. It is assumed that the device starts in SPI
mode, enables QSPI mode, and is brought back to SPI mode after the instruction sequence. First, Write Enable Latch
(WEL) must be set before any WRITE operation to the memory can be performed. Afterward, if CS# is not brought
high after the first write data byte and SCK is continuously toggled, the burst data mode is executed. Finally, WEL will
need to be disabled since a write command to memory does not reset WEL to avoid any inadvertent writes. To end
the instruction, CS# must be brought high.
www.cypress.com
Document No. 001-96589 Rev. *A
12
Designing with Cypress 1-Mb Quad SPI nvSRAM
Figure 10. WRITE Functional Flow Chart – QSPI Mode
WRITE – QPI
Start
CS# goes Low
I/O Mode: SPI
Command
1-Byte
WRCR
WRCR
87h
Write Data
1-Byte
CS# goes High
0x42
Configuration Register
I/O Mode: Quad
CS# goes Low
Command
1-Byte
Enable QPI
QPIEN
38h
Mode: QPI
CS# goes High
CS# goes Low
Command
1-Byte
Write Enable
WREN
06h
CS# goes High
CS# goes Low
Command
1-Byte
WRITE
WRITE
02h
Address
3-Bytes
Write Data
1-Byte
Data
Memory Core
No
Yes
BURST
CS# goes High
CS# goes Low
WRDI
04h
Command
1-Byte
Write Disable
CS# goes High
CS# goes Low
SPIEN
FFh
Command
1-Byte
Disable QPI
CS# goes High
CS# goes Low
WRCR
87h
Command
1-Byte
WRCR
Write Data
1-Byte
CS# goes High
0x40
Configuration Register
I/O Mode: SPI
END
www.cypress.com
Document No. 001-96589 Rev. *A
13
Designing with Cypress 1-Mb Quad SPI nvSRAM
3.1.4
H I B E N I n s t r u c t i o n – P o w e r S a ve H i b e r n a t e M o d e
Figure 11 shows the hibernate instruction sequence in SPI mode. Hibernate mode is the lowest power mode with a
device leakage current of IZZ (10 µA). The hibernate instruction initiates a STORE operation (if a write instruction has
been executed before the last STORE operation) in which data is transferred from the SRAM elements to the
nonvolatile SONOS memory elements. The HIBEN operation takes tHIBEN (8 ms), and the status register WIP (Work
In Progress) bit can be polled to determine the completion status. To end the instruction, CS# must be brought high.
Figure 11. HIBEN Functional Flow Chart – SPI Mode
HIBERNATE – SPI
Start
CS# goes Low
HIBEN
BAh
I/O Mode: SPI
Command
1-Byte
HIBERNATE
CS# goes High
END
Figure 12 shows the hibernate exit instruction sequence in SPI mode. Exit from hibernate begins by bringing CS#
low, and it requires a RECALL operation where data is transferred from the nonvolatile SONOS memory elements to
SRAM elements. The HIBERNATE EXIT operation takes tWAKE (20 ms), and the status register WIP bit can be polled
to determine the completion status. To end the instruction, CS# must be brought high.
Figure 12. HIBERNATE EXIT Functional Flow Chart – SPI Mode
HIBERNATE EXIT – SPI
Start
CS# goes Low
RDSR
05h
Data
Status Register
I/O Mode: SPI
Command
1-Byte
READ Status Register
Read Data
No
WIP=1
Yes
CS# goes High
CS# goes High
END
www.cypress.com
Document No. 001-96589 Rev. *A
14
Designing with Cypress 1-Mb Quad SPI nvSRAM
3.1.5
STORE Instruction – Nonvolatile Store Operation
Figure 13 shows the store instruction sequence in SPI mode. The STORE operation transfers data from SRAM
elements to SONOS nonvolatile elements in QSPI nvSRAM. The completion status of STORE can be checked by
polling the WIP bit in the status register. QSPI nvSRAM also provides a FAULT register, where checking the STORE
bit once WIP goes low shows successful completion. To end the instruction, CS# must be brought high.
Figure 13. STORE Functional Flow Chart – SPI Mode
STORE - SPI
Start
CS# goes Low
STORE
8Ch
I/O Mode: SPI
Command
1-Byte
STORE
CS# goes High
CS# goes Low
RDSR
05h
Data
Status Register
Command
1-Byte
READ Status Register
Read Data
No
WIP=1
Yes
CS# goes High
CS# goes High
END
www.cypress.com
Document No. 001-96589 Rev. *A
15
Designing with Cypress 1-Mb Quad SPI nvSRAM
3.1.6
R E C A L L I n s t r u c t i o n – N o n vo l a t i l e R e c a l l O p e r a t i o n
Figure 14 shows the recall instruction sequence in SPI mode. The RECALL operation transfers data from SONOS
nonvolatile elements to SRAM elements in Quad SPI nvSRAM. The completion status of RECALL can be checked by
polling the WIP bit in the status register. QSPI nvSRAM also provides a FAULT register, where checking the RECALL
bit once WIP goes low shows successful completion. To end the instruction, CS# must be brought high.
Figure 14. RECALL Functional Flow Chart – SPI Mode
RECALL - SPI
Start
CS# goes Low
RECALL
8Dh
I/O Mode: SPI
Command
1-Byte
RECALL
CS# goes High
CS# goes Low
RDSR
05h
Data
Status Register
Command
1-Byte
READ Status Register
Read Data
No
WIP=1
Yes
CS# goes High
CS# goes High
END
www.cypress.com
Document No. 001-96589 Rev. *A
16
Designing with Cypress 1-Mb Quad SPI nvSRAM
4
PCB Layout Guides
This section provides general layout recommendations.
4.1
Power Supply Decoupling
The Cypress 1-Mb QSPI nvSRAM has two power supply input pins (VCC and VCCQ) and one ground pin (VSS). The
use of one 0.1-μF ceramic capacitor, normally in a 0603 or 0402 package, is recommended for decoupling each
power supply input pin. This decoupling capacitor should be placed as close as possible to the power supply input
pins. The routing of the decoupling capacitors should be optimized to achieve low inductance. Power supply trace
lengths from the package pads to the vias should be as short as possible with a trace width of approximately 0.6 mm.
It is recommended that you avoid sharing the same via with two or more decoupling capacitors.
4.2
Clock Routing
For reliable high-speed synchronous data transfers, it is essential that the clock signal have very good signal integrity.
Following are recommendations for routing the clock signal:
4.3

Run the clock signal at least 3x of the trace width away from all other signal traces. This will help keep the clock
signal clean from noise.

Use as few vias as possible for the entire path of the clock signal. Each via creates impedance changes and may
cause signal reflections.



Run the clock trace as straight as possible and avoid using serpentine routing.
Keep a continuous ground in the next layer as a reference plane.
Route the clock trace with controlled impedance, typically a 50- trace impedance with ± 5 percent tolerance.
Data Signal Routing
The Cypress 1-Mb QSPI nvSRAM supports 1-bit, 2-bit, and 4-bit data bus configurations. In 2-bit and 4-bit multiple
I/O configurations, it is important that the I/O traces are routed such that they have identical lengths, within
approximately 1 mm, to ensure equivalent propagation delays. To promote reliable data transfers for all
configurations, make sure that the propagation delays for the clock trace and all data traces are identical. The data
signals should be routed with traces of controlled impedance, typically 50 , to reduce signal reflection. Data traces
should have no 90° angle corners. The preferred method for implementing a 90° angle change is to cut the corner to
smooth the trace. To maximize signal integrity, avoid using multiple signal layers for data signal routing and ensure all
signal traces have a continuous reference plane.
5
Summary
AN96589 provided an overview of the QSPI. It introduced the instruction set and instruction protocol and then
provided a series of communication examples between a host (master) and Cypress’s 1-Mb QSPI nvSRAM (slave)
device. It also included recommendations for the PCB layout to achieve optimum performance.
www.cypress.com
Document No. 001-96589 Rev. *A
17
Designing with Cypress 1-Mb Quad SPI nvSRAM
Document History
Document Title: AN96589 - Designing with Cypress 1-Mb Quad SPI nvSRAM
Document Number: 001-96589
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
4703103
SZZX
03/27/2015
New Spec.
*A
4829487
SZZX
07/09/2015
Incorporated Instruction Opcode changes
Updated template
www.cypress.com
Document No. 001-96589 Rev. *A
18
Designing with Cypress 1-Mb Quad SPI nvSRAM
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find
the office closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
cypress.com/go/automotive
psoc.cypress.com/solutions
Clocks & Buffers
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Interface
cypress.com/go/interface
Cypress Developer Community
Lighting & Power Control
cypress.com/go/powerpsoc
Community | Forums | Blogs | Video | Training
Memory
cypress.com/go/memory
Technical Support
PSoC
cypress.com/go/psoc
cypress.com/go/support
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/usb
Wireless/RF
cypress.com/go/wireless
PSoC is a registered trademark and PSoC Creator is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks
referenced herein are the property of their respective owners.
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone
Fax
Website
: 408-943-2600
: 408-943-4730
: www.cypress.com
© Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor
Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any
license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or
safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies
Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide
patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a
personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative
works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source
Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the
right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or
use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
www.cypress.com
Document No. 001-96589 Rev. *A
19
Similar pages