V6205609 VID

REVISIONS
LTR
DESCRIPTION
DATE
APPROVED
A
Add test conditions to the table I. - phn
08-07-09
Thomas M. Hess
B
Add footnote to paragraphs 1.2.2 and 6.3.
Table I, VS = ±7.5 V condition, make changes to
open loop transimpedance gain, input bias
current (inverting and non inverting), common
mode rejection ratio, voltage output swing, and
positive power supply rejection ratio test limits.
Table I, VS = ±5.0 V condition, make changes to
open loop transimpedance gain, input offset
voltage, input bias current (inverting and non
inverting), common mode rejection ratio, current
output sinking, and positive power supply
rejection ratio test limits.
Make corrections to A1 and c dimensions under
case X. Make corrections to all dimensions
under case Y. - ro
12-06-14
Charles F. Saffle
CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24
Vendor item drawing
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PMIC N/A
PREPARED BY
Phu H. Nguyen
Original date of drawing
YY-MM-DD
CHECKED BY
Phu H. Nguyen
05-06-14
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
TITLE
MICROCIRCUIT, LINEAR, 1.8 GHz, LOW
DISTORTION, CURRENT FEEDBACK
AMPLIFIER, MONOLITHIC SILICON
APPROVED BY
Thomas M. Hess
SIZE
CODE IDENT. NO.
A
REV
AMSC N/A
DWG NO.
V62/05609
16236
B
PAGE
1
OF
12
5962-V018-12
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance 1.8 GHz, low distortion, current feedback
amplifier, with an operating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/05609
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s). 1/
Device type
Generic
01
Circuit function
THS3201-EP
1.8 GHz, low distortion, current feedback amplifier
1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter
Number of pins
X
Y 2/
8
8
JEDEC PUB 95
Package style
JEDEC MS-012
JEDEC M0-187
Plastic small outline package
Plastic small outline package
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture:
Finish designator
A
B
C
D
E
Z
1/
2/
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
Users are cautioned to review the manufacturers data manual for additional user information relating to this device.
The manufacture has changed lead frames NiPdAu to NiPdAuAg and location of assembly from their Hana facility to their
Shanghai facility. Product with a Lot Trace Code of 1CxxxxH and earlier is a NiPdAu frame from the Hana facility.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
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REV
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V62/05609
PAGE
2
1.3 Absolute maximum ratings. 3/
Supply voltage, (VS) .................................................................................................................
Input voltage, (VI): .....................................................................................................................
Output current, (IO) ...................................................................................................................
Differential input voltage, (VID) ..................................................................................................
Maximum junction temperature, (TJ) ........................................................................................
Maximum junction temperature, continuous operation, long term reliability, (TJ) .....................
Storage temperature range, (TSTG) ...........................................................................................
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds .............................................
ESD ratings:
HBM .....................................................................................................................................
CDM .....................................................................................................................................
MM .......................................................................................................................................
Package dissipation ratings:
θJC
(°C/W)
θJA 6/
(°C/W)
Case X
38.3
97.5
Case Y 7/
4.7
58.4
Package
+16.5 V
±VS
175 mA
±3.0 V
+150°C 4/
+125°C 5/
-65°C to +150°C
+300°C
+3000 V
+1500 V
+100 V
1.4 Recommended operating conditions.
Supply voltage:
Maximum dual supply .............................................................................................................. ±3.3 V to ±7.5 V
Single supply ............................................................................................................................ +6.6 V to +15.0 V
Operating free air temperature range, (TA) .................................................................................. -55°C to +125°C
3/
4/
5/
6/
7/
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods
may affect device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions
beyond those specified is not implied.
The absolute maximum temperature under any condition is limited by the constraints of the silicon process. Stresses above
these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may affect device
reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
specified is not implied.
Long term high temperature storage and/or extended used at maximum recommended operating conditions may result in a
reduction of overall device life. See figure 3 for additional information on thermal derating.
This data was taken using the JEDEC standard high K test PCB.
The devices on this drawing may incorporate a thermal pad on the underside of the chip. This act as a heatsink and must be
connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum
junction temperature which could permanently damage the device. Refer to the manufacturer for more information about utilizing
the thermally enhanced package.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
B
DWG NO.
V62/05609
PAGE
3
2. APPLICABLE DOCUMENTS
JEDEC Solid State Technology Association
JEDEC PUB 95 –
Registered and Standard Outlines for Semiconductor Devices
(Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107
or online at http://www.jedec.org)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are
as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1
Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1.
3.5.2
Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3
Wirebond life versus temperature. Wirebond life versus temperature shall be as shown in figure 3.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
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REV
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DWG NO.
V62/05609
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4
TABLE I. Electrical performance characteristics. 1/
Test
Limits
Test condition
VS = ±7.5 V, G = +2
Rf = 1 kΩ, RL = 100 Ω
unless otherwise noted
Device type: All
Typ
Over temperature
25°C
25°C
Unit
Min/
Typ/
Max
Typ
-55°C to
+125°C
AC Performance
G = +1, Rf = 1.2 kΩ
1.8
GHz
G = +2, Rf = 768 Ω
850
MHz
G = +5, Rf = 619 Ω
565
G = +10, Rf = 487 Ω
520
Bandwidth for 0.1 dB flatness
G = +2, VO = 200 mVPP, Rf = 768 Ω
380
MHz
Large signal bandwidth
G = +2, VO = 2 VPP, Rf = 715 Ω
880
MHz
Slew rate
G = +2, VO = 5-V step,
Rf = 768 Ω, Rise/Fall
5400/
4000
V/µs
G = +2, VO = 10-V step,
Rf = 768 Ω, Rise/Fall
9800/
6700
Rise and fall time
G = +2, VO = 4-V step,
Rf = 768 Ω, Rise/Fall
0.7/
0.9
Setting time to 0.1%
G = -2, VO = 2-V step
20
Small signal bandwidth, -3 dB
(VO = 200 mVPP)
Setting time to 0.01%
ns
60
Harmonic distortion
2
nd
harmonic
G = +5, f = 10 MHz,
VO = 2 VPP
rd
3 harmonic
RL = 100 Ω
-64
RL = 100 Ω
-73
dBc
Third order intermodulation distortion (IMD3)
G = +10, fc = 100 MHz,
∆f = 1 MHz, VO(envelope) = 2 VPP
-78
Noise figure
G = +10, fc = 100 MHz, RF = 255 Ω
RG = 28
11
dB
Input voltage noise
f > 10 MHz
1.65
nV/ Hz
Input current noise (non inverting)
f > 10 MHz
13.4
pA/ Hz
Input current noise (inverting)
Differential gain
Differential phase
20
G = +2, RL = 150 Ω,
Rf = 768 Ω
NTSC
0.008%
PAL
0.004%
NTSC
0.007°
PAL
0.011°
See notes at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
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CODE IDENT NO.
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REV
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TABLE I. Electrical performance characteristics – Continued. 1/
Test
Test condition
VS = ±7.5 V, G = +2
Rf = 1 kΩ, RL = 100 Ω
Single ended input
unless otherwise noted
Device type: All
Limits
Over temperature
Typ
Input offset voltage
VCM = 0 V, RL = 1 kΩ
±0.7
±4
Average offset voltage drift
±13
±65
Average bias current drift (-)
±14
±40
Average bias current drift (+)
Input resistance
±5.1
71
16
780
Inverting
11
Input capacitance
Output
Non inverting
1
Voltage output swing
RL = 1 kΩ
Current output, sourcing
Current output sinking
Closed loop output impedance
Power supply
Minimum operating voltage
Maximum operating voltage
Maximum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (-PSRR)
RL = 100 Ω
RL = 20 Ω
G = +1, f = 1 MHz
±6
mV
Max
±13
µV/°C
Typ
100
200
RL = 1 kΩ
VCM = ±3.75 V
Open loop
Non inverting
Min
-55°C to
+125°C
300
Input
Common mode input range
Common mode rejection ratio
Inverting input impedance, Zin
kΩ
25°C
VO = ±4 V, RL = 1 kΩ
Input bias current (non inverting)
Min/
Typ/
Max
25°C
DC performance
Open loop transimpedance gain
Input bias current (inverting)
Unit
±5
58
±90
µA
Max
±400
nA/°C
Typ
±60
µA
Max
±400
nA/°C
Typ
±5
53
V
dB
Min
Min
Typ
Ω
kΩ
Ω
pF
±6
±5.9
±5.7
V
Min
±5.8
115
100
0.01
±5.7
105
85
±5.35
100
80
V
mA
mA
Ω
Min
Min
Min
Typ
VS+ = 7 V to 8 V, RL = 1 kΩ
14
69
±3.3
±7.5
18
60
VS- = -7 V to -8 V, RL = 1 kΩ
65
58
±3.3
±7.5
22
56
V
V
mA
dB
Min
Max
Max
Min
55
dB
Min
See notes at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
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CODE IDENT NO.
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6
TABLE I. Electrical performance characteristics.- Continued. 1/
Test
Test condition
VS = ±5.0 V, G = +2
Rf = 1 kΩ, RL = 100 Ω
Single ended input
unless otherwise noted
Device type: All
Limits
Typ
Over temperature
25°C
25°C
Unit
Min/
Typ/
Max
Typ
-55°C to
+125°C
AC Performance
G = +1, Rf = 1.2 kΩ
1.3
GHz
G = +2, Rf = 715 Ω
725
MHz
G = +5, Rf = 576 Ω
540
G = +10, Rf = 464 Ω
480
Bandwidth for 0.1 dB flatness
G = +2, VO = 200 mVPP, Rf = 715 Ω
170
MHz
Large signal bandwidth
G = +2, VO = 2 VPP, Rf = 715 Ω
900
MHz
Slew rate
G = +2, VO = 5-V step,
Rf = 715 Ω, Rise/Fall
5200/
4000
V/µs
Rise and fall time
G = +2, VO = 4-V step,
Rf = 715 Ω, Rise/Fall
0.7/
0.9
ns
Setting time to 0.1%
G = -2, VO = 2-V step
20
Small signal bandwidth, -3 dB
(VO = 200 mVPP)
Setting time to 0.01%
60
Harmonic distortion
2
nd
harmonic
G = +5, f = 10 MHz,
VO = 2 VPP
rd
3 harmonic
RL = 100 Ω
-69
RL = 100 Ω
-75
dBc
Third order intermodulation distortion (IMD3)
G = +10, fc = 20 MHz,
∆f = 1 MHz, VO(envelope) = 2 VPP
-81
Noise figure
G = +10, , fc = 100 MHz, RF = 255 Ω
RG = 28
11
dB
Input voltage noise
f > 10 MHz
1.65
nV/ Hz
Input current noise (non inverting)
f > 10 MHz
13.4
pA/ Hz
Input current noise (inverting)
Differential gain
Differential phase
20
G = +2, RL = 150 Ω,
Rf = 768 Ω
NTSC
0.006%
PAL
0.004%
NTSC
0.03°
PAL
0.04°
See notes at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
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SIZE
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CODE IDENT NO.
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PAGE
7
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Test condition
VS = ±5.0 V, G = +2
Rf = 1 kΩ, RL = 100 Ω
Single ended input
unless otherwise noted
Device type: All
Limits
Over temperature
Typ
25°C
25°C
-55°C to
+125°C
Unit
Min/
Typ/
Max
kΩ
Min
DC performance
Open loop transimpedance gain
VO = ±2 V, RL = 1 kΩ
300
200
100
Input offset voltage
VCM = 0 V, RL = 1 kΩ
±0.7
±3
±5.5
mV
Max
±13
µV/°C
Typ
Average offset voltage drift
Input bias current (inverting)
±13
±65
Average bias current drift (-)
Input bias current (non inverting)
±14
±40
Average bias current drift (+)
Input
Common mode input range
Common mode rejection ratio
Inverting input impedance, Zin
Input resistance
±2.6
71
17.5
780
RL = 1 kΩ
VCM = ±2.5 V
Open loop, RL = 1 kΩ
Non inverting
±2.5
56
±90
µA
Max
±400
nA/°C
Typ
±60
µA
Max
±400
nA/°C
Typ
±2.5
50
V
dB
Min
Min
Typ
Ω
kΩ
Ω
pF
Inverting
11
Input capacitance
Output
Non inverting
1
Voltage output swing
RL = 1 kΩ
±3.65
±3.5
±3.4
V
Min
RL = 100 Ω
RL = 20 Ω
±3.45
115
100
0.01
±3.33
105
80
±3.2
90
75
V
mA
mA
Ω
Min
Min
Min
Typ
Current output, sourcing
Current output sinking
Closed loop output impedance
Power supply
Minimum operating voltage
Maximum operating voltage
Maximum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (-PSRR)
1/
G = +1, f = 1 MHz
VS+ = 4.5 V to 5.5 V, RL = 1 kΩ
14
69
±3.3
±7.5
16.8
60
VS- = -4.5 V to -5.5 V, RL = 1 kΩ
65
58
±3.3
±7.5
20.5
56
V
V
mA
dB
Min
Max
Max
Min
55
dB
Min
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not
necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
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Case X
Symbol
A
A1
A2
b
c
Notes:
1.
2.
3.
4.
Millimeters
Min
Max
1.75
0.10
0.25
0.25 BSC
0.31
0.51
0.13
0.25
Inches
Min
Max
.069
.004
.010
.010 BSC
.012
.020
.005
.010
Symbol
D
E
E1
e
L
Millimeters
Min
Max
4.80
5.00
3.80
4.00
5.80
6.20
1.27 BSC
0.40
1.27
Inches
Min
Max
.189
.197
.150
.157
.228
.244
.050 BSC
.016
.050
Controlling dimensions are millimeter, inch dimensions are given for reference only.
For dimension D, body length does not include mold flash, protrusion, or gate burrs. Mold flash, protrusion, or
gate burrs shall not exceed 0.006 inch (0.15 mm) each side.
For dimension E, body width does not include interlead flash. Interlead flash shall not exceed 0.017 inch (0.43 mm)
each side.
Falls within reference to JEDEC MS-012-AA.
FIGURE 1. Case outlines.
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Case Y
Symbol
A1
A2
b
c
D
Notes:
1.
2.
3.
4.
Millimeters
Min
Max
0.05
0.15
--1.10
0.25
0.38
0.13
0.23
2.90
3.10
Inches
Min
Max
.001
.005
--.043
.009
.014
.005
.009
.114
.122
Symbol
E
E1
e
L
---
Millimeters
Min
Max
2.90
3.10
4.75
5.05
0.65
BSC
0.40
0.70
-----
Inches
Min
Max
.114
.122
.187
.198
.025
BSC
.015
.027
-----
Controlling dimensions are millimeter, inch dimensions are given for reference only.
Body dimensions do not include mold flash or protrusion.
This package is designed to be soldered to a thermal pad on the board. Refer to technical brief, power pad thermally
enhanced package, manufacturer literature number SLMA002 for information regarding recommended board layout.
The vendor datasheet is available from the manufacturer.
Falls with JEDEC MO-187 variation AA-T.
FIGURE 1. Case outline - Continued.
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FIGURE 2. Terminal connections.
FIGURE 3. Wirebond life versus temperature.
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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item.
Vendor item drawing administrative
control number 1/
Device manufacturer
CAGE code
Vendor part number
Package
marking
V62/05609-01XE
2/
THS3201MDREP 3/

V62/05609-01YE
01295
THS3201MDGNREP 3/ 4/
BLM
1/
2/
3/
4/
The vendor item drawing establishes an administrative control number for identifying the item on
the engineering documentation.
Not yet available from a source of supplied.
The package is available taped and reel. The R suffix standard quality is 2500 (e.g.,
THS3201MDGNREP).
The manufacture has changed lead frames NiPdAu to NiPdAuAg and location of assembly from their
Hana facility to their Shanghai facility. Product with a Lot Trace Code of 1CxxxxH and earlier is a
NiPdAu frame from the Hana facility.
CAGE code
01295
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
Source of supply
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
SIZE
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CODE IDENT NO.
16236
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