REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA 13-07-01 4 A REV 5 6 7 8 9 10 11 12 13 14 15 16 17 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil/ TITLE MICROCIRCUIT, LINEAR, WIDEBAND, LOW DISTORTION, DIFFERENTIAL AMPLIFIER, MONOLITHIC SILICON APPROVED BY CHARLES F. SAFFLE SIZE AMSC N/A 3 CODE IDENT. NO. DWG NO. V62/13610 16236 PAGE 1 OF 17 5962-V048-13 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance wideband, low distortion, differential amplifier microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/13610 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 THS4500-EP Circuit function Wideband, low distortion, differential amplifier 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 8 JEDEC PUB 95 Package style MO-187-AA-T Plastic small outline with thermal pad 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 2 1.3 Absolute maximum ratings. 1/ Supply voltage range (VS) .......................................................................................... 16.5 V Input voltage (VIN) ...................................................................................................... ±VS Output current (IOUT) ................................................................................................. 150 mA 2/ Differential input voltage (VID) .................................................................................... 4 V Maximum junction temperature range (TJ) ................................................................. +150°C 3/ Storage temperature range (TSTG) ............................................................................ Lead temperature, 1.6 mm (1/16 inch) from case for 10 seconds .............................. Electrostatic discharge (ESD): Human body model (HBM) ..................................................................................... Charge device model (CDM) .................................................................................. Machine model (MM) ............................................................................................. -65°C to +150°C +300°C 4,000 V 1,000 V 100 V 1.4 Recommended operating conditions. 4/ Supply voltage (VS) : Dual supply ............................................................................................................ ±5 V nominal and ±7.5 V maximum Single supply .......................................................................................................... 5 V minimum and 15 V maximum Operating junction temperature range (TJ) ................................................................ -55°C to +125°C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ This device may incorporate a thermal pad on the underside of the chip. This acts as a heat sink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so, may result in exceeding the maximum junction temperature which could permanently damage the device. 3/ The absolute maximum temperature under any condition is limited by the constraints of the silicon process. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 3 1.5 Thermal characteristics. Thermal metric Symbol Case X Unit θJA 63.1 °C/W θJC(TOP) 46.2 °C/W Thermal resistance, junction-to-board 7/ θJB 33.9 °C/W Characterization parameter, junction-to-top 8/ ψJT 1.9 °C/W Characterization parameter, junction-to-board 9/ ψJB 33.6 °C/W Thermal resistance, junction-to-case (bottom) 10/ θJC(BOTTOM) 11.9 °C/W Thermal resistance, junction-to-ambient 5/ Thermal resistance, junction-to-case (top) 6/ 5/ The thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a JEDEC standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 6/ The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 7/ The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as described in JESD51-8. 8/ Characterization parameter, junction-to-top (ψJT ) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). 9/ Characterization parameter, junction-to-board (ψJB ) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). 10/ The thermal resistance, junction-to-case (bottom) is obtained by simulating a cold plate test on the exposed thermal pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 4 2. APPLICABLE DOCUMENTS AMERICAN NATIONAL STANDARDS INSTITUTE ANSI SEMI STANDARD G30-88 Packages Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http://www.ansi.org) JEDEC Solid State Technology Association EIA/JESD 51-2a EIA/JESD 51-7 EIA/JESD 51-8 JEDEC PUB 95 - Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air) High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages Integrated Circuits Thermal Test Method Environment Conditions – Junction-to-Board Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ VS = ±5 V unless otherwise specified Temperature, TJ Device type Limits Min Unit Max AC characteristics. Small signal bandwidth SSBW G = +1, PIN = -20 dBm, RF = 392 Ω +25°C 01 370 typical G = +2, PIN = -30 dBm, RF = 1 kΩ 175 typical G = +5, PIN = -30 dBm, RF = 2.4 kΩ 70 typical G = +10, PIN = -30 dBm, RF = 5.1 kΩ 30 typical MHz Gain bandwidth product GBWP G > +10 +25°C 01 300 typical MHz Bandwidth for 0.1 – dB flatness BW PIN = -20 dBm +25°C 01 150 typical MHz Large signal bandwidth LSBW VP = 2 V +25°C 01 220 typical MHz Slew rate SR 4 VPP step +25°C 01 2800 typical V/µs Rise time tr 2 VPP step +25°C 01 0.4 typical ns Fall time tf 2 VPP step +25°C 01 0.5 typical ns Settling time ts To 0.01%, VO = 4 VPP +25°C 01 8.3 typical ns 6.3 typical To 0.1%, VO = 4 VPP Harmonic distortion Second harmonic G = +1, VO = 2 VPP +25°C f = 8 MHz +25°C 01 f = 30 MHz Third harmonic -82 typical dBc -71 typical f = 8 MHz +25°C 01 f = 30 MHz -97 typical dBc -74 typical Third order intermodulation distortion RF = 392 Ω, 200 kHz tone spacing Third order output intercept point fC = 30 MHz, RF = 392 Ω, referenced to 50 Ω VO = 2 VPP, fC = 30 MHz, +25°C 01 -90 typical dBc +25°C 01 49 typical dBm See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 6 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ VS = ±5 V unless otherwise specified Temperature, TJ Device type Limits Min Unit Max AC characteristics – continued. f > 1 MHz Input voltage noise +25°C 01 7 typical nV / Hz f > 100 kHz Input current noise +25°C 01 1.7 typical pA / Hz Overdrive recovery time Overdrive = 5.5 V +25°C 01 60 typical ns DC performance characteristics. Open loop voltage gain AVOL -55°C to +125°C 01 49 dB Input offset voltage VIO -55°C to +125°C 01 -11 Average offset voltage drift ∆VIO -55°C to +125°C 01 Input bias current IIB -55°C to +125°C 01 Average bias current drift ∆IIB -55°C to +125°C 01 ±10 typical nA/ °C Input offset current IIO -55°C to +125°C 01 2 µA Average offset current drift ∆IIO -55°C to +125°C 01 ±40 typical nA/ °C Common mode input range VCMIR -55°C to +125°C 01 -5.1 Common mode rejection ratio CMRR -55°C to +125°C 01 70 Input impedance ZIN +25°C 01 10 ||1 typical 6 mV ±10 typical µV/ °C µA 6.6 Input characteristics 3/ 2 V dB 7 Ω||pF See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 7 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ VS = ±5 V unless otherwise specified Temperature, TJ Device type Limits Min Unit Max Output characteristics. Differential output voltage swing VOD RL = 1 kΩ -55°C to +125°C 01 ±7.25 V Differential output current drive IOD RL = 20 Ω -55°C to +125°C 01 90 mA Output balance error PIN = -20 dBm, f = 100 kHz +25°C 01 -58 typical dB Closed loop output impedance (single ended) f = 1 MHz +25°C 01 0.1 typical Ω Output common mode voltage control characteristics. Small signal bandwidth SSBW RL = 400 Ω +25°C 01 180 typical MHz Slew rate SR 2 VPP step +25°C 01 92 typical V/µs Minimum gain -55°C to +125°C 01 Maximum gain -55°C to +125°C 01 -55°C to +125°C 01 -55°C to +125°C 01 -55°C to +125°C 01 +25°C 01 Common mode offset voltage VOCM Input bias current IIB Input voltage range VINR Input impedance ZIN VOCM = 2.5 V 3/ 0.98 -7.6 V/V 1.08 V/V 15 mV 170 µA ±3.4 V 25||1 typical kΩ||pF Maximum default voltage VOCM left floating -55°C to +125°C 01 0.10 V Minimum default voltage VOCM left floating -55°C to +125°C 01 Specified operating voltage -55°C to +125°C 01 7.5 V Maximum quiescent current -55°C to +125°C 01 40 mA Minimum quiescent current -55°C to +125°C 01 11 mA -55°C to +125°C 01 70 dB -0.10 V Power supply characteristics. Power supply rejection ±PSRR See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 8 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ VS = ±5 V unless otherwise specified Temperature, TJ Device type Limits Min Unit Max Power down characteristics. Enable voltage threshold Device enabled ON above – 2.9 V -55°C to +125°C 01 Disable voltage threshold Device disabled OFF below – 4.3 V -55°C to +125°C 01 -4.3 V -55°C to +125°C 01 1400 µA -55°C to +125°C 01 260 µA +25°C 01 50||1 typical kΩ||pF Power down quiescent current -2.9 V Input bias current IIB Input impedance ZIN Turn on time delay ton +25°C 01 1000 typical ns Turn off time delay toff +25°C 01 800 typical ns 3/ See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 9 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ VS = 5 V unless otherwise specified Temperature, TJ Device type Limits Min Unit Max AC characteristics. Small signal bandwidth SSBW G = +1, PIN = -20 dBm, RF = 392 Ω +25°C 01 320 typical G = +2, PIN = -30 dBm, RF = 1 kΩ 160 typical G = +5, PIN = -30 dBm, RF = 2.4 kΩ 60 typical G = +10, PIN = -30 dBm, RF = 5.1 kΩ 30 typical MHz Gain bandwidth product GBWP G > +10 +25°C 01 300 typical MHz Bandwidth for 0.1 – dB flatness BW PIN = -20 dBm +25°C 01 180 typical MHz Large signal bandwidth LSBW VP = 1 V +25°C 01 200 typical MHz Slew rate SR 2 VPP step +25°C 01 1300 typical V/µs Rise time tr 2 VPP step +25°C 01 0.5 typical ns Fall time tf 2 VPP step +25°C 01 0.6 typical ns Settling time ts To 0.01%, VO = 2 VPP +25°C 01 13.1 typical ns 8.3 typical To 0.1%, VO = 2 VPP Harmonic distortion Second harmonic G = +1, VO = 2 VPP f = 8 MHz +25°C 01 f = 30 MHz Third harmonic -80 typical dBc -55 typical f = 8 MHz +25°C 01 f = 30 MHz -76 typical dBc -60 typical See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 10 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ VS = 5 V unless otherwise specified Temperature, TJ Device type Limits Min Unit Max AC characteristics – continued. f > 1 MHz Input voltage noise +25°C 01 7 typical nV / Hz f > 100 kHz Input current noise +25°C 01 1.7 typical pA / Hz Overdrive recovery time Overdrive = 5.5 V +25°C 01 60 typical ns DC performance characteristics. Open loop voltage gain AVOL -55°C to +125°C 01 48 Input offset voltage VIO -55°C to +125°C 01 -11 Average offset voltage drift ∆VIO -55°C to +125°C Input bias current IIB Average bias current drift dB 6 mV 01 ±10 typical µV/ °C -55°C to +125°C 01 8 µA ∆IIB -55°C to +125°C 01 ±10 typical nA/ °C Input offset current IIO -55°C to +125°C 01 2 µA Average offset current drift ∆IIO -55°C to +125°C 01 ±20 typical nA/ °C Common mode input range VCMIR -55°C to +125°C 01 -0.1 Common mode rejection ratio CMRR -55°C to +125°C 01 65 Input impedance ZIN +25°C 01 10 ||1 typical Input characteristics. 3/ 2 V dB 7 Ω||pF See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 11 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ VS = 5 V unless otherwise specified Temperature, TJ Device type Limits Min Unit Max Output characteristics. Differential output voltage swing VOD RL = 1 kΩ, referenced to 2.5 V -55°C to +125°C 01 ±2.7 V Output current drive IOD RL = 20 Ω -55°C to +125°C 01 80 mA Output balance error PIN = -20 dBm, f = 100 kHz +25°C 01 -58 typical dB Closed loop output impedance (single ended) f = 1 MHz +25°C 01 0.1 typical Ω Output common mode voltage control characteristics. Small signal bandwidth SSBW RL = 400 Ω +25°C 01 180 typical MHz Slew rate SR 2 VPP step +25°C 01 80 typical V/µs Minimum gain -55°C to +125°C 01 Maximum gain -55°C to +125°C 01 -55°C to +125°C 01 -55°C to +125°C 01 -55°C to +125°C 01 1.3 +25°C 01 25||1 typical Common mode offset voltage VOCM Input bias current IIB Input voltage range VINR Input impedance ZIN VOCM = 2.5 V 3/ 0.92 -5.6 V/V 1.17 V/V 35 mV 3 µA 3.7 V 2.75 kΩ||pF Maximum default voltage VOCM left floating -55°C to +125°C 01 Minimum default voltage VOCM left floating -55°C to +125°C 01 Specified operating voltage -55°C to +125°C 01 15 V Maximum quiescent current -55°C to +125°C 01 38 mA Minimum quiescent current -55°C to +125°C 01 10 mA -55°C to +125°C 01 66 dB 2.25 V V Power supply characteristics. Power supply rejection ±PSRR See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 12 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ VS = 5 V unless otherwise specified Temperature, TJ Device type Limits Min Unit Max Power down characteristics. Enable voltage threshold Device enabled ON above – 2.1 V -55°C to +125°C 01 2.1 typical V Disable voltage threshold Device disabled OFF below – 0.7 V -55°C to +125°C 01 0.7 typical V -55°C to +125°C 01 1400 µA -55°C to +125°C 01 140 µA +25°C 01 50||1 typical kΩ||pF Power down quiescent current Input bias current IIB Input impedance ZIN Turn on time delay ton +25°C 01 1000 typical ns Turn off time delay toff +25°C 01 800 typical ns 3/ 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, fixed resistance (RF) = gain resistance (RG) = 392 Ω, load resistance (RL) = 800 Ω, G = +1, and single ended input. 3/ The || symbolizes that the input impedance is being represented as the resistance value is in parallel with the capacitance. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 13 Case X FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 14 Case X Dimensions Inches Symbol Millimeters Min Max Min Max A --- 0.043 --- 1.10 A1 0.001 0.005 0.05 0.15 b 0.009 0.014 0.25 0.38 c 0.005 0.009 0.13 0.23 D 0.114 0.122 2.90 3.10 e 0.025 BSC 0.65 BSC E 0.114 0.122 2.90 3.10 E1 0.187 0.198 4.75 5.05 L 0.015 0.027 0.40 0.70 L1 0.009 BSC 0.25 BSC NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. Body dimension do not include mold flash or protrusion. 3. This package is designed to be soldered to a thermal pad on the board. Refer to technical brief, power pad thermally enhanced package information from the manufacturer. 4. See the additional figure in the product data sheet for details regarding the exposed thermal pad features and dimensions. 5. Falls within reference to JEDEC MO-187-AA-T. FIGURE 1. Case outline - Continued. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 15 Device type 01 Case outline X Terminal number Terminal symbol 1 -VIN 2 VOCM 3 +VS 4 +VOUT 5 -VOUT 6 -VS 7 PD 8 +VIN FIGURE 2. Terminal connections. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 16 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ 2/ Device manufacturer CAGE code Topside marking Transportation and quantity Vendor part number V62/13610-01XE 01295 SJE Reel of 2500 THS4500MDGNREP Tube of 80 THS4500MDGNEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ For the most current package and ordering information, see the package option addendum at the end of the manufacturer’s data sheet. CAGE code 01295 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/13610 PAGE 17