Cypress Semiconductor Product Qualification Report QTP# 082609 VERSION 1.0 June 2009 HX2LP Device Family C8Q-3R Technology, Fab 5 CY7C656205 CY7C656305 USB High-Speed Hub CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Fredrick Whitwer Principal Reliability Engineer (408) 943-2722 Mira Ben-Tzur Quality Engineering Director (408) 943-2675 Cypress Semiconductor HX2LP Device Family, C8Q-3R Technology, Fab5 Device: CY7C656205/CY7C656305 082609 V. 1.0 Page 2 of 9 June 2009 PRODUCT QUALIFICATION HISTORY QUAL REPORT DESCRIPTION OF QUALIFICATION PURPOSE DATE COMP. 065201 Qualify FX2LP18 Device Family on C8Q-3R Technology at GSMC Foundry (Fab 5) Sep 07 082609 Qualify HX2LP (7C65630C, USB High Speed HUB) at GSMC on C8Q-3R Jun 09 Cypress products are manufactured using qualified processes. The technology qualification for this product is referenced above and must be considered to get a complete and thorough evaluation of the reliability of the product. Cypress Semiconductor HX2LP Device Family, C8Q-3R Technology, Fab5 Device: CY7C656205/CY7C656305 082609 V. 1.0 Page 3 of 9 June 2009 PRODUCT DESCRIPTION (for qualification) Qualification Purpose: Qualify HX2LP (7C65630C, USB High Speed HUB) at GSMC on C8Q-3R Marketing Part #: CY7C656205, CY7C656305 Device Description: 3.3V 24Mhz High-Speed USB 2.0 Hub Cypress Division: Cypress Semiconductor Corporation – Consumer and Computation Division TECHNOLOGY/FAB PROCESS DESCRIPTION Number of Metal Layers: Metal Composition: Metal 1: 100A Ti/3,200A Al 0.5% Cu/300A TiW 4 Metal 2: 150A Ti/4,230A Al 0.5% Cu/300A TiW Metal 3: 150A Ti/4,230 Al 0.5% Cu/300A TiW Metal 4: 150A Ti/8,000 Al 0.5% Cu/300A TiW 1000Å TEOS / 9000Å Si3N4 Passivation Type and Materials: Generic Process Technology/Design Rule (µ-drawn): CMOS, 0.13µm Gate Oxide Material/Thickness (MOS): SiO2 /55A Name/Location of Die Fab (prime) Facility: GSMC China Die Fab Line ID/Wafer Process ID: Fab5, C8Q-3R PACKAGE AVAILABILITY PACKAGE 56-QFN ASSEMBLY FACILITY SITE CML-RA, L-Korea, AE-Shanghai Note: Package Qualification details available upon request. Cypress Semiconductor HX2LP Device Family, C8Q-3R Technology, Fab5 Device: CY7C656205/CY7C656305 082609 V. 1.0 Page 4 of 9 June 2009 MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: Mold Compound Flammability Rating: Mold Compound Alpha Emission Rate: LY56 56-Lead QFN Sumitomo EME-G700 V-O per UL94 N/A Oxygen Rating Index: N/A Lead Frame Material: Copper Lead Finish, Composition / Thickness: Matte Sn Die Backside Preparation Method/Metallization: Backgrind Die Separation Method: Punch Die Attach Supplier: Ablestik Die Attach Material: Ablebond 8290 Die Attach Method: Epoxy Bond Diagram Designation: 10-06541, 10-06493 Wire Bond Method: Thermosonic Wire Material/Size: Au, 1.0mil Thermal Resistance Theta JA °C/W: 101 °C/W Package Cross Section Yes/No: No Assembly Process Flow: 001-09888 Name/Location of Assembly (prime) facility: SEOUL-KOREA (L) MSL Level 3 Reflow Profile 260C ELECTRICAL TEST / FINISH DESCRIPTION Test Location: CML-R Cypress Semiconductor HX2LP Device Family, C8Q-3R Technology, Fab5 Device: CY7C656205/CY7C656305 082609 V. 1.0 Page 5 of 9 June 2009 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENT Stress/Test Test Condition (Temp/Bias) Result P/F Electrostatic Discharge Human Body Model (HBM) 2200V JESD22, Method A114-E P Electrostatic Discharge Charge Device Model (CDM) 500V Cypress Spec. 25-00020 P High Accelerated Saturation Test (HAST) 130°C, 3.65V, 85%RH Precondition: JESD22 Moisture Sensitivity Level 3 P 192 Hrs, 30C/60%RH+3IR-Reflow, 260°C+0, -5°C High Temperature Operating Life Early Failure Rate High Temperature Operating Life P Dynamic Operating Condition, Vcc=3.8V, 150°C Dynamic Operating Condition, Vcc=3.8V, 150°C P High Temperature Steady State life Static Operating Condition, Vcc= 3.63V, 150°C P High Temperature Storage 150C, no bias P Low Temperature Operating Life Dynamic Operating Condition, Vcc=4.3V, -30°C P Pressure Cooker 121°C, 100%RH, 15 Psig Precondition: JESD22 Moisture Sensitivity Level 3 P Latent Failure Rate 192 Hrs, 30C/60%RH+3IR-Reflow, 260°C+0, -5°C Static Latchup 125C, 5.1V, ± 200mA Cypress Spec. 01-00081 P Temperature Cycle MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C Precondition: JESD22 Moisture Sensitivity Level 3 P 192 Hrs, 30C/60%RH+3IR-Reflow, 260°C+0, -5°C Acoustic Microscopy Cypress Spec. 25-00104 P Cypress Semiconductor HX2LP Device Family, C8Q-3R Technology, Fab5 Device: CY7C656205/CY7C656305 082609 V. 1.0 Page 6 of 9 June 2009 RELIABILITY FAILURE RATE SUMMARY Device Tested/ Device Hours # Fails Activation Energy Thermal3 A.F Failure Rate High Temperature Operating Life Early Failure Rate1 3,000 Devices 0 N/A N/A 0 PPM High Temperature Operating Life1,2 Long Term Failure Rate 362,000 DHRs 0 0 .7 170 15 FIT Stress/Test 1 2 3 Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C. Chi-squared 60% estimations used to calculate the failure rate. Thermal Acceleration Factor is calculated from the Arrhenius equation ⎡E ⎡ 1 1 ⎤ ⎤ AF = exp ⎢ A ⎢ - ⎥ ⎥ ⎣ k ⎣ T 2 T1 ⎦ ⎦ where: EA =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions. Cypress Semiconductor HX2LP Device Family, C8Q-3R Technology, Fab5 Device: CY7C656205/CY7C656305 082609 V. 1.0 Page 7 of 9 June 2009 Reliability Test Data QTP #: Device Fab Lot # 065201 Assy Lot # Assy Loc Duration Samp Rej CY7C68053 (7C680510BK) 9714792 610721014 TAIWN-G COMP 15 0 CY7C68053 (7C680510BK) 4720785 610729797 TAIWN-G COMP 15 0 610739937 TAIWN-G COMP 15 0 STRESS: ACOUSTIC-MSL3 CY7C68053 (7C680510BK) 4727325 STRESS: ESD-CHARGE DEVICE MODEL (500V) CY7C68053 (7C680510BK) 9714792 610721014 TAIWN-G COMP 9 0 CY7C68053 (7C680510BK) 4720785 610729797 TAIWN-G COMP 9 0 STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-E, 2200V CY7C68053 (7C680510BK) 9714792 610721014 TAIWN-G COMP 8 0 CY7C68053 (7C680510BK) 4720785 610729797 TAIWN-G COMP 8 0 STRESS: HIGH TEMP STEADY STATE LIFE TEST (150C, 3.63V) CY7C68053 (7C680510BK) 9714792 610721250 CML-R 80 80 0 CY7C68053 (7C680510BK) 9714792 610721250 CML-R 168 80 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE (150C, 3.8V, Vcc Max) CY7C68053 (7C680510BK) 9714792 610721250 CML-R 48 338 0 CY7C68053 (7C680510BK) 4720785 610731288 CML-R 48 348 0 CY7C68053 (7C680510BK) 4727325 610739215 CML-R 48 340 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE (150C, 3.8V, Vcc Max) CY7C68053 (7C680510BK) 9714792 610721250 CML-R 80 182 0 CY7C68053 (7C680510BK) 9714792 610721250 CML-R 500 182 0 CY7C68053 (7C680510BK) 4720785 610731288 CML-R 80 182 0 CY7C68053 (7C680510BK) 4720785 610731288 CML-R 500 182 0 CY7C68053 (7C680510BK) 4727325 610739215 CML-R 80 180 0 CY7C68053 (7C680510BK) 4727325 610739215 CML-R 500 180 0 Failure Mechanism Cypress Semiconductor HX2LP Device Family, C8Q-3R Technology, Fab5 Device: CY7C656205/CY7C656305 082609 V. 1.0 Page 8 of 9 June 2009 Reliability Test Data QTP #: 065201 Device Fab Lot # Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism STRESS: HI-ACCEL SATURATION TEST (130C, 85%RH, 3.65V), PRE COND 192 HR, 30C/60%RH, MSL3 CY7C68053 (7C680510BK) 9714792 610721250 CML-R 128 50 0 CY7C68053 (7C680510BK) 4720785 610731288 CML-R 128 45 0 500 45 0 STRESS: LOW TEMPERATURE OPERATING LIFE (-30C, 4.3V) CY7C68053 (7C680510BK) 9714792 610721250 CML-R STRESS: STATIC LATCH-UP TESTING (125C, ±200mA) CY7C68053 (7C680510BK) 9714792 610721014 TAIWN-G COMP 3 0 CY7C68053 (7C680510BK) 4720785 610729797 TAIWN-G COMP 6 0 STRESS: HIGH TEMPERATURE STORAGE, 150C, no bias CY7C68053 (7C680510BK) 9714792 610721250 CML-R 500 50 0 CY7C68053 (7C680510BK) 9714792 610721250 CML-R 1000 50 0 STRESS: PRESSURE COOKER TEST (121C, 100%RH), 15 Psig, PRE COND 192 HR, 30C/60%RH, MSL3 CY7C68053 (7C680510BK) 9714792 610721014 TAIWN-G 168 48 0 CY7C68053 (7C680510BK) 4720785 610729797 TAIWN-G 168 50 0 STRESS: TC COND. C -65C TO 150C, PRE COND 192 HRS, 30C/60%RH, MSL3 CY7C68053 (7C680510BK) 9714792 610721014 TAIWN-G 300 50 0 CY7C68053 (7C680510BK) 9714792 610721014 TAIWN-G 1000 50 0 CY7C68053 (7C680510BK) 4720785 610729797 TAIWN-G 500 50 0 CY7C68053 (7C680510BK) 4720785 610729797 TAIWN-G 1000 50 0 CY7C68053 (7C680510BK) 4727325 610739937 TAIWN-G 300 50 0 Cypress Semiconductor HX2LP Device Family, C8Q-3R Technology, Fab5 Device: CY7C656205/CY7C656305 082609 V. 1.0 Page 9 of 9 June 2009 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 082609 Assy Loc Duration Samp Rej STRESS: ESD-CHARGE DEVICE MODEL, 500V CY7C656305 (7C656305DK) 4838922 610849515 SEOUL-L COMP 9 0 8 0 STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-E, 2200V CY7C656305 (7C656305DK) 4838922 610849515 SEOUL-L COMP STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE (150C, 3.8V, Vcc Max) CY7C656305 (7C656305DK) 4838922 610849515 SEOUL-L 48 1000 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE (125C, 3.8V, Vcc Max) CY7C656305 (7C656305DK) 4838922 610849516 SEOUL-L 96 1000 0 CY7C656305 (7C656305DK) 4838922 610849514 SEOUL-L 96 1000 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE (150C, 3.8V, Vcc Max) CY7C656305 (7C656305DK) 4838922 610849515 SEOUL-L 80 180 0 CY7C656305 (7C656305DK) 4838922 610849515 SEOUL-L 500 180 0 COMP 6 0 STRESS: STATIC LATCH-UP TESTING (125C, 5.1V, ±200mA) CY7C656305 (7C656305DK) 4838922 610849515 SEOUL-L Failure Mechanism