4 JP1 VCC_D VREG VCC I2C_SDA OVR#[1] OVR#[2] GANG SELFPWR VCC_D nOVRP3 nOVRP4 TEST RESET# DP4 DM4 EC1 10uF C8 0.1uF C3 0.1uF C4 1uF C5 1uF C6 0.1uF EC1 close to Pin 28 USB Upstream Ports RREF VBUS XOUT XIN R14 680R FB LB2 PWR1 R1 10K USB Downstream Ports 1 2 C12 20P 12MHz C C13 1uF PWR1 100K 100K 10K VCC_5V VCC_5V PORT 1 VBUS_T DM_T DP_T GND_T A1 A2 A3 A4 DM1 DP1 PORT 2 VBUS_B DM_B DP_B GND_B B1 B2 B3 B4 DM2 DP2 R16 47K VCC_5V Close to CY7C65632 10K nENP1 nOVRP1 nOVRP2 nENP1 U3 1 2 3 4 8 7 6 5 CTLA OUTA FLGA IN FLGB GND CTLB OUTB S1 S2 C19 0.1u F1 F2 6V500mA 6V500mA VCC_5V_REG PWR1 PWR2 R19 30K PWR3 R9 R10 R11 2 10K 100K 100K Vout 1 2 3 4 8 7 6 5 CTLA OUTA FLGA IN FLGB GND CTLB OUTB C9 R21 30K R20 30K C18 0.1u 4 1uF TAB GND 1 R22 30K PORT 3 VBUS_T DM_T DP_T GND_T A1 A2 A3 A4 DM3 DP3 PORT 4 VBUS_B DM_B DP_B GND_B B1 B2 B3 B4 DM4 DP4 SW1 S1 S2 VCC_5V_IN VCC_5V PWR4 VCC_5V_REG PWR3 S1 S2 S3 S4 PWR4 VCC_D USB A RA STACKED J5 I2C_EEPROM_PWR F4 6V500mA 6V500mA LED2 PWR3 2 3 1 S_VCC Q1 FDN338P + C20 0.1uF G EC2 4.3uF R12 4.7K nOVRP3 LED5 A C GREEN_LED1 R25 30K A GREEN_LED4 LED3 nOVRP4 A 1 2 3 4 R24 30K VCC WP SCL SDA C7 0.1uF 8 7 6 5 R2 10K TEST nENP1 LED4 C GREEN_LED2 R26 30K VBUS A Note: U2 should be place on socket C GREEN_LED3 A CYPRESS SEMICONDUCTOR © 2011 Title R18 470R TEST R17 470R nENP1 HX2VL QFN28 USB2.0 4-PORT DVK Size B Date: 5 A0 A1 A2 GND 1 2 SELF_PWR D SELF_PWR S S_VCC C PWR4 R23 30K R13 510K U2 24LC02B/P GANG VCC_5V A 1 2 DPDT F3 B EC6 120uF S3 S4 VCC_3.3 NOTE: 5V Adapter input + C17 0.1uF VCC_5V POWER CIRCUIT + EC5 120uF FB LB5 VCC_3.3_IN J1 DC JACK EC4 120uF C16 0.1uF J3 AME8805-SOT89 5V to 3.3V AIC1526-0 VCC_5V 4 C S3 S4 USB Downstream Ports C10 1uF 10K nENP1 nOVRP3 nOVRP4 nENP1 PWR2 + C15 0.1uF FB LB4 VCC_3.3 3 nOVRP2 U4 B Vin VCC_5V nOVRP1 FB LB3 USB A RA STACKED AIC1526-0 R8 S3 S4 EC3 120uF U5 VCC_D PWR2 S1 S2 + C14 0.1uF J2 R3 C11 20P R7 3 DP0 DLP11S Close to CY7C65632 650R 1% R15 100K CY7C65632-QFN28 VCC_D R6 2 DM0 4 D LED1 RESET# R5 T1 1 USBB-A X1 R4 DM0_C DP0_C G2 HAND2 GANG GND RREF VCC_A2 XIN XOUT DM3 DP3 VCC_A3 C2 0.1uF 1 2 3 4 VCC DD+ GND Individual Mode A 21 20 19 18 17 16 15 C1 0.1uF FB LB1 G1 HAND1 RED BUS_LED P 8 9 10 11 12 13 14 QFN28 LB7 FB VCC_D OVR#[3] OVR#[4] TEST RESET# DD+4 DD-4 VBUS VCC_A3 VCC_3.3_IN C DD-0 DD+0 DD-1 CY7C65632 DD+1 VCC_A_5 DD-2 DD+2 VCC_A LB6 FB P 1 2 3 4 5 6 7 1 J4 + RREF VCC_A_9 XIN XOUT DD-3 DD+3 VCC_A_14 DM0 DP0 DM1 DP1 VCC_A1 DM2 DP2 VCC_A 2 VCC_5V 4 VBUS 6 GND VCC_A3 2 4 6 VCC_A2 1 3 5 Header 3x2 D 2 VCC_A2 VCC_D 1 TEST 3 GANG 5 28 27 26 25 24 23 22 U1 3 VCC_A1 VCC_3.3_IN VCC_5V_IN nENP1 nOVRP1 nOVRP2 GANG SELF_PWR 5 3 2 Document Number <Doc> Thursday, September 29, 2011 Rev ** Sheet 1 1 of 1