4 3 VCC_3.3_IN VCC_5V_IN AMBER1 GREEN1_IN VCC_D4 nENP1 nOVRP1 nENP2 nOVRP2 GANG VCC_D3 SELF_PWR 5 EC1 10uF C5 1uF C6 0.1uF C7 1uF C8 0.1uF C9 0.1uF C10 0.1uF C11 0.1uF FB LB1 G1 HAND1 VCC_D4 VCC_D3 VCC_D2 VCC_D1 VCC_A5 VCC_A4 VCC_A4 VCC_A3 C4 0.1uF J4 1 2 3 4 VCC DD+ GND C12 0.1uF DM0_C DP0_C EC1 close to VREG USB Upstream Ports PWR1 USB Downstream Ports R2 RESET# 100K C13 1uF X1 R3 GANG PORT 1 C14 20P 1 2 12MHz R16 47K PORT 2 C15 20P S1 S2 VCC_D VCC_D VBUS_T DM_T DP_T GND_T A1 A2 A3 A4 DM1_C DP1_C VBUS_B DM_B DP_B GND_B B1 B2 B3 B4 DM2_C DP2_C S1 S2 S3 S4 DLP11S AIC1526-0 VCC_D PWR2 B J8 FIXED_PORT2 1 1 GREEN2_IN 2 2 3 3 J9 FIXED_PORT3 1 1 GREEN3_IN 2 2 3 3 FB LB3 PWR2 T3 S3 S4 1 2 DM2 4 3 DP2 + C20 0.1uF EC4 120uF C DLP11S FB LB4 PWR3 J10 FIXED_PORT4 1 1 GREEN4_IN 2 2 3 3 PORT 4 S1 S2 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 YELLOW GREEN YELLOW GREEN YELLOW GREEN YELLOW GREEN VBUS_T DM_T DP_T GND_T A1 A2 A3 A4 DM3_C DP3_C VBUS_B DM_B DP_B GND_B B1 B2 B3 B4 DM4_C DP4_C S1 S2 S3 S4 2 DM3 1 + C21 0.1uF T4 J3 PORT 3 A GREEN4 C17 0.1u J7 FIXED_PORT1 1 1 GREEN1_IN 2 2 3 3 A AMBER4 CTLA OUTA FLGA IN FLGB GND CTLB OUTB 8 7 6 5 3 DP1 4 USB Downstream Ports R15 10K A GREEN3 U3 1 2 3 4 A GREEN2 10K A AMBER2 100K EC3 120uF USB A RA STACKED VCC_D R14 10K R5 10K A GREEN1 100K nENP1 nOVRP1 nOVRP2 nENP2 A AMBER1 10K R4 10K A AMBER3 PWR1 VCC_5V 2 DM1 1 + C19 0.1uF T2 J2 XOUT XIN R1 10K R24 D DLP11S Close to CY7C65632 VCC_D R23 3 DP0 G2 FB LB2 VCC_D R22 2 DM0 4 HAND2 Close to CY7C65632 R21 T1 1 USBB-A AMBER2 GREEN2_IN VCC_D2 AMBER3 GREEN3_IN nENP3 nOVRP3 nENP4 nOVRP4 TEST RESET# VBUS VCC_D1 CY7C65632-TQFP48 C3 0.1uF RREF 36 35 34 33 32 31 30 29 28 27 26 25 C2 0.1uF 650R 1% AMBER#[2] GREEN#[2] VCC_D AMBER#[3] GREEN#[3] PWR#[3] OVR#[3] PWR#[4] OVR#[4] TEST RESET# SEL48 CY7C65632 TQFP48 C1 0.1uF VCC_A3 48 47 46 45 44 43 42 41 40 39 38 37 C + VREG VCC AMBER#[1] GREEN#[1] SEL27 PWR#[1]/I2C_SDA OVR#[1] PWR#[2] OVR#[2] GANG VCC_D SELFPWR VCC_A_1 GND_2 DD-0 DD+0 DD-1 DD+1 VCC_A_7 GND_8 DD-2 DD+2 RREF VCC_A_12 GND 13 XIN 14 XOUT 15 VCC_A4 16 DM3 17 DP3 18 VCC_A5 19 GND 20 DM4 21 DP4 22 GREEN4_IN 23 AMBER4 24 VCC_A1 1 GND 2 DM0 3 DP0 4 DM1 5 DP1 6 VCC_A2 7 GND 8 DM2 9 DP2 10 RREF 11 VCC_A3 12 VCC_D VCC_A2 VCC_A VCC_A1 VCC_A VCC_3.3 GND_13 XIN XOUT VCC_A_16 DD-3 DD+3 VCC_A_19 GND_20 DD-4 DD+4 GREEN#[4] AMBER#[4] D 1 VBUS VCC_D LB6 FB U1 2 EC5 120uF 3 DP3 4 DLP11S FB LB5 PWR4 T5 S3 S4 1 2 DM4 4 3 DP4 + C22 0.1uF EC6 120uF DLP11S B USB A RA STACKED PWR3 VCC_5V CTLA OUTA FLGA IN FLGB GND CTLB OUTB 8 7 6 5 C18 0.1u PORT1 AIC1526-0 PORT3 PORT4 R8 R9 R10 680R 680R 680R 680R GND PWR4 VCC_D U5 VCC_5V 2 S_VCC Vin Vout 3 GND 1 2 3 1 C24 Q1 FDN338P A + G EC2 4.3uF VBUS R12 4.7K TAB J6 1 2 1 2 C23 1uF 1 2 1 2 3 4 VCC WP SCL SDA 8 7 6 5 1 VCC_5V_REG 3 R6 680R VCC_3.3 TEST nENP1 2 VCC_5V 5 VCC_3.3_IN 4 6 A DPDT U2 C25 0.1uF A0 A1 A2 GND 1 2 SW1 VCC_5V_IN SPI_EEPROM_PWR I2C_EEPROM_PWR U6 SELF_PWR VCC_D J5 VCC_3.3 AME8805-SOT89 5V to 3.3V D C16 0.1uF S S_VCC 1uF R11 510K 4 2VCC_5V 4 VBUS 6 TEST 8 GND LED1 RED BUS_LED VCC_5V_REG 2 4 6 8 HEADER1 POWER CIRCUIT NOTE: 5V Adapter input SELF_PWR NOTE: When SPI EEPROM is used J9 and J10 should be in position 2-3. C J1 DC JACK PORT2 R7 1 3 5 7 A 1 2 3 4 GANG U4 nENP3 nOVRP3 nOVRP4 nENP4 VCC_D 1 AMBER3 3 AMBER4 5 GANG 7 C C C JP1 C 10K C R20 100K C R19 100K C R18 10K C R17 R13 10K AMBER1 GREEN1 AMBER2 GREEN2 1 2 3 4 CS SK DI DO VCC NC2 NC1 GND 8 7 6 5 AT93C46E-PU 24LC02B/P CYPRESS SEMICONDUCTOR © 2011 Title HX2VL TQFP48 USB2.0 4-PORT DVK Size B Document Number <Doc> Rev ** Note: U2 and U6 should be placed on sockets Date: 5 4 3 2 Monday, August 29, 2011 Sheet 1 1 of 1