RTC6711 Preliminary Data Sheet Dec 2005 Rev. Date From Description V.002 V.003 10/3/2005 10/31/2005 R2200 R2200 V.004 12/1/2005 R2200 Original Modify the following items: 1. Add pin 1 PD_REG18 description; 1 for power down and 0 for power on 2. Modify switch mode to Easy channel selection mode 3. Add Absolute Maximum Ratings 4. Add S3=0 into Channel selection table 5. Modify Data slicer bit rate 4Mpbs in typical case 1.Add SPI timing diagram 2.Add mini audio SNR 45dB in electrical specification 3.Add mini video SNR 45dB in electrical specification Applicant: R2200 Document Title: Data Sheet of RTC6711 Approvals: R2000: S.C. Wong R2500: C.J. Chao R2100: J.Y. Tsai Marketing: Jack Chang Contents: 8 Attach: 0 Total Page: 9 File Format: Word R2200: W.K. Deng R2300: T.S. Liou Document No.: RTC6711-DST-004 ☆ Signature on file in DC ☆ www.richwave.com.tw Specifications subject to change without notice Rev V.004 Preliminary Confidential Proprietary 1 RTC6711 Preliminary Data Sheet Dec 2005 RTC6711 CMOS 2.4GHz FM/FSK Receiver Product Description The RTC6711 is a highly integrated FM/FSK receiver intended for application on 2.4GHz band analog FM or digital FSK demodulation. The chip includes a low noise amplifier, mixer, IF amplifier, FM demodulator, AGC, and FSK data slicer. With RSSI voltage output the instantaneous radio signal strength can be monitoring as input for the followed indicator process. RX Carrier frequency can be set by SPI programming, or by selecting among 4 fixed channels using three dedicated pins. The device is available in a 48-pin QFN package. Features 3.3V/2.5V Power Supply 2.4GHz ISM bands FM demodulator High sensitivity FM/FSK Receiver Operation Simple three digital pins setting 4 fixed channels to eliminate external micro-controller FM and FSK dual output formats Radio Strength Indicator (RSSI) CMOS technology On-chip VCO and PLL Receiver frequency setting by SPI programming 48-pin Leadless QFN package Application AV Sender FSK transmitter Baby Monitor Wireless Camera Wireless Audio Wireless Earphone www.richwave.com.tw Specifications subject to change without notice Rev V.004 Preliminary Confidential Proprietary 2 RTC6711 Preliminary Data Sheet Dec 2005 Pin Descriptions PIN NAME I/O 1 PD_REG18 Digital In 2 3 7 LNAVDD RFIN2 CS2 SPIDATA CS1 SPILE CS0 SPICLK SPI_SE Supply In Analog In Digital In Digital In Digital In Digital In Digital In Digital In Digital In 8 BX Digital In 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD33D VSS_SYN3 VSS_SYN4 XTAL1 XTAL2 LOCK_DT CP VDDSYN S2 VT2G VCO2GVDD VDD2D5 REG1D8 BCR IFINP IFINN AGC_C BBVDD0 FSKCOMIN VAMP_REF BBOUT2 VAMPIN VAMPVDD VAMPOUT Supply In Digital Ground Digital Ground Analog In Analog In Digital Out Analog Out Supply In Digital In Analog In Supply In Supply In Analog Out Analog I/O Analog In Analog In Analog I/O Supply In Analog IN Analog I/O Analog Out Analog In Supply In Analog Out 33 THD_C Digital In 4 5 6 FUNCTION Power Down 1.8V Regulator 1: Power Down; 0:Power on LNA VDD NC Easy channel selection (Internal pull high) SPI bus data input Easy channel selection (Internal pull high) SPI bus latch enable input Easy channel selection (Internal pull high) SPI bus clock input Switch mode or SPI selection 1 At easy channel selection mode : BX is used for alternative band selection 1 At SPI mode : BX is Don’t care 3.3V Digital Power RF synthesizer digital ground pad RF synthesizer digital ground pad Crystal Input Crystal Input NC Charge Pump Output Synthesizer VDD Internal test only, don’t care RFVCO Vtune 2G VCO VDD Regulator/Bias Center VDD Regulator 1.8V for Digital Reference current by connecting 10k resistor IFA_AF inputs IFA_AF inputs AGC Rectifier output Baseband 2.5V Supply FSK comparator Input Video amp reference FMDeMod Buffer negative output Video amp input Video amp 3.3V VDD Video amp output Video amp linearity control 1 (Default): for high linearity mode IFVCO VDD IFVCO switched cap Control 1 IFVCO switched cap Control 2 FSKCOM Slicer time constant Adjust FSK comparator 3.3V VDD FSKCOM Slicer hysteresis control FSK comparator Output Baseband 2.5V Supply IFA_BF outputs 34 VCOD5VDD Supply In 35 X1 Digital In 36 X2 Digital In 37 SLICER_RC Analog I/O 38 FSKVDD Supply In 39 HYS_C Digital In 40 FSKCOMOUT Analog Out 41 BBVDD1 Supply In 42 IFAOUTN Analog Out www.richwave.com.tw Specifications subject to change without notice Rev V.004 Preliminary Confidential Proprietary 3 RTC6711 Preliminary Data Sheet Dec 2005 Pin Descriptions (continued) PIN 43 44 45 46 47 48 NAME IFAOUTP VDD33_IFA IFAVDD RFGND RFIN LNA_LG I/O Analog Out Supply In Supply In Analog In Analog In Digital In FUNCTION IFA_BF outputs IFA_BF ESD 3.3V VDD IFA_BF and Mixer 2.5V VDD LNA input be tied to RF ground 2.4 GHz LNA input for RF input signal LNA high/low gain control Note 1. Digital pins BX and SPI_SE (7,8) are without internal pull-high circuits, therefore those pins can not be left floating for logical high operation. PD_REG18 1 LNAVDD 2 RFIN2 3 SPIDATA(CS2) 4 SPILE(CS1) 5 SPICLK(CS0) 6 SPI_SE 7 BX 8 BBVDD1 FSKCOMOUT HYS_C FSKVDD SLICER_RC 45 IFAOUTN 46 IFAOUTP RFGND 47 VDD33_IFA RFIN 48 IFAVDD LNA_LG Block Diagram 44 43 42 41 40 39 38 37 36 X2 IFA BF LNA 35 X1 34 VCOD5VDD 33 THD_C AGC 32 VAMPOUT VCO FSK VAMP Comp X2 X1 30 VAMPIN VCO Demodulation Demodulation Synthesizer SPI 29 BBOUT2 Buffer VDD33D 9 31 VAMPVDD 28 VAMP_REF Buffer VSS_SYN3 10 27 FSKCOMIN AGC VSS_SYN4 11 26 BBVDD0 19 20 21 22 VDD2D5 REG1D8 BCR www.richwave.com.tw Specifications subject to change without notice Rev V.004 23 24 IFINN 18 IFINP 17 VCO2GVDD CP 16 VT2G 15 S2 14 VDD_SYN 13 LOCK_DT 25 AGC_C XTAL2 XTAL1 12 Preliminary Confidential Proprietary 4 RTC6711 Preliminary Data Sheet Dec 2005 Electrical Specification (1) Absolute Maximum Ratings SYMBOL PARAMETER Ratings UNIT Tstr Storage Temperature Range -65 to +150 °C Totr Vdd Vlog VRX Operating Temperature Range -40 to +85 Supply Voltage Logic control signal RX input -0.5 to +5 -0.5 to +5 -2 to +2 °C V V V The maximum rating must not be exceeded at any time. Do not operate the device under conditions outside the above (2) DC Electrical Characteristics SYMBOL PARAMETER CONDITION Tj VDD2D5 VDD33 Temperature Range Analog Supply Voltage 3.3V Supply Voltage I_RF Power consumption for IC I_module Power consumption under test circuit TT 25C, 2.5V/3.3V TT 25C, 2.5V/3.3V I_pd Power down current leakage TT 25C, 2.5V Fref V_IH V_IL Oscillator operating frequency High Level Input Voltage for Digital Interface Low Level Input Voltage for Digital Interface MIN. TYP. MAX. UNIT -40 2.25 3.1 25 2.5 3.3 85 2.75 3.5 °C V V 94 mA 140 mA 1 10 8 V_IO=3V uA MHz 0.7xV_IO V_IO+0.3 V -0.3 0.3xV_IO V (3) Receiver Specifications SYMBOL RF_Freq IF_Freq S11 PARAMETER CONDITION RF Input frequency IF output frequency RF Input return loss under test circuit Z22_IFout IF 479.5MHz output Impedance Z22_IFin IF 479.5MHz Input Impedance SE Phase noise TYP. MAX. UNIT 2510 479.5 MHz MHz -10 dB -87 dBm 2370 External matching@50Ω SNR 45dB Fmod=15KHz LPF BW:20KHz 100KHz offset 1MHz offset SE Si MIN. Input Sensitivity measurement under test circuit 1934.5MHz www.richwave.com.tw Specifications subject to change without notice Rev V.004 -110 -120 70 280 dBc/Hz Ω Ω Preliminary Confidential Proprietary 5 RTC6711 Preliminary Data Sheet Dec 2005 (3) Receiver Specifications (continued) SYMBOL Video Output signal level PARAMETER CONDITION Vpp after video amplifier Useable S/N 20dB higher than sensitivity VRSSI RSSI Output Voltage (AGC_C pin) MIN. 75ohm load Fmod=15KHz LPF BW:20KHz Monotonically -85dBm to 5dBm TYP. MAX. UNIT 1 Vpp 60 dB 1.68 1.9 V Audio Output signal level Vpp after Audio Amplifier THD Total harmonic distortion Output 1Vpp (1KHz tone) S/N Audio SNR (as reference design,) With pre-emphasis/ de-emphasis Fmod: 1KHz tone Frequency deviation: ±25Khz Load: > 1Kohm Fmod: 1KHz tone Frequency deviation: ±25Khz Load: > 1Kohm Fmod: 1KHz tone Frequency deviation: ±25Khz Load: > 1Kohm FSK application Data Slicer As reference design Bit rate www.richwave.com.tw Specifications subject to change without notice Rev V.004 1 0.6 45 Vpp 0.9 % 47 dB 4 Mbps Preliminary Confidential Proprietary 6 RTC6711 Preliminary Data Sheet Dec 2005 (4) SPI Digital Timing Diagram 1st data 2nd data Control Bit Invalid Data DATA LSB MSB CLK t1 t2 t3 t6 t7 LE t4 t5 P a ra me t er M in. Ty p. M a x. Un it t1 20 - - ns t2 20 - - ns t3 30 - - ns t4 30 - - ns t5 100 - - ns t6 20 - - ns t7 100 - - ns Note: 1.) On the rising edge of the clock, one bit of data is transferred into the shirt register. 2.) LE should be *L* when the data is transferred into the shirt register. www.richwave.com.tw Specifications subject to change without notice Rev V.004 Preliminary Confidential Proprietary 7 RTC6711 Preliminary Data Sheet Dec 2005 Channel Selection There are two principle modes for channel selection SPI_SE (Pin 7) High Low Mode SPI Mode Easy Channel Selection Mode (1) Easy channel selection mode Pin 7 (SPI_SE) set low (0V), and the chip operates in Easy Channel Selection Mode. Operation frequency is selected by the pins 4(CS2), 5(CS1) and 6(CS0). The selected channel frequencies are listed in Table below. BX=0 Pin8 (BX) is pulled low for normal ISM band, and operation frequency table show as following Table. BX SPI_SE Pin6/Pin5/Pin4 CS0/CS1/CS2 101 110 S2 011 0 0 0 2414MHz 2432MHz 111 2450MHz 2468MHz BX=1 Reserved for alternative band selection (2) SPI mode When pin 7 (SPI_SE) is set at high (3.3V), the chip works as in the SPI mode and the pins 5(SPIDATA), 5(SPILE) and 6(SPICLK)are used for ‘SPI’ inputs for 3-wire programming interface. The BX is “don’t care”. SPI Register Definition Address 00: Synthesizer Register A Bits 23 22 21 20 19 Name Default 18 17 16 15 14 13 12 11 10 9 8 SYN_RF_R_REG [14:0] 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 SYN_RF_A_REG [6:0] 1 0 0 0 0 0 0 1 1 1 0 1 0 Address 1 0 0 SYN_RF_R_REG [14:0]: R counter divider ratio control for RF Synthesizer. SYN_RF_A_REG [6:0]: A counter divider ratio control for RF Synthesizer. For integer N Synthesizer, the RF LO frequency is calculated by (N*32+A)*fref/R, where fref is the frequency of external reference oscillator (8 MHz). For default operation (f = 2414MHz, flo=1934.5MHz), Default: R=16; N=120; A=29 1934.5MHz= (120*32+29)*8MHz/16 www.richwave.com.tw Specifications subject to change without notice Rev V.004 Preliminary Confidential Proprietary 8 RTC6711 Preliminary Data Sheet Dec 2005 22 21 20 Name Default 19 18 17 16 15 14 13 12 11 10 0 0 0 0 0 1 1 1 8 CP_RF [2:0] SYN_RF_N_REG [12:0] 0 9 1 0 0 0 0 0 7 1 0 6 5 4 Not Used X X X 3 2 Not Used 23 SC_ctrl Bits Not Used Address 01: Synthesizer Register B X X 1 0 Address 0 1 SYN_RF_N_REG [12:0] : N counter divider ratio control for RF Synthesizer. CP_RF [2:0] RF charge pump current control (from 50uA to 6mA, default=100uA) SC_ctrl: external/internal SC_select control pin (LOW=internal). If set “1” in RTC67 series then charge pump will enter the testing mode ----Only for internal testing Address 10: Synthesizer Register C Bits Name Default 23 22 21 20 19 18 17 LNAMIX_ctrl [2:0] 1 1 16 15 14 13 12 0 LNAMIX_ctrl [2:0]: 0 0 1 0 10 9 Mout [1:0] Not Used 0 11 0 0 1 0 0 0 8 7 6 PRE_ctrl [2:0] 1 0 5 4 IFA_ctrl [2:0] 1 0 0 3 2 Not used 0 1 1 0 Address 0 1 0 1 0 For Rx Mixer LO_BUFFER bias current fine-tuning. Ibias(000,001,010,011,100,101,110,111)=(0,30uA,60uA,90uA,120uA,150uA ,180uA,210uA) Multi-function output select (00,01,11,10)=(gnd, lock in detect ,RF divider output, reference clk output) Prescaler current control ([001]~[111])=(20 ~ 140uA). For Rx IFA bias fine-tuning ([000] ~ [111])=240uA+15uA*(0~7) Mout [1:0]: PRE_ctrl [2:0]: IFA_ctrl [2:0]: 22 21 20 Name Default 19 18 17 16 15 14 13 Not Used 0 0 0 0 0 0 0 0 0 0 0 12 11 10 VCOSC [1:0] 1 0 0 9 8 7 6 5 Not used 0 0 0 4 3 0 0 2 AC10_DMVCOPOUT [1:0] 23 Not used Bits Not used Address 11: Synthesizer Register D 0 0 Address 0 1 1 VCOSC[1:0] : The RF VCO switch capacitance AC10_DMVCOPOUT [1:0] : The demodulation VCO output swing adjustment AC10_DMVCOPOUT [1:0] Total Rb (ohm) www.richwave.com.tw Specifications subject to change without notice Rev V.004 Preliminary Confidential Proprietary 9 RTC6711 Preliminary Data Sheet Dec 2005 PACKAGE QFN 7X7 48 pins www.richwave.com.tw Specifications subject to change without notice Rev V.004 Preliminary Confidential Proprietary 10