Multimedia ICs Status display LCD driver for PCs with I2C Bus interface BU9910KV The BU9910KV is a status LCD driver with I2C Bus intetface. Various lighting mode can be controlled through I2C Bus. In addition, 20 direct drive inputs allow the application to drive 20 elements directly without I2C Bus, so that the system configuration can be kept simple. •PCsApplications •1)Features I C Bus interface. 2 2) Drive up to 44 LCD cells. 4 common × 11 segment, 1 / 3 bias, 1 / 4 duty 3) Blink operation for eaeh cell. 4) Support four frame frequencies 256Hz, 128Hz, 64Hz, 32Hz (at fOSC = 32.768kHz) 5) 20 direct drive inputs, which allow the application to drive LCD directly without I2C control. 6) Minimum LCD drive time is guaranteed for direct in. 7) LCD device test ferminals.(LCDT0, LCDT1) 8)Power aupply voltages: 3.3V to 5.0V 1 Multimedia ICs BU9910KV SEG10 DIN19 DIN18 DIN17 DIN16 DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 •Block diagram 36 35 34 33 32 31 30 29 28 27 26 25 37 24 DIN7 Date Latch Logic SEG9 38 23 DIN6 SEG8 39 22 DIN5 SEG7 40 21 DIN4 SEG6 41 20 DIN3 SEG5 42 19 DIN2 SEG4 43 18 DIN1 SEG3 44 17 DIN0 SEG2 45 16 HT1 Control Logic I2CBus Interface Segment Driver Timing Generator Common Driver 2 1 2 3 4 5 6 7 8 9 10 11 12 SCL LCDT0 SDA 13 #RES 48 CLK VDD COM0 LCDT1 COM1 14 COM2 47 COM3 SEG0 GND HT0 VL1 15 VL2 46 VL3 SEG1 Multimedia ICs BU9910KV •Pin descriptions Pin No. Pin name Function 1 VL3 Input for LCD driver 2 VL2 Input for LCD driver (2 / 3) 3 VL1 Input for LCD driver (1 / 3) 4 GND Ground 5 COM3 LCD common driver output 3 6 COM2 LCD common driver output 2 7 COM1 LCD common driver output 1 8 COM0 LCD common driver output 0 ∗VL3 ∗VL3 9 CLK 10 #RES Reset 11 SDA I2CBus Serial Data Line 12 SCL I2CBus Serial Clock Input 13 LCDT0 LCD Device test mode set 0 14 LCDT1 LCD Device test mode set 1 15 HT0 Direct IN Hold time set 0 16 HT1 Direct IN Hold time set 1 17 DIN0 Direct IN 0 18 DIN1 Direct IN 1 19 DIN2 Direct IN 2 20 DIN3 Direct IN 3 21 DIN4 Direct IN 4 22 DIN5 Direct IN 5 23 DIN6 Direct IN 6 24 DIN7 Direct IN 7 25 DIN8 Direct IN 8 26 DIN9 Direct IN 9 27 DIN10 Direct IN 10 28 DIN11 Direct IN 11 29 DIN12 Direct IN 12 30 DIN13 Direct IN 13 31 DIN14 Direct IN 14 32 DIN15 Direct IN 15 33 DIN16 Direct IN 16 34 DIN17 Direct IN 17 35 DIN18 Direct IN 18 36 DIN19 Direct IN 19 Clock input (ex.32.768kHz) 3 Multimedia ICs BU9910KV Pin No. Pin name 37 SEG10 Function 38 SEG9 LCD segment driver output 9 39 SEG8 LCD segment driver output 8 40 SEG7 LCD segment driver output 7 41 SEG6 LCD segment driver output 6 42 SEG5 LCD segment driver output 5 43 SEG4 LCD segment driver output 4 44 SEG3 LCD segment driver output 3 45 SEG2 LCD segment driver output 2 46 SEG1 LCD segment driver output 1 47 SEG0 LCD segment driver output 0 48 VDD Supply Voltage 3.0V to 5.5V LCD segment driver output 10 •Absolute maximum ratings (Ta = 25°C) Parameter Symbol Limits Unit Applied voltage VDD 7.0 Power dissipation Pd 400∗ mW Operating temperature Topr – 15 ~ + 75 °C Storage temperature Tstg – 55 ~ + 125 °C Input voltage VIN V V GND – 0.5 ~ VDD + 0.5 ∗ Reduced by 4mW for each increase in Ta of 1°C over 25°C. 䊊 ROHM holds a license from Philips semicondoctors for the “I2C Bus.” •Electrical characteristics (unless otherwise noted, Ta = 25°C, V DD Parameter Symbol Min. Typ. = 5.0V) Max. Unit Conditions Bias 51kΩ × 3 Circuit current IDD 20 35 50 µA Input high level voltage VIH VDD∗0.7 VDD VDD + 0.5 V — Input low level voltage VIL 0.0 VDD∗0.3 V — Input high level current IIH 0.0 1.0 µA — Input low level current IIL – 1.0 0.0 — µA — VOLsda 0.0 0.2 0.6 V IOL = 6.0mA tfsda — — 250 ns CL = 400pF IOL = 6.0mA Output intermediate level voltage VL3 VOM3 VL3 – 0.1 VL3 VL3 + 0.1 V IOM3 = 100µA Output intermediate level voltage VL2 VOM2 VL2 – 0.1 VL2 VL2 + 0.1 V IOM2 = 100µA Output intermediate level voltage VL1 VOM1 VL1 – 0.1 VL1 VL1 + 0.1 V IOM1 = 100µA VOL 0.0 0.2 0.6 V IOL = 100µA RPU 24k 30k 36k Ω – 0.5 — 〈SDA pin〉 Output low level voltage Output fall time 〈COM, SEG pins〉 Output low level voltage 〈LCDT pin〉 Pull-up resistance 䊊 Not designed for radiation resistance. 4 — Multimedia ICs BU9910KV •Input / output circuits Pin No. Pin name Equivalent circuit Pin description 11 SDA I2C Bus serial data input / output. 12 SCL I2C Bus serial clock Input. 9 CLK Clock Input for LCD display. Clock frequency is 32.768kHz. Reset input.(Low Active) Low: Reset all internal registers. 10 #RES Note: Require external power on reset. 4 GND 48 VDD Ground terminal. Power supply. 3.0V to 5.5V supply voltage range. 5 Multimedia ICs BU9910KV Pin No. Pin name Equivalent circuit Pin description 5~8 COM0 ~ COM3 LCD common drive output. 37 ~ 47 SEG0 ~ SEG10 LCD segment drive output. Input of LCD drive voltage setting. Supply the 1 / 3 ∗ VL3 voltage to VL1. 1 2 3 17 ~ 36 6 VL3 VL2 VL1 DIN0 ~ DIN19 Supply the 2 / 3 ∗ VL3 voltage to VL2. Supply the VDD or the zero to VDD voltage to VL3 . Direct drive Input.(High Active) The drive time is set from the HT0 and HT1 terminals, and the drive starts from a rising edge of the direct drive Inputs. LCD cells will be driven while the direct drive Input remains high. Multimedia ICs Pin No. Pin name 15 ~ 16 HT0 ~ HT1 13 ~ 14 LCDT0 ~ LCDT1 BU9910KV Equivalent circuit Pin description Hold time setting terminal of the direct drive input. There are four hold times to drive the cell. 30kΩ: VDD = 5.0V LCD device test terminal. 7 Multimedia ICs BU9910KV •Application example VDD COM0 VDD COM1 VR COM2 VL3 COM3 R VL2 SEG0 R SEG1 VL1 C C C 44 Segment LCD R Power on Reset fosc = 32.768kHz I2C Bus Controller #RES BU9910KV GND SEG9 SEG10 CLK SCL SDA DIN0 DIN1 Set direct in hold time LCD panel test HT0 HT1 Direct In LCDT0 DIN18 LCDT1 DIN19 Note: Choose appropriate values of Road C and R for the LCD panel and application. Fig.1 8 (HDD.FDD.etc) Multimedia ICs BU9910KV operation •(1)Circuit Description of the I C Bus interface 2 1) Slave address 0 1 1 1 0 MSB 0 1 R/W LSB 2) Conformance to I2C Bus standards Parameter Symbol Min. Max. Unit f SCL 0 400 kHz Start condition hold time t HD: STA 0.6 – µs Start condition setup time t SU: STA 0.6 – µs Data setup time t SU: DAT 100 – ns Data hold time t HD: DAT 0 0.9 µs Stop condition setup time t SU: STO 0.6 – µs SCL clock frequency (Start condition) SCL SDA t SU: STA t HD: STA (Data condition) SCL SDA t SU: DAT t HD: DAT (Stop condition) SCL SDA t SU: STO 9 Multimedia ICs BU9910KV (2) Data structure 1) Wrote Mode S – W Address A Command Reg. Byte A Write Data Byte A P – A P Auto Increment 2) Read Mode 1. Command register set S – W Address A Command Reg. Byte Sr Address R A A Read Data Byte Auto Increment 2. Preset command register S Address R A Read Data Byte – A P Auto Increment ∗ In multi-master application, the preset command register mode is prohibited. S: Start condition P: Stop condition Sr: Restart condition A: Acknowledge A: Acknowledge bar (3) Mode settings table 1) Command Register (commands and pointers) D7 Disp D6 D5 D4 Frame freq. D3 Blink freq. The all bit may be "0"during the reset procedure. D7: Display control 0: Light (depend on the LCD segment data memory status ) 1: All off D6, D5: Frame frequency select D6 D5 f0 0 0 32Hz (default) 0 1 64Hz 1 0 128Hz 1 1 256Hz At fosc = 32.768kHz D4: Blink frequency select 0: Blink frequency = 0.5Hz (default) 1: Blink frequency = 1Hz 10 D2 D1 Pointer register D0 Multimedia ICs BU9910KV D3 to D0: Pointer register The Pointer register appoints a base address, which acceses the LCD display memory in read or write mode. In the write mode, a byte data that follows command byte is written to the LCD display memory which is appointed by the pointer register. Write address is incremented automatically and more than 2 bytes data are written to continuous place that starts from the base address. A master controller can continue to access the LCD display memory untill it generates the stop condition. In the read mode, the master reads the LCD display memory data that is appointed by the pointer register. Read adress is incremented automatically and the master read the LCD display memory data of continuous address that starts from the base address. The master can continue to access the LCD display memory data until it generates the NO ACK & Stop Condition. The pointer register value should be 0000b(0h) to 1011b(Bh) and becomes 0h after Bh. Do not set Ch, Dh, Eh, Fh to the pointer register. 2) LCD display memory LCD driving condition Segment data memory Blink control memory Driving condition 0 0 Off 0 1 Off 1 0 Light 1 1 Blink Segment data memory: SEG vs. COM(COM No. / SEG No.) Base address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0000b 3/1 2/1 1/1 0/1 3/0 2/0 1/0 0/0 0001b 3/3 2/3 1/3 0/3 3/2 2/2 1/2 0/2 0010b 3/5 2/5 1/5 0/5 3/4 2/4 1/4 0/4 0011b 3/7 2/7 1/7 0/7 3/6 2/6 1/6 0/6 0100b 3/9 2/9 1/9 0/9 3/8 2/8 1/8 0/8 0101b 0 0 0 0 3 / 10 2 / 10 1 / 10 0 / 10 11 Multimedia ICs BU9910KV Blink control memory: SEG vs. COM(COM No. / SEG No.) Base Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0110b 3/1 2/1 1/1 0/1 3/0 2/0 1/0 0/0 0111b 3/3 2/3 1/3 0/3 3/2 2/2 1/2 0/2 1000b 3/5 2/5 1/5 0/5 3/4 2/4 1/4 0/4 1001b 3/7 2/7 1/7 0/7 3/6 2/6 1/6 0/6 1010b 3/9 2/9 1/9 0/9 3/8 2/8 1/8 0/8 1011b 0 0 0 0 3 / 10 2 / 10 1 / 10 0 / 10 3) Direct drive input description Direct input pin vs.SEG / COM SEG6 SEG7 SEG8 SEG9 SEG10 COM0 DIN0 DIN4 DIN8 DIN12 DIN16 COM1 DIN1 DIN5 DIN9 DIN13 DIN17 COM2 DIN2 DIN6 DIN10 DIN14 DIN18 COM3 DIN3 DIN7 DIN11 DIN15 DIN19 In the test mode, the specified lighting is carried out regardless of the state of the segment data register. Setting pins to the open state returns to the normal state without carrying out a reset. Holding time setting(when activate the direct input pins) HT1 HT0 Holding time L L 0.125s ⬉ HT < 0.156s L H 0.250s ⬉ HT < 0.313s H L 0.500s ⬉ HT < 0.625s H H 1.000s ⬉ HT < 1.250s At fosc = 32.768kHz 4) LCD device test terminal description LCD device test pins setting table LCDT1 LCDT0 Lighting conditions L L Test mode : All cells are turned on L H Test mode : 10100101b (set all Segment Data Memory) H L Test mode : 01011010b (set all Segment Data Memory) H H Normal: Controlled by the LCD display memory When these pins are low, the Segment data memory are ignored. Each of LCDT1 and LCDT2 has a pull-up resister. When these pins are open, return to nomal operation without reset. 12 Multimedia ICs BU9910KV (4) Output waveforms (1 / 2) To = 1 / fo VL3 VL2 VL1 VSS • COM 0 Drive Output VL3 VL2 VL1 VSS • COM 1 Drive Output VL3 VL2 VL1 VSS • COM 2 Drive Output VL3 VL2 VL1 VSS • COM 3 Drive Output VL3 VL2 VL1 VSS • SEG Drive Output COM 0-off, COM 1-off, COM 2-off, COM 3-off • SEG Drive Output COM 0-ON, COM 1-off, COM 2-off, COM 3-off VL3 VL2 VL1 VSS • SEG Drive Output COM 0-off, COM 1-ON, COM 2-off, COM 3-off VL3 VL2 VL1 VSS • SEG Drive Output COM 0-off, COM 1-off, COM 2-ON, COM 3-off VL3 VL2 VL1 VSS • SEG Drive Output COM 0-off, COM 1-off, COM 2-off, COM 3-ON VL3 VL2 VL1 VSS VL3 VL2 VL1 VSS • SEG Drive Output COM 0-ON, COM 1-ON, COM 2-ON, COM 3-ON 1 / 3 bias, 1 / 4 duty waveforms 13 Multimedia ICs BU9910KV (5) Output waveforms (2 / 2) To = 1 / fo VL3 VL2 VL1 VSS • COM 0 Drive Output VL3 VL2 VL1 VSS • COM 1 Drive Output VL3 VL2 VL1 VSS • COM 2 Drive Output VL3 VL2 VL1 VSS • COM 3 Drive Output VL3 VL2 VL1 VSS • SEG Drive Output COM 0-ON, COM 1-off, COM 2-ON, COM 3-off VL3 VL2 VL1 VSS • SEG Drive Output COM 0-ON, COM 1-off, COM 2-ON, COM 3-off • SEG Drive Output COM 0-ON, COM 1-off, COM 2-off, COM 3-ON VL3 VL2 VL1 VSS • SEG Drive Output COM 0-off, COM 1-ON, COM 2-ON, COM 3-off VL3 VL2 VL1 VSS • SEG Drive Output COM 0-off, COM 1-ON, COM 2-off, COM 3-ON VL3 VL2 VL1 VSS • SEG Drive Output COM 0-off, COM 1-off, COM 2-ON, COM 3-ON VL3 VL2 VL1 VSS 1 / 3 bias, 1 / 4 duty waveforms 14 Multimedia ICs BU9910KV •External dimensions (Units: mm) 9.0 ± 0.3 7.0 ± 0.2 24 48 13 1 1.425 ± 0.1 0.10 25 0.5 12 0.5 7.0 ± 0.2 9.0 ± 0.3 36 37 0.125 ± 0.1 0.2 ± 0.1 0.10 VQFP48 15