V6210610 VID

REVISIONS
LTR
DESCRIPTION
A
Add case outline Y. Add paragraph 1.6.
Make change to output current, from 72 mA to
130 mA as specified under paragraph 1.3.
Make changes to constant output current under
paragraph 1.4. Under Table I; IOLC test, delete
DATE
APPROVED
10-05-18
C. SAFFLE
45 mA and substitute 42 mA, IOLC0 test, delete
11% and substitute 12%; IOLC3 test, delete
10%/V and substitute 11%/V; and IOLC4 test,
delete 15%/V and substitute 20%/V. - ro
Prepared in accordance with ASME Y14.24
Vendor item drawing
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PMIC N/A
PREPARED BY
RICK OFFICER
Original date of drawing
YY-MM-DD
CHECKED BY
RAJESH PITHADIA
10-04-08
TITLE
MICROCIRCUIT, LINEAR, 16 CHANNEL,
CONSTANT CURRENT SINK LED DRIVER,
MONOLITHIC SILICON
APPROVED BY
CHARLES F. SAFFLE
SIZE
A
REV
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
CODE IDENT. NO.
DWG NO.
V62/10610
16236
A
PAGE
1
OF
19
5962-V048-10
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a 16 channel, constant current sink light emitting diode (LED) driver
microcircuit, with an operating temperature range of -40C to +125C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
-
V62/10610
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Generic
Device type
01
Circuit function
TLC5940-EP
16 channel, constant current sink LED driver
1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter
Number of pins
X
Y
28
32
JEDEC PUB 95
Package style
MO-153
MO-220
Plastic surface mount with thermal pad
Plastic quad flat pack
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture:
Finish designator
A
B
C
D
E
Z
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Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
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1.3 Absolute maximum ratings.
1/ 2/
Input voltage range (VIN) ........................................................................................... -0.3 V to 6 V 3/
Output current (dc) (IOUT) .......................................................................................... 130 mA
Input voltage range (VIN):
VBLANK, VDCPRG, VSCLK, VXLAT, VSIN, VGSCLK, VIREF ..................................... -0.3 V to VCC +0.3 V
Output voltage range:
VSOUT, VXERR ....................................................................................................... -0.3 V to VCC +0.3 V
VOUT0 to VOUT15 ...................................................................................................
ElectrIcally eraseable programmable read only memory (EEPROM)
program range ........................................................................................................
EEPROM write cycles ................................................................................................
Electrostatic discharge (ESD) rating:
Human body model (HBM) .....................................................................................
Charge device model (CDM) ..................................................................................
Power dissipation (PD) ...............................................................................................
Storage temperature range (TSTG) ..............................................................................
Operating free-air temperature range (TA) .................................................................
Package thermal impedance ......................................................................................
-0.3 V to 18 V
-0.3 V to 24 V
25
2 kV
500 V
See 1.5, dissipation ratings
-55C to +150C
-40C to +125C
See 1.6, thermal characteristics
1.4 Recommended operating conditions. 4/
DC characteristics
Supply voltage (VCC) ............................................................................................. 3 V to 5.5 V
Voltage applied to output (OUT0 - OUT15) (VOUT) ............................................... 17 V
High level input voltage (VIH) ................................................................................. 0.8VCC to VCC
Low level input voltage (VIL) .................................................................................. GND to 0.2VCC
High level output current (IOH) (VCC = 5 V at SOUT) ............................................ -1 mA
Low level output current (IOL) (VCC = 5 V at SOUT) .............................................. 1 mA
Constant output current (IOLC) (OUT0 to OUT15):
( –40°C to 125°C ) .............................................................................................. 72 mA
( –40°C to 85°C, VCC  3.6 V ) ........................................................................... 60 mA
( –40°C to 85°C, VCC  3.6 V ) ........................................................................... 120 mA
EEPROM program range (VPRG) .......................................................................... 20 V to 23 V
1/
2/
3/
4/
Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
Long term high temperature storage and/or extended use at maximum recommended operating conditions may result in a
reduction of overall device life. See manufacturer for additional information on enhanced plastic packaging.
All voltages are within respect to device GND terminal.
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
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1.4 Recommended operating conditions - continued. 4/
AC characteristics (unless otherwise specified, VCC = 3 V to 5.5 V)
Data shift clock frequency (fSCLK) ......................................................................... 30 MHz
Grayscale clock frequency (fGSCLK) ...................................................................... 30 MHz
SCLK pulse duration ( twh0 / twl0 ) (SCLK = H/L) see figure 3 ............................... 16 ns
GSCLK pulse duration ( twh1 / twl1 ) (GSCLK = H/L) see figure 3 .......................... 16 ns
XLAT pulse duration ( twh2 ) (XLAT = H) see figure 3 ............................................ 20 ns
BLANK pulse duration ( twh3 ) (BLANK = H) see figure 3 ...................................... 20 ns
Setup time: 5/
tsu0 ( SIN to SCLK  ) see figure 3 .................................................................... 5 ns
tsu1 (SCLK  to XLAT  ) see figure 3 ............................................................... 10 ns
tsu2 (VPRG  to SCLK  ) see figure 3 ........................................................... 10 ns
tsu3 (VPRG  XLAT  ) see figure 3 ................................................................ 10 ns
tsu4 (BLANK  to GSCLK  ) see figure 3 ......................................................... 10 ns
tsu5 (XLAT  to GSCLK  ) see figure 3 ............................................................ 30 ns
tsu6 (VPRG  to DCPRG  ) see figure 4 .......................................................... 1 ms
Hold time: 5/
th0 (SCLK  to SIN ) see figure 3 ...................................................................... 3 ns
th1 (XLAT  to SCLK  ) see figure 3 ................................................................ 10 ns
th2 (SCLK  to VPRG  ) see figure 3 ............................................................. 10 ns
th3 (XLAT  to VPRG  ) see figure 3 ............................................................. 10 ns
th4 (GSCLK  to BLANK  ) see figure 3 ........................................................... 10 ns
th5 (DCPRG  to VPRG  ) see figure 3 ............................................................ 1 ms
tprog (programming time for EEPROM) see figure 4 ............................................. 20 ms
1.5 Dissipation ratings.
Package
Power rating
TA  25C
Derating factor
above
TA = 25C
Power rating
TA = 70C
Power rating
TA = 85C
Power rating
TA = 125C
Case X, thermal pad
soldered 1/
3958 mW
31.67 mW/C
2533 mW
2058 mW
791 mW
Case X, thermal pad
unsoldered
2026 mW
16.21 mW/C
1296 mW
1053 mW
405 mW
Case Y 1/
3482 mW
27.86 mW/C
2228 mW
1811 mW
696 mW
1/ The power pad is soldered to the printed circuit board with 2 ounce (56.7 grams) copper trace.
_____
5/  and  indicates a rising edge, and a falling edge respectively.
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1.6 Thermal characteristics.
Thermal metric
Symbol
Case X
Case Y
Unit
JA
35.4
33.9
C/W
JC(TOP)
29.94
30
C/W
JC(BOTTOM)
5.37
3.9
C/W
Thermal resistance, junction-to-board 4/
JB
15.02
9.3
C/W
Characterization parameter, junction-to-top 5/
JT
1.297
0.619
C/W
Characterization parameter, junction-to-board 6/
JB
10.96
9.3
C/W
Thermal resistance, junction-to-ambient 1/
Thermal resistance, junction-to-case (top) 2/
Thermal resistance, junction-to-case (bottom) 3/
1/
The thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a
JEDEC standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
2/
The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the package top.
No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
3/
The thermal resistance, junction-to-case (bottom) is obtained by simulations of this device as configured per
MIL-STD-883 method 1012.1.
4/
The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate
fixture to control the printed circuit board (PCB) temperature, as described in JESD51-8.
5/
Characterization parameter, junction-to-top (JT ) estimates the junction temperature of a device in a real system
and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6
and 7).
6/
Characterization parameter, junction-to-board (JB ) estimates the junction temperature of a device in a real system
and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6
and 7).
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2. APPLICABLE DOCUMENTS
JEDEC PUB 95
JESD51-2a
JESD51-7
JESD51-8
-
Registered and Standard Outlines for Semiconductor Devices
Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convention (still air)
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Integrated circuits Thermal Test Method Environmental Conditions - Junction to Board
(Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington,
VA 22201-3834 or online at http://www.jedec.org)
ANSI SEMI STANDARD G30-88 Packages
Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic
(Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and
Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http://www.ansi.org)
MIL-STD-883
-
Test Method Standard Microcircuits.
(Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization Document
Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are
as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Serial data input timing waveforms. The serial data input timing waveforms shall be as shown in figure 3.
3.5.4 EEPROM programming timing waveforms. The EEPROM programming timing waveforms shall be as shown in figure 4.
3.5.5 Parameter measurement circuits. The parameter measurement circuits shall be as shown in figure 5.
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TABLE I. Electrical performance characteristics. 1/
Test
Symbol
Conditions
VCC = 3 V to 5.5 V
unless otherwise specified
Temperature,
TA
Device
type
Min
High level output
voltage
VOH
IOH = -1 mA, SOUT
-40C to +125C
01
Low level output
voltage
VOL
IOL = 1 mA, SOUT
-40C to +125C
01
Input current
IIN
VIN = VCC or GND, BLANK,
DCPRG, GSCLK, SCLK, SIN, XLAT
-40C to +125C
01
VIN = GND, VPRG
Supply current
ICC
Limits
IOLC
see figure 5
Leakage output current
ILKG
Max
V
VCC
-0.5
0.5
V
-1
1
A
-2
2
VIN = VCC, VPRG
50
VIN = 21 V, VPRG, DCPRG = VCC
10
mA
6
mA
No data transfer, all output OFF,
VO = 1 V, RIREF = 10 k
01
-40C to +125C
No data transfer, all output OFF,
VO = 1 V, RIREF = 1.3 k
Constant sink current,
Unit
12
Data transfer 30 MHz, all output ON,
VO = 1 V, RIREF = 1.3 k
16 typical
Data transfer 30 MHz, all output ON,
VO = 1 V, RIREF = 640 
30 typical
01
+25C
All output ON, VO = 1 V,
54
69
42
72
mA
RIREF = 640 
-40C to +125C
All output OFF, VO = 15 V,
-40C to +125C
01
1
A
+25C
01
4
%
RIREF = 640 , OUT0 to OUT15
Constant sink current
error,
IOLC0
see figure 5
All output ON, VO = 1 V,
RIREF = 640 , OUT0 to OUT15
All output ON, VO = 1 V,
2/
-40C to +125C
12
+25C
4
-40C to +125C
8
RIREF = 640 , OUT0 to OUT15
All output ON, VO = 1 V,
RIREF = 1300 , OUT0 to OUT15
All output ON, VO = 1 V,
2/
RIREF = 1300 , OUT0 to OUT15
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
VCC = 3 V to 5.5 V
unless otherwise specified
Temperature,
TA
Device
type
Limits
Min
Unit
Max
Constant sink current
error,
see figure 5
IOLC1
Device to device, averaged
3/
current from OUT0 to OUT15,
RIREF = 1920  (20 mA)
-40C to +125C
01
-2 + 0.4 typical
%
Constant sink current
error,
see figure 5
IOLC2
Device to device, averaged
3/
current from OUT0 to OUT15,
RIREF = 480  (80 mA)
-40C to +125C
01
-2.7 + 2 typical
%
Line regulation,
IOLC3
All output ON, VO = 1 V,
+25C
01
see figure 5
IOLC4
see figure 5
11
+25C
4
RIREF = 1300 , OUT0 to OUT15
-40C to +125C
4
All output ON, VO = 1 V to 3 V, 5/
+25C
4/
TTEF
LED open detector
threshold
VLED
Reference voltage
output
VIREF
6
01
-40C to +125C
20
All output ON, VO = 1 V to 3 V, 5/
+25C
6
RIREF = 1300 , OUT0 to OUT15
-40C to +125C
6
Junction temperature 6/
-40C to +125C
01
-40C to +125C
01
-40C to +125C
01
RIREF = 640 , OUT0 to OUT15
Thermal error flag
threshold
4
-40C to +125C
RIREF = 640 , OUT0 to OUT15
All output ON, VO = 1 V,
Load regulation,
4/
RIREF = 640 
150
1.20
%/V
%/V
170
C
0.4
V
1.28
V
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
VCC = 3 V to 5.5 V
unless otherwise specified
Temperature,
TA
Device
type
Limits
Min
Unit
Max
tr0
SOUT
tr1
OUTn, VCC = 5 V, DCn = 3 Fh
tf0
SOUT
tf1
OUTn, VCC = 5 V, DCn = 3 Fh
tpd0
SCLK to SOUT, see figure 3
tpd1
BLANK to OUT0
tpd2
OUTn to XERR, see figure 3
tpd3
GSCLK to OUT0, see figure 3
60
tpd4
XLAT to IOUT (dot correction),
see figure 3
60
tpd5
DCPRG to OUT0, see figure 3
30
Output delay time
td
OUTn to OUT(n+1), see figure 3
-40C to +125C
01
Output on time error
ton-err
touton - tgsclk, GSn = 01h,
GSCLK = 11 MHz, see figure 3
-40C to +125C
01
Rise time
Fall time
Propagation delay time
01
60C
16
ns
30
01
60C
16
ns
30
01
-40C to +125C
30
ns
60
1000
10
30
ns
-90
ns
1/
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over
the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
2/
The deviation of each output from the average of OUT0-15 constant current.
It is calculated by equation: (%) = (( IOUTn - IOUTavg_0-15 ) / ( IOUTavg_0-15 )) x 100.
3/
The deviation of average of OUT1-15 constant current from the ideal constant-current value.
It is calculated by equation: (%) = (( IOUTavg - IOUT(IDEAL) ) / ( IOUT(IDEAL) )) x 100.
The ideal current is calculated: IOUT(IDEAL) = 31.5 x ( 1.24 V / RIREF ).
4/
The line regulation is calculated by equation:
(%/V) = ((( IOUTn at VCC = 5.5 V ) - ( IOUTn at VCC = 3.0 V )) / ( IOUTn at VCC = 3.0 V )) x ( 100 / 2.5 ).
5/
The load regulation is calculated by equation:
(%/V) = ((( IOUTn at VOUTn = 3.0 V ) - ( IOUTn at VOUITn = 1.0 V )) / ( IOUTn at VOUTn = 1.0 V )) x ( 100 / 2.0 ).
6/
Not tested. Specified by design.
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Case X
FIGURE 1. Case outlines.
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Case X – continued.
Dimensions
Inches
Symbol
Millimeters
Min
Max
Min
Max
A
---
0.047
---
1.20
A1
0.002
0.006
0.05
0.15
b
0.007
0.012
0.19
0.30
c
D
e
0.006 nominal
0.378
0.15 nominal
0.386
9.60
0.025 BSC
9.80
0.65 BSC
E
0.169
0.177
4.30
4.50
E1
0.244
0.259
6.20
6.60
L
0.019
0.029
0.50
0.75
n
28 leads
28 leads
NOTES:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2. Body dimensions do not include mold flash or protrusions. Mold flash and protrusion shall not exceed
0.15 mm (0.006 inch) on each side.
3. This package is designed to be soldered to a thermal pad on the board. Refer to technical brief, power pad thermally
enhanced package, manufacturer’s literature number SLMA002 for information regarding recommended board layout.
This document is available at www.ti.com.
4. Falls within reference to JEDEC MO-153.
FIGURE 1. Case outlines - Continued.
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Case Y
FIGURE 1. Case outlines - Continued.
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Case Y – continued.
Dimensions
Inches
Symbol
Millimeters
Min
Max
Min
Max
A
0.031
0.039
0.80
1.00
A1
---
0.001
---
0.05
A2
0.007 REF
0.20 REF
b
0.007
0.011
0.18
0.30
D/E
0.19
0.202
4.85
5.15
e
0.019 BSC
0.50 BSC
e1
0.137 BSC
3.50 BSC
S
n
0.011
0.019
0.30
32 leads
0.50
32 leads
NOTES:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2. The package thermal pad must be soldered to the board for thermal and mechanical performance.
3. Falls within reference to JEDEC MO-220.
FIGURE 1. Case outlines - Continued.
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Device type
Case outlines
Terminal
number
01
X
Y
Terminal symbol
Case outlines
Terminal
number
X
Y
Terminal symbol
1
GND
SCLK
17
OUT10
OUT11
2
BLANK
SIN
18
OUT11
OUT12
3
XLAT
VPRG
19
OUT12
OUT13
4
SCLK
OUT0
20
OUT13
OUT14
5
SIN
OUT1
21
OUT14
OUT15
6
VPRG
OUT2
22
OUT15
XERR
7
OUT0
OUT3
23
XERR
SOUT
8
OUT1
OUT4
24
SOUT
GSCLK
9
OUT2
OUT5
25
GSCLK
DCPRG
10
OUT3
OUT6
26
DCPRG
IREF
11
OUT4
OUT7
27
IREF
VCC
12
OUT5
NC
28
VCC
NC
13
OUT6
NC
29
---
NC
14
OUT7
OUT8
30
---
GND
15
OUT8
OUT9
31
---
BLANK
16
OUT9
OUT10
32
---
XLAT
FIGURE 2. Terminal connections.
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A
CODE IDENT NO.
16236
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Terminal
symbol
I/O
BLANK
I
DCPRG
I
GND
G
Ground
GSCLK
I
Reference clock for grayscale PWM control.
IREF
I
Reference current terminal.
NC
Description
Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF.
GS counter is also reset. When BLANK = L, OUTn are controlled by
grayscale PWM control.
Switch DC data input. When DCPRG = L, DC is connected to EEPROM.
When DCPRG = H, DC is connected to the DC register. DCPRG also controls
EEPROM writing, when VPRG = VPRG. EEPROM data = 3 Fh (default).
No connection.
OUT0
O
Constant current output.
OUT1
O
Constant current output.
OUT2
O
Constant current output.
OUT3
O
Constant current output.
OUT4
O
Constant current output.
OUT5
O
Constant current output.
OUT6
O
Constant current output.
OUT7
O
Constant current output.
OUT8
O
Constant current output.
OUT9
O
Constant current output.
OUT10
O
Constant current output.
OUT11
O
Constant current output.
OUT12
O
Constant current output.
OUT13
O
Constant current output.
OUT14
O
Constant current output.
OUT15
O
Constant current output.
SCLK
I
Serial data shift clock.
SIN
I
Serial data input.
SOUT
O
Serial data output.
VCC
I
VPRG
I
XERR
O
XLAT
I
Power supply voltage.
Multifunction input pin. When VPRG = GND, the device is in GS mode.
When VPRG = VCC, the device is in DC mode. When VPRG = VVPRG, DC
register data can be programmed into DC EEPROM with DCPRG = HIGH.
EEPROM data = 3Fh (default).
Error output. XERR is an open drain terminal. XERR goes L when LOD or
temperature error flag (TEF) is detected.
Level triggered latch signal. When XLAT = high, the device writes data from
the input shift register to either GS register (VPRG = low) or DC register
(VPRG = high). When XLAT = low, the data in GS or DC register is held
constant.
FIGURE 2. Terminal connections - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
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CODE IDENT NO.
16236
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FIGURE 3. Serial data input timing waveforms.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
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16
FIGURE 4. EEPROM programming timing waveforms.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
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DWG NO.
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17
FIGURE 5. Parameter measurement circuits.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/10610
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18
4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item.
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
Vendor part number
V62/10610-01XE
01295
TLC5940QPWPREP
V62/10610-01YE
01295
TLC5940QRHBREP
1/ The vendor item drawing establishes an administrative control number
for identifying the item on the engineering documentation.
2/ For the most current package and ordering information, see the package
option addendum at the end of the manufacturer’s data sheet ,
or use website www.ti.com.
CAGE code
01295
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
Source of supply
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
SIZE
A
CODE IDENT NO.
16236
REV
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DWG NO.
V62/10610
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