CY8CPLC10 Datasheet Powerline Communication Solution Powerline Communication Solution Features Functional Description ■ Integrated Powerline Modem PHY ■ 2400 bps Frequency Shift Keying Modulation ■ Powerline Optimized Network Protocol The CY8CPLC10 is an integrated Powerline Communication chip with the Powerline Modem PHY and Powerline Network Protocol Stack. This chip provides robust communication between different nodes on a Powerline. ■ Integrates Data Link, Transport, and Network Layers Powerline Transmitter ■ Supports Bidirectional Half-Duplex Communication ■ 8-bit CRC Error Detection to Minimize Data Loss The application residing on a host microcontroller generates messages to be transmitted on the Powerline. These messages are delivered to the CY8CPLC10 over an I2C serial link. ■ I2C enabled Powerline Application Layer I2C ■ Supports ■ Reference Designs for 110V to 240V AC, 12V to 24V AC/DC Powerlines ■ Reference Designs Comply with CENELEC EN50065-1:2001 and FCC Part 15 The Powerline Network Layer residing on the CY8CPLC10 receives these I2C messages and generates a Powerline Transceiver (PLT) packet. These packets are modulated by the FSK Modem and coupled with Powerline by the external coupling circuit. Frequencies of 50, 100, and 400 kHz Powerline Receiver Powerline signals are received by the coupling circuit and demodulated by the FSK Modem PHY to reconstruct PLT packets. These PLT packets are decoded by the Powerline Network Protocol and then transferred to the external host microcontroller in an I2C format. Applications ■ Residential and Commercial Lighting Control ■ Home Automation ■ Automatic Meter Reading ■ Industrial Control and Signage ■ Smart Energy Management Logic Block Diagram Host System Powerline Network Protocol 2 I C Packet Powerline FSK Modem PHY Application Circuitry CY8CPLC10 PSoC/ External μC Powerline Communication Solution AC/DC Powerline Coupling Circuit (110V-240V AC, 12V-24V AC/DC, etc.) Powerline Cypress Semiconductor Corporation Document Number: 001-50001 Rev. *M • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 21, 2015 CY8CPLC10 Datasheet Contents Robust Communication using Cypress’s PLC Solution ........................................ 3 Detailed Description ......................................................... 3 Powerline Modem PHY ............................................... 3 Powerline Network Protocol ........................................ 4 CY8CPLC10 Memory Map .......................................... 6 External Host Application .......................................... 12 Target Applications ........................................................ 14 Lighting Control ......................................................... 14 Smart Energy Management ...................................... 15 Automatic Meter Reading .......................................... 16 Industrial Signage ...................................................... 17 Pinouts ............................................................................ 18 Pin Definitions ................................................................ 18 Electrical Specifications ................................................ 20 Absolute Maximum Ratings ....................................... 20 Operating Temperature ............................................. 20 DC Electrical Characteristics ..................................... 21 AC Electrical Characteristics ..................................... 22 Packaging Information ................................................... 24 Thermal Impedances ................................................. 24 Capacitance on Crystal Pins ..................................... 24 Document Number: 001-50001 Rev. *M Solder Reflow Peak Temperature ............................. 24 Development Tool Selection ......................................... 25 Development Kits ...................................................... 25 Evaluation Kits ........................................................... 25 Device Programmers ................................................. 25 Ordering Information ...................................................... 26 Ordering Code Definitions ......................................... 26 Acronyms ........................................................................ 27 Acronyms Used ......................................................... 27 Reference Documents .................................................... 27 Document Conventions ............................................. 27 Units of Measure ....................................................... 27 Numeric Conventions ................................................ 27 Glossary .......................................................................... 28 Document History Page ................................................. 33 Sales, Solutions, and Legal Information ...................... 35 Worldwide Sales and Design Support ....................... 35 Products .................................................................... 35 PSoC® Solutions ...................................................... 35 Cypress Developer Community ................................. 35 Technical Support ..................................................... 35 Page 2 of 35 CY8CPLC10 Datasheet Robust Communication using Cypress’s PLC Solution Powerline Modem PHY Figure 2. CY8CPLC10: FSK Modem PHY Powerlines are one of the most widely available communication mediums for PLC technology. The pervasiveness of Powerlines also makes it difficult to predict the characteristics and operation of PLC products. Because of the variable quality of Powerline around the world, implementing robust communication over Powerline is an engineering challenge. Keeping this in mind, Cypress's PLC solution has been designed to enable secure and reliable communication over Powerlines. Cypress PLC features that enable robust communication over Powerline include: ■ ■ ■ Powerline Network Protocol I2C Packet Integrated Powerline PHY modem with optimized filters and amplifiers to work with lossy high voltage and low voltage Powerlines. Powerline optimized Network Protocol that supports bidirectional communication with acknowledgement based signaling. In case of data packet loss due to bursty noise on the Powerline, the transmitter can retransmit data. The Powerline Network Protocol also supports 8-bit CRC for error detection and data packet retransmission. A Carrier Sense Multiple Access (CSMA) scheme, built into the Network Protocol, minimizes collisions between packet transmissions on the Powerline. This provides support for multiple masters and reliable communication on a bigger network. Powerline FSK Modem PHY CY8CPLC10 ■ Powerline Communication Solution The physical layer of Cypress’s PLC solution is implemented using an FSK modem that enables half duplex communication on a Powerline. This modem supports data rates up to 2400 bps. Figure 3. CY8CPLC10: FSK Modem PHY Block Diagram Detailed Description Network Protocol Figure 1. CY8CPLC10 Internal Block Diagram HOST _INT TX_ RX_ LED LED BIU_ LED External 32.768 kHz Crystal (XTAL_IN, XTAL_OUT) External 24 MHz Clock Oscillator (EXTCLK) Digital Receiver Digital Transmitter Hysteresis Comparator Protocol Timer I2C_SCL I2C_SDA TX Buffer I2C Interface Memory Array FSK Modulator FSK_OUT Processor FSK Modem Clock RX Buffer FSK De-Modulator FSK_IN EEPROM I2C_ADDR LOG_ADDR[2:0] The CY8CPLC10 consists of two main functional components: ■ ■ Powerline Modem PHY Powerline Network Protocol Local Oscillator Logic ‘1’ or Logic ‘0’ Low Pass Filter Modulator External Low Pass Filter Correlator Square Wave at FSK Frequencies IF Band Pass Filter Local Oscillator Mixer Programmable Gain Amplifier Receiver FSK Modem Clock Transmitter CLKSEL Status and interrupt signals Powerline Modem PHY PLL HF Band Pass Filter RX Amplifier Coupling Circuit The user application resides on a host system such as PSoC®, EZ-Color™, or any other microcontroller. The messages generated by the application are communicated to the CY8CPLC10 over I2C and processed by these functional components. The following sections present a brief description of each of these components. Document Number: 001-50001 Rev. *M Page 3 of 35 CY8CPLC10 Datasheet Transmitter Section Powerline Network Protocol Digital data from the network layer is serialized by the digital transmitter and fed as input to the modulator. The modulator divides the local oscillator frequency by a definite factor depending on whether the input data is high level logic ‘1’ or low level logic ‘0’. It then generates a sine wave at 133.3 kHz (Logic ‘0’) or 131.8 kHz (Logic ‘1’), which is fed to the Programmable Gain Amplifier to generate FSK modulated signals. The logic ‘1’ frequency can also be configured as 130.4 kHz for wider FSK bandwidth. Cypress’s Powerline optimized Network Protocol performs the functions of the data link, network, and transport layers in an ISO/OSI Equivalent Model. Figure 4. CY8CPLC10: Powerline Network Protocol Powerline Communication Solution The incoming FSK signal from the Powerline is input to a High Frequency (HF) Band Pass Filter that filters out-of-band frequency components and outputs filtered signal within the desired spectrum of 125 kHz to 140 kHz for further demodulation. The Mixer block multiplies the filtered FSK signals with a locally generated signal to produce heterodyned frequencies. The Intermediate Frequency (IF) Band Pass Filters further remove out-of-band noise as required for further demodulation. This signal is fed to the correlator which produces a DC component (consisting of Logic ‘1’ and ‘0’) and a higher frequency component. The output of the correlator is fed to an external Low Pass filter with a cut-off frequency of 7.5 KHz. The signal is then fed to the internal Low Pass FIlter (LPF) that outputs only the demodulated digital data at 2400 baud and suppresses all other higher frequency components generated in the correlation process. The output of the LPF is digitized by the hysteresis comparator. This eliminates the effects of correlator delay and false logic triggers due to noise. The Digital Receiver deserializes this data and outputs to the Network Layer for interpretation. Coupling Circuit Reference Design The coupling circuit couples low voltage signals from CY8CPLC10 to the Powerline. The topology of this circuit is determined by the voltage on the Powerline and design constraints mandated by Powerline usage regulations. Cypress provides reference designs for a range of Powerline voltages such as 110V AC, 240V AC, 12V DC, 12V AC, 24V DC, and 24V AC. The CY8CPLC10 is capable of data communication over other AC/DC Powerlines as well with the appropriate external coupling circuit. The 110V AC and 240V AC designs are compliant to the following Powerline usage regulations: ■ FCC part 15 for North America ■ EN50065-1:2001 Document Number: 001-50001 Rev. *M Powerline Network Protocol Powerline FSK Modem PHY CY8CPLC10 I2C Packet Receiver Section The Network Protocol implemented on the CY8CPLC10 chip supports the following features: ■ Bidirectional half-duplex communication ■ Master and slave as well as peer-to-peer network of Powerline nodes ■ Multiple masters on Powerline network ■ 8-bit logical addressing supports up to 256 Powerline nodes ■ 16-bit extended logical addressing supports up to 65536 Powerline nodes ■ 64-bit physical addressing supports up to 264 Powerline nodes ■ Individual broadcast or group mode addressing ■ Carrier Sense Multiple Access (CSMA) ■ Full control over transmission parameters ❐ Acknowledged ❐ Unacknowledged ❐ Repeated transmit ❐ Sequence numbering CSMA and Timing Parameters ■ CSMA: The protocol provides the random selection of a period between 85 and 115 ms (out of seven possible values in this range) in which the band in use detector must indicate that the line is not in use, before attempting a transmission. After completing a transmission when band-in-use is enabled for the system, the application should wait 125 ms before the next transmission. Page 4 of 35 CY8CPLC10 Datasheet ■ Band-In-Use (BIU): A Band-In-Use detector, as defined under CENELEC EN 50065-1, is active whenever a signal that exceeds 86 dBuVrms in the range 131.5 KHz to 133.5 KHz is present for at least 4 ms. This threshold can be configured for different end-system applications not requiring CENELEC compliance.The modem tries to retransmit after every 85 to 115 ms when the Band is in use. The Transmitter times out after 1.1 seconds to 3 seconds (depending on the noise on the Powerline) and generates an interrupt to indicate that the transmitter was unable to acquire the Powerline. Powerline Transceiver Packet The Powerline Network Protocol defines a Powerline Transceiver (PLT) packet structure, which is used for data transfer between nodes across the Powerline. Packet formation and data transmission across the Powerline network is implemented internally in CY8CPLC10. A PLT Packet is apportioned into a variable length header (minimum 6 bytes to maximum 20 bytes, depending on address type), a variable length payload (minimum 0 bytes to maximum 31 bytes), and a packet CRC byte. This packet (preceded by a one byte preamble “0xAB”) is then transmitted by the Powerline Modem PHY and the external coupling circuit across the Powerline. The format of the PLT packet is shown in Table 1. 6 5 4 3 2 0 SA DA Type Service Type Type 0x01 Destination Address (8-bit Logical, 16-bit Extended Logical or 64-bit Physical) 0x02 Source Address (8-bit Logical, 16-bit Extended Logical or 64-bit Physical) 0x04 RSVD 1 0x00 0x03 Response RSVD Command RSVD 0x05 0x06 Payload Length Seq Num No. of Bits Tag Description SA Type 1 Source 0 - Logical Addressing Address Type 1- Physical Addressing DA Type 2 Destination 00 - Logical Addressing Address Type 01 - Group Addressing 10 - Physical Addressing 11 - Invalid Service Type 1 Response 1 Response 0 - Not an acknowledgement or response packet 1 - Acknowledgement or response packet Seq Num 4 Sequence Number Four bit Unique Identifier for each packet between source and destination Header CRC 4 0 - Unacknowledged Messaging 1 - Acknowledged Messaging Four bit CRC Value. This enables the receiver to suspend receiving the rest of the packet if its header is corrupted Payload Packet CRC Bit Offset 7 Field Name The packet payload has a length of 0 to 31 bytes. Payload content is user defined and can be read or written through I2C. Table 1. Powerline Transceiver (PLT) Packet Structure Byte Offset Table 2. Powerline Transceiver (PLT) Packet Header Powerline Packet Header CRC Payload (0 to 31 Bytes) The last byte of the packet is an 8-Bit CRC value used to check packet data integrity. This CRC calculation includes the header and payload portions of the packet and is in addition to the Powerline Packet Header CRC. Sequence Numbering The sequence number is increased for every new unique packet transmitted. If in acknowledged mode and an acknowledgment is not received for a given packet, that packet is re-transmitted (if TX_Retry > 0) with the same sequence number. If in unacknowledged mode, the packet is transmitted (TX_Retry + 1) times with the same sequence number. If the receiver receives consecutive packets from the same source address with the same sequence number and packet CRC, it does not notify the host of the duplicate packet reception. If in acknowledged mode, it still sends an acknowledgment so that the transmitter knows that the packet was received. Addressing Powerline Transceiver Packet CRC Packet Header The Packet Header comprises the first six bytes of the packet when 1-byte logical addressing is used. When 8-byte physical addressing is used, the source and destination addresses each contain eight bytes. In this case, the header can consist of a maximum of 20 bytes. Unused fields marked RSVD are for future expansion and are transmitted as bit 0. Table 2 describes the PLT Packet Header fields in detail. Document Number: 001-50001 Rev. *M The logical address of the PLC node is set through software by the external host controller or by a remote node on the Powerline. The logical address can also be set through hardware with the 3-bit LOG_ADDR (Logical Address) Port (for example, an on-board 3-bit DIP switch). However, it is overwritten when set in software. Every CY8CPLC10 chip also has a unique 64-bit physical address which can be used for assigning the logical addresses. Page 5 of 35 CY8CPLC10 Datasheet Both these modes can also be used together for Group membership. For example, a single PLC node can be a part of Group 131 and also multiple groups such as Group 3, Group 4, and Group 7. All the address pins are logically inverted, that is, applying a high voltage on these pins corresponds to writing a logic ‘0’ and vice versa. Group Membership The Group membership ID for broadcasting messages to all nodes in the network is 0x00. Group Membership enables the user to multicast messages to select groups. The CY8CPLC10 supports two types of group addressing. ■ ■ The Service Type is always set to Unacknowledgment Mode in Group Addressing Mode. This is to avoid Acknowledgment flooding on the Powerline during multicast. Single Group Membership: The Network protocol supports up to 256 different groups on the network in this mode. In this mode, each PLC node can only be part of a single group. For example, multiple PLC nodes can be part of Group 131. CY8CPLC10 Memory Map Table 3 gives the detailed CY8CPLC10 memory location information. This information can be used for application development on an external host controller. Several PLC Commands are instantiated from the Powerline Network Protocol based on which memory location is written. Multiple Group Membership: The Network protocol supports eight different groups in this mode and each PLC node can be a part of multiple groups. For example, a single PLC node can be a part of Group 3, Group 4, and Group 7at the same time. Table 3. CY8CPLC10 Memory Map Offset Register Name Access 7 6 5 4 INT_Clear INT_Polarity INT_UnableTo TX INT_TX_ NO_ACK 3 2 INT_TX_ INT_RX_ NO_RESP Packet_ Dropped 1 0 INT_RX_ Data_ Available INT_TX_ Data_ Sent 0x00 INT_Enable RW 0x01 Local_LA_LSB RW 8 - bit Logical Address/LSB for extended 16-bit address 0x02 Local_LA_MSB RW MSB for extended 16-bit address 0x03 Local_Group RW 8-bit Group Address 0x04 Local_Group_ Hot RW One Hot Encoded (e.g. if byte = 0b00010001, then member of groups #5 and #1) 0x05 PLC_Mode RW 0x06 TX_Message_ Length RW Send_ Message Reserved 0x07 TX_Config RW TX_SA_ Type TX_DA_Type 0x08 TX_DA RW 0x10 TX_CommandID RW 0x11 TX_Data 0x30 Threshold_Noise RW Reserved 0x31 Modem_Config RW Reserved 0x32 TX_Gain RW 0x33 RX_Gain RW 0x34-0x3F Reserved RW 0x40 RX_Message_ INFO R 0x41 RX_SA R 0x49 RX CommandID R TX_Enable RX_Enable Lock_ Configuration Disable_ BIU Rx_ Overwrite Set_Ext_ Promiscuous Promiscuous Address _MASK _CRC_MAS K Payload_Length_MASK TX_Service _Type TX_Retry Remote Node Destination Address (8 bytes) TX Command ID RW TX Data (31 bytes) Auto_BIU_ Threshold Reserved TX_Delay Reserved BIU_Threshold_Constant Modem_F Reserve SKBW_MA d SK Reserved Modem_BPS_MASK TX_Gain Reserved RX_Gain Reserved New_RX_ Msg RX_DA_ Type RX_SA_ Type RX_Msg_Length Remote Node Source Address (8 Bytes) RX Command ID 0x4a RX_Data R 0x69 INT_Status R RX Data (31 bytes) 0x6A Local_PA R Physical Address (8 bytes), "0x6A -> MSB" 0x72 Local_FW R Version Number Status_Valu e_Change Document Number: 001-50001 Rev. *M Reserved Status_BUSY Status_TX_ Status_TX Status_ Status_RX_ Status_TX_D NO_ACK _ RX_Pack Data_Availab ata_ NO_RESP et_Dropp le Sent ed Page 6 of 35 CY8CPLC10 Datasheet Table 4 gives the description of the various fields outlined in Table 3 on page 6 [1]. Table 4. Memory Field Description Field Name INT_Clear INT_Polarity INT_UnableToTX INT_TX_NO_ACK INT_TX_NO_RESP INT_RX_Packet_Dropped INT_RX_Data_Available INT_TX_Data_Sent TX_Enable RX_Enable Lock_Configuration Disable_BIU RX_Overwrite Set_Ext_Address Promiscuous_MASK Promiscuous_CRC_MASK Send_Message Payload_Length_MASK No. of Bits Description INT_Enable Register (0x00) for the HOST_INT pin 1 0 - INT Cleared (W) 1 - INT Triggered (Set Internally) Note: The user should set this bit to Logic 0 after reading the INT_Status register. This clears the INT_Status register, except for Status_RX_Packet_Dropped and Status_RX_Data_Available. 1 0 - Active High 1 - Active Low 1 Enable Interrupt for BIU Timeout and the Modem is unable to Transmit if Disable BIU = 0 1 Enable Interrupt for no acknowledgment received if Service Type = 1 (Ack Mode) 1 Enable Interrupt for No Response Received 1 Enable Interrupt when RX Packet is dropped because RX Buffer is full. Note: If there is a prior status change that hasn't been cleared (Status_Value_Change = '1') when an RX Packet is dropped, the HOST_INT pin will be asserted regardless of the value of this bit. 1 Enable Interrupt when RX buffer has new data. Note: If there is a prior status change that hasn't been cleared (Status_Value_Change = '1') when a new message is received, the HOST_INT pin will be asserted regardless of the value of this bit. 1 Enable Interrupt when TX data is sent successfully PLC_Mode Register (0x05) 1 0 - TX Disabled (Can send ACKs only) 1 - TX Enabled 1 0 - RX Disabled (Can Receive ACKs only) 1 - RX Enabled 1 0 - Allow Remote Access to change config (TX Enable, Ext Address, Disable BIU, Threshold Value, Logical Address, Group Membership) 1 - Lock Remote Access to change config 1 0 - Enables Band-In-Use 1 - Disables Band-In-Use 1 0 - If RX Buffer is full, new RX Message is dropped 1 - If RX Buffer is full, new RX Message overwrites RX Buffer 1 0 - 8-bit Addressing Mode 1 - Extended 16-bit Addressing Mode Note: This mode should be the same in all the devices in the network 1 0 - Drops the RX Message if Destination Address does not match the Local Address 1- Ignores Destination Address match and accepts all CRC-verified RX Messages 1 0 - Drops the RX Message if the 8-bit packet CRC fails 1- Ignores the 8-bit packet CRC and accepts all RX Messages if Destination Address matches Local Address TX_Message_Length Register (0x06) 1 0 - Transmitter is idle. Automatically cleared after each Transmit 1 - Triggers the Transmit to send message in TX Data across Powerline Note: The registers TX Config, TX Destination Address, TX Command ID and TX Data need to be set before the user sets this bit to Logic 1 5 5-bit value for variable payload length. The payload length can vary from 0 to 31. Note 1. To ensure that the receiver has sufficient time to start up and read the first byte, the transmit delay parameter (Modem_TXDelay) should be set to >= 18 ms for 600 bps and >= 12 ms for 1200 bps. For 1800 bps and 2400 bps, the delay can be set to any value. Document Number: 001-50001 Rev. *M Page 7 of 35 CY8CPLC10 Datasheet Table 4. Memory Field Description (continued) Field Name No. of Bits TX_SA_Type 1 TX_DA_Type 2 TX_Service_Type 1 TX_Retry 4 8-bit Logical Address 16-bit Logical Address 64-bit Physical Address Auto_BIU_Threshold 1 BIU_Threshold_Constant 3 TX_Delay 2 Modem_FSK_BW_MASK 1 Modem_BPS_MASK 2 Document Number: 001-50001 Rev. *M Description TX_Config Register(0x07.) 0 - Logical Address 1 - Physical Address 00 - Logical Address 01 - Group Address 10 - Physical Address 11 - Invalid 0 - Unacknowledgement mode 1 - Acknowledgement Mode 4-bit value for variable TX Retry Count TX_DA Register (0x08 - 0x0F) 0x08 0x08 - LSB 0x09 - MSB 0x08 - MSB | 0x0F - LSB Threshold_Noise Register (0x30) 0 - Auto Set Threshold is disabled 1 - Auto Set Threshold is enabled. This state overrides the Threshold Values in Register 0x30. 000 - 70 dBuVrms 001 - 75 dBuVrms 010 - 80 dBuVrms 011 - 87 dBuVrms (default) 100 - 90 dBuVrms 101 - 93 dBuVrms 110 - 96 dBuVrms 111 - 99 dBuVrms Modem_Config Register (0x31) 00 - 7 ms 01 - 13 ms 10 - 19 ms 11 - 25 ms 0 - Logic '0' - 133.3 kHz Logic '1' - 131.8 kHz 1 - Logic '0' - 133.3 kHz Logic '1' - 130.4 kHz 00 - 600 bps[1] 01 - 1200 bp[1] 10 - 1800 bps 11 - 2400 bps (default) Page 8 of 35 CY8CPLC10 Datasheet Table 4. Memory Field Description (continued) Field Name No. of Bits TX_Gain 4 RX_Gain 3 New_RX_Msg 1 RX_DA_Type 1 RX_SA_Type 1 RX_Msg_Length 5 8-bit Logical Address 16-bit Logical Address 64-bit Physical Address Description TX_Gain Register (0x32) The following values are the output AC voltage swing for the given settings: 0000 - 55 mVp-p 0001 - 75 mVp-p 0010 - 100 mVp-p 0011 - 125 mVp-p 0100 - 180 mVp-p 0101 - 250 mVp-p 0110 - 360 mVp-p 0111 - 480 mVp-p 1000 - 660 mVp-p 1001 - 900 mVp-p 1010 - 1.25 Vp-p 1011 - 1.55 Vp-p (default) 1100 - 2.25 Vp-p 1101 - 3.00 Vp-p 1110 - 3.50 Vp-p 1111 - Reserved RX_Gain Register (0x33) The following values are the minimum RX input sensitivity for the given settings: 000 - 5 mVrms (default) 001 - 5 mVrms 010 - 2.5 mVrms 011 - 1.25 mVrms 100 - 600 Vrms 101 - 350 Vrms 110 - 250 Vrms 111 - 125 Vrms RX_Message_INFO Register (0x40) 0 - No Packet received 1 - New Packet received Note: User sets this bit to Logic 0 after reading the RX Message. This allows the device to receive a new RX message. This also clears the Status_Value_Change, Status_RX_Packet_Dropped, and Status_RX_Data_Available bits in the INT_Status register. 0 - Logical / Physical Addressing 1 - Group Addressing 0 - Logical Address 1 - Physical Address 5-bit value for variable payload length. The payload length can vary from 0 to 31. RX_SA Register (0x41 - 0x48) 0x41 0x41 - LSB 0x42 - MSB 0x41 - MSB | 0x48 - LSB INT_Status Register (0x69) Note: When the user sets INT_Clear to Logic 0, every bit in this register (except Status_RX_Packet_Dropped and Status_RX_Data_Available) will be cleared to Logic 0. When the user sets New_RX_MSG, the Status_Value_Change, Status_RX_Packet_Dropped and Status_RX_Data_Available bits will be cleared to Logic 0. Status_Value_Change 1 0 - No Change 1 - Change Document Number: 001-50001 Rev. *M Page 9 of 35 CY8CPLC10 Datasheet Table 4. Memory Field Description (continued) Field Name Status_BUSY Status_TX_NO_ACK Status_TX_NO_RESP Status_RX_Packet_Dropped Status_RX_Data_Available Status_TX_Data_Sent No. of Bits Description 1 0 - No BIU Timeout 1 - BIU Timeout or transmission is attempted when TX_Enable = 0 1 If Service Type = 1 (ACK Mode) 0 - ACK Received (when TX Data sent = 1) 1 - No ACK received (when TX Data sent = 0) Note: The timeout window for receiving the ACK is 500ms 1 0 - Response Received (when TX Data sent = 1) 1 - No Response Received (when TX Data sent = 0) Note:The timeout window for receiving Responses is 1.5s 1 If RX Overwrite = 0 0 - No RX Packet is dropped 1- RX Packet is dropped because RX Buffer is full 1 0 - No new data available in RX buffer 1- RX buffer has new data available 1 0 - No TX data sent 1- TX data sent successfully Baud rate Sets the baud rate for the Powerline Communication PHY. You can configure the baud rate to 600, 1200, 1800, or 2400 bits per second. To ensure that the receiver has sufficient time to start up and read the first byte, the transmit delay parameter (Modem_TXDelay) should be set to > 19 ms for 600 bps and > 13 ms for 1200 bps. For 1800 bps and 2400 bps, the delay can be set to any value. TX Gain Sets the gain of the transmitter’s programmable gain amplifier. RX Gain Sets the gain of the receiver’s programmable gain amplifier. This in turn determines the minimum input sensitivity for the receiver. Noise Level Threshold Sets the Noise Level Threshold for Brand In Use (BIU) detection. FSK Bandwidth Sets the separation of the FSK signals representing logic ‘1’ and logic ‘0’. Can either be set to a deviation of ~1.5 kHz or ~3 kHz. The logic ‘0’ frequency is always 133.3 kHz. The logic ‘1’ frequency can be configured to either 131.8 kHz or 130.4 kHz. This parameter is sometimes referred to as FSK Deviation. Modem_TXDelay Sets the amount of delay from when the transmission is initiated to when the data starts being output from the Transmit Programmable Gain Amplifier. This gives the external circuitry time to set up. The TX_Shutdown signal (Port2[7]) is set before the delay. BIU Timeout Sets the condition for timing out the BIU detector. It can be either on the first BIU detection of a signal or if the BIU detector can't acquire the line after 1.1 seconds. (This value can be up to 3.5s depending on the amount of noise on the line). ACK Timeout Sets the amount of time that the device will wait for an acknowledgment after it completes the transmission of a packet. This only applies when the Service Type is acknowledgment mode. The time can be a fixed 500ms, or can be based on the expected time to receive the acknowledgment packet plus a buffer. For example, the “Auto + 20ms” property will set the timeout to be 20 ms longer than the time it would normally take to receive the acknowledgement. This gives the receiver extra time to perform other functions in between checking for a received message. The calculation is based on the length of the acknowledgment packet, the baud rate, and the Modem_TXDelay. Addressing Mode Sets the logical addressing length to 8-bit or 16-bit. Logical Address of Node Set the logical address for the Powerline node. The available addresses vary depending on whether 8-bit or 16-bit addressing is used. Document Number: 001-50001 Rev. *M Page 10 of 35 CY8CPLC10 Datasheet Transmit Enable Enables Transmit Mode operation. When transmit mode is disabled, no new messages are transmitted. Acknowledgments are transmitted, regardless of Transmit Enable. Transmit Source Address Type Sets the Transmit SA Type. Choose Logical Address or Physical Address. You cannot change this parameter if Transmit Enable is set to Disable. Transmit Destination Address Type Sets the Transmit DA Type. Choose from Logical Address, Group Address, and Physical Address. This parameter is not editable if the Transmit Enable option is set to Disable. Transmit Service Type Sets the Transmit Acknowledgment Mode. Transmissions are acknowledged in acknowledgement mode. This parameter is not editable if the Transmit Enable option is set to Disable. Transmit Retry Count Sets the transmitter retry count. In Acknowledgment mode, sets the maximum transmit retries if no acknowledgment is received. In Unacknowledgment mode, sets how many times the transmitter retransmits the same packet. This parameter is not editable if the Transmit Enable option is set to Disable. Transmit Payload Length Sets the Payload Length from 0 to 31 bytes. This parameter is not editable if the Transmit Enable option is set to Disable. Receive Enable Enables Receive Mode. When receive mode is disabled, no new messages are accepted. Lock Configuration Allows remote access to change the configuration. Rx Overwrite Enables receive buffer overwrite mode. When enabled, newly received messages overwrite the Rx Buffer when it contains an unread packet. When disabled and the Rx Buffer contains an unread packet, the newly received message is dropped. To clear the RX buffer, the New_RX_Msg must be set to ‘0’. Destination Address Verification Allows the receiver to ignore destination address verification. When the setting is Do Not Ignore the received packet is dropped if it does not match the local address. When set to Ignore, the received packet is accepted regardless of the local address. CRC Messages Verification Allows the receiver to ignore cyclic redundancy check message verification. When the setting is Do Not Ignore the packet is dropped if the 8-bit packet CRC fails. Single Group Membership ID Sets the group number when the network is placed in ‘single group membership’ mode. Multiple Group Membership ID Sets the group number when network is placed in ‘multiple group membership’ mode. This parameter is an 8-bit value and is expressed in binary. Each instance of 1 in the number indicates that the group is member of the group corresponding to the binary position of the number. For example, if the value is 01000001, then the particular node is part of the 1st and 7th group. I2C Slave Address Can be any value from 0x01 to 0x7F. Document Number: 001-50001 Rev. *M Page 11 of 35 CY8CPLC10 Datasheet External Host Application The application residing on the external host microcontroller has direct access to the local PLC memory over I2C. The I2C communication enables the host controller to instantiate several PLC functions by reading or writing to the appropriate memory locations in the PLC chip. Thus the host application can configure the CY8CPLC10, read status and configuration information, and transmit data to remote Powerline nodes. Refer to the CY8CPLC10 application note (AN52478 at http://www.cypress.com) on how to build a PLC command set using the CY8CPLC10 memory map. The device has a dedicated pin (I2C_ADDR) for selecting the I2C slave address while communicating with the external controller. The two I2C slave addresses available are 0x01 and 0x7A. Remote Commands In addition to sending normal data over the Powerline, the CY8CPLC10 can also send (and request) control information to (and from) another node on the network. The type of remote command to transmit is set by the TX_CommandID register and when received, is stored in the RX_CommandID register. When a control command (Command ID = 0x01 - 0x08 and 0x0C - 0x0F) is received, the protocol automatically processes the packet (if Lock_Configuration is '0'), responds to the initiator, and notifies the host of the successful transmission and reception. the acknowledgment packet within 500 ms, it notifies the host of the ‘no acknowledgment received’ condition. When a response command (ID 0x0B) is received by the initiator within 1.5s of sending the request for data command, the protocol notifies the host of the successful transmission and reception. If the response command is not received by the initiator within 1.5s, it notifies the host of the no response received condition. The host is notified by updating the appropriate values in the INT_Status register (including Status_Value_Change) and asserting the HOST_INT pin (if the corresponding bit is set in the INT_Enable register). The command IDs 0x30-0xff can be used for custom commands that will be processed by the external host (for example, set an LED color, get a temperature/voltage reading). The available remote commands are described in Table 5 with the respective Command IDs. EEPROM Back Up for Remote Reset The device also has an EEPROM to back up Memory Registers 0x00-0x05 and 0x30-0x33. When the device is reset remotely by the SetRemote_Reset command (described in Table 5), it clears its memory map and loads from the EEPROM and returns to idle mode. When the send data command (ID 0x09) or request for data command (ID 0x0A) is received, the protocol replies with an acknowledgment packet (if TX_Service_Type = '1'), and notifies the host of the new received data. If the initiator does not receive Table 5. Remote Commands Cmd ID Command Name Description Payload (TX Data) Response (RX Data) 0x01 SetRemote_TXEnable Sets the TX Enable bit in the 0 - Disable Remote TX PLC Mode Register. Rest of the 1 - Enable Remote TX PLC Mode register is unaffected If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) 0x02 SetRemote_Reset Reset the Remote Node Configuration None If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) 0x03 SetRemote_ExtendedAddr Set the Addressing to Extended Addressing Mode 0 - Disable Extended Addressing 1 - Enable Extended Addressing If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) 0x04 SetRemote_LogicalAddr Assigns the specified logical address to the remote PLC node If Ext Address = 0, Payload = 8-bit Logical Address If Ext Address = 1, Payload = 16-bit Logical Address If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) 0x05 GetRemote_LogicalAddr Get the Logical Address of the None remote PLC node Document Number: 001-50001 Rev. *M If Remote TX Enable = 0, Response = None If Remote TX Enable = 1, {If Ext Address = 0, Response = 8-bit Logical Address If Ext Address = 1, Response = 16-bit Logical Address} Page 12 of 35 CY8CPLC10 Datasheet Table 5. Remote Commands (continued) Cmd ID Command Name Description Payload (TX Data) Response (RX Data) 0x06 GetRemote_PhysicalAddr Get the Physical Address of the None remote PLC node If Remote TX Enable = 0, Response = None If Remote TX Enable = 1, Response = 64-bit Physical Address 0x07 GetRemote_State Request PLC_Mode Register content from a Remote PLC node If Remote TX Enable = 0, Response = None If Remote TX Enable = 1, Response = Remote PLC Mode register 0x08 GetRemote_Version Get the Version Number of the None Remote Node If TX Enable = 0, Response = None If TX Enable = 1, Response = Remote Version register 0x09 SendRemote_Data Transmit data to a Remote Node. Payload = Local TX Data If Local Service Type = 0, Response = None If Local Service Type = 1, Response = Ack 0x0A RequestRemote_Data Request data from a Remote Node Payload = Local TX Data If Local Service Type = 1, Response = Ack Then, the remote node host must send a ResponseRemote_Data command. The response must be completely transmitted within 1.5s of receiving the request. Otherwise, the requesting node will time out. 0x0B ResponseRemote_Data Transmit response data to a Remote Node. Payload = Local TX Data None 0x0C SetRemote_BIU Enables/Disables BIU function- 0 - Enable Remote BIU If Remote Lock Config = 0, ality at the remote node 1 - Disable Remote BIU Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) 0x0D SetRemote_ThresholdValue Sets the Threshold Value at the 3-bit Remote Remote node Threshold Value 0x0E SetRemote_GroupMembership Sets the Group Membership of Byte0 - Remote SIngle the Remote node Group Membership Address Byte1- Remote Multiple Group Membership Address If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) 0x0F GetRemote_GroupMembership Gets the Group Membership of None the Remote node If Remote TX Enable = 0, Response = None If Remote TX Enable = 1, Response = Byte0 - Remote SIngle Group Membership Address Byte1- Remote Multiple Group Membership Address 0x10 0x2F Reserved 0x30 0xFF User Defined Command Set Document Number: 001-50001 Rev. *M None If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) Page 13 of 35 CY8CPLC10 Datasheet Target Applications Lighting Control CY8CPLC10 enables control of incandescent, sodium vapor, fluorescent, and LED lighting fixtures over existing Powerlines. Cypress’s Powerline communication solution easily integrates with wall-switch dimmers and lamp and appliance modules, enabling on and off, dimming, color mixing, and tunable white light control. The CY8CPLC10 can control individual or a group of lighting fixtures in a home or a commercial building. Elaborate lighting scenes can be created using application software. Household lighting fixtures can also be programmed to turn on and off at user defined intervals using a PC based Graphical User Interface. Figure 5. Powerline Communication for Home Lighting Figure 6. Powerline Communication for Pool Lighting Document Number: 001-50001 Rev. *M Page 14 of 35 CY8CPLC10 Datasheet Smart Energy Management Using the CY8CPLC10, individual panels in a solar array can transmit diagnostic data over the existing DC powerlines. An Array Diagnostic Unit Controller can communicate with individual solar panels to probe specific diagnostic information. When the diagnostic data is collected by the controller, it is transmitted across the Powerline to a data monitoring console. This makes it possible to acquire and transmit real time data regarding energy output of individual panels to the array controller and subsequently even to a solar farm control station over the Powerline. Figure 7. Powerline Communication for Smart Energy Management (Solar Diagnostics) Document Number: 001-50001 Rev. *M Page 15 of 35 CY8CPLC10 Datasheet Automatic Meter Reading The CY8CPLC10 can be designed in electric meters in household and industrial environments to transmit power usage information to a centralized billing system. The Cypress Powerline communication solution is ideally suited to handle multiple data sources because of the in-built Network Protocol Stack that enables individual addressing of multiple nodes on the same Powerline. In physical addressing mode, up to 264 power meters can transmit usage statistics to the local billing center. Application Layer software can be used to provide real time usage statistics to a customer. Energy utilities can improve customer service and control meter reading costs, especially in areas where accessing meters is difficult or unsafe, while making the invoicing process more efficient. Figure 8. Powerline Communication for Automatic Meter Reading Document Number: 001-50001 Rev. *M Page 16 of 35 CY8CPLC10 Datasheet Industrial Signage An entire array of new convenience and advanced control features are available in automobiles today. It is projected that a high feature content car cannot have enough space to contain multiple wiring segments and connectors without compromising power loss and safety. One solution is to reduce the number of cables by using existing Powerline as the transmission medium of digital control signals. The CY8CPLC10 enables control of Automotive LED strobe, beacon, tail lights, and indicators over the existing direct current (DC) 12V to 42V battery Powerline. Combined with Cypress’s EZ-Color lighting solution, dimming and color mixing of LED based automotive lighting fixtures in applications such as mobile LED displays is possible. Figure 9. Powerline Communication for Industrial Signage Document Number: 001-50001 Rev. *M Page 17 of 35 CY8CPLC10 Datasheet Pinouts Figure 10. CY8CPLC10 28-pin SSOP RX_LED RSVD FSK_ OUT CLKSEL TX_ SHUTDOWN LOG_ ADDR_0 LOG_ ADDR_1 LOG_ ADDR_2 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 RSVD I2C_SCL 9 20 10 19 I2C_ SDA XTAL_ STABLITY 11 18 12 17 13 16 14 15 XTAL_IN VSS VDD FSK_IN I2C_ ADDR RSVD RSVD HOST_INT AGND RXCOMP_IN RXCOMP_ OUT RESET BIU_LED EXTCLK TX_LED XTAL_ OUT Pin Definitions Pin Number Pin Name I/O Description 1 RX_LED Output RX Indicator LED 2 RSVD Reserved Reserved Pin[2] 3 FSK_OUT Analog Output Analog FSK Output. This signal is coupled to the powerline through an external coupling circuit 4 CLKSEL Input (Internal Pull up) FSK Modem Clock Source Select Logic ‘0’ – External Clock Oscillator (EXTCLK) selected Logic ‘1’ – External Crystal (XTAL_IN, XTAL_OUT) selected Note: The external crystal (XTAL_IN, XTAL_OUT) is always required for the protocol timing. 5 TX_SHUTDOWN Output 6 LOG_ADDR_0 Input (Internal Pull up) Connected to the Least Significant Bit of the 3-bit Logical Address. This is an inverted pin; applying a high voltage on this pin corresponds to writing a logic ‘0’ and vice versa. 7 LOG_ADDR_1 Input (Internal Pull up) Connected to the 2nd Most Significant Bit of the 3-bit Logical Address. This is an inverted pin; applying a high voltage on this pin corresponds to writing a logic ‘0’ and vice versa. 8 LOG_ADDR_2 Input (Internal Pull up) Connected to the Most Significant Bit of the 3-bit logical address. This is an inverted pin; applying a high voltage on this pin corresponds to writing a logic ‘0’ and vice versa. 9 RSVD Reserved Reserved pin[2] 10 I2C_SCL Input I2C Serial Clock 11 I2C_SDA Input/Output I2C Serial Data Output to Disable external transmit circuitry during Receive Mode. Logic ‘0’ - When the Modem is transmitting Logic ‘1’ - When the Modem is not transmitting Note 2. Reserved pins must be left unconnected. Document Number: 001-50001 Rev. *M Page 18 of 35 CY8CPLC10 Datasheet Pin Definitions (continued) Pin Number Pin Name I/O Description 12 XTAL_STABILITY Input/Output External Crystal Stability. Connect a 0.1 µF capacitor between the pin and VSS. 13 XTAL_IN Input External Crystal Input. This is the input clock from an external crystal oscillator. This crystal is always required for protocol timing. 14 Vss Ground Ground 15 XTAL_OUT Output External Crystal Output. This pin is used along with XTAL_IN to connect to the external oscillator. This crystal is always required for protocol timing. 16 TX_LED Output TX Indicator LED 17 EXTCLK Input Optional external 24 MHz clock oscillator input for PLC modem. 18 BIU_LED Output BIU Indicator LED 19 RESET Reset Reset Pin 20 RXCOMP_OUT Analog Output Analog Output to the external Low Pass Filter circuitry. 21 RXCOMP_IN Analog Input Analog Input from the external Low Pass Filter circuitry 22 AGND Ground Analog Ground. Connect a 1.0 uF capacitor between the pin and VSS. 23 HOST_INT Output Interrupt Output to Host Controller. Polarity and enable are configured by the INT_Enable register. 24 RSVD Reserved Reserved Pin[3] 25 RSVD Reserved Reserved Pin[3] 26 I2C_ADDR Input (Internal Pull up) Set I2C Slave Address. When high - Slave Address ‘0x01’ When low - Slave Address ‘0x7A’ 27 FSK_IN Input Analog FSK Input.This is the input signal from the Powerline. 28 VDD Power Supply Voltage. 5V ± 5% Note 3. Reserved pins must be left unconnected. Document Number: 001-50001 Rev. *M Page 19 of 35 CY8CPLC10 Datasheet Electrical Specifications This section presents the DC and AC electrical specifications of the CY8CPLC10 PLC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com. Absolute Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Table 6. Absolute Maximum Ratings Symbol TSTG Description Storage Temperature TBAKETEMP Bake Temperature Min -55 Typ 25 Max +100 Units C – 125 C See package label -40 – See package label 72 Hours – +85 C – – – – +6.0 Vdd + 0.5 Vdd + 0.5 +50 V V V mA – +50 mA – – – 200 V mA Typ – – Max +85 +100 TBAKETIME Bake Time TA Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss -0.5 DC Input Voltage Vss - 0.5 DC Voltage Applied to Tristate Vss - 0.5 Maximum Current into any Input/Output -25 Pin Maximum Current into any Input/Output -50 Pin Configured as Analog Driver Electro Static Discharge Voltage 2000 Latch up Current – Vdd VIO VIOZ IMIO IMAIO ESD LU Notes Higher storage temperatures reduces data retention time. Recommended storage temperature is +25C ± 25C. Extended duration storage temperatures above 65C degrades reliability. Human Body Model ESD. Operating Temperature Table 7. Operating Temperature Symbol TA TJ Description Ambient Temperature Junction Temperature Document Number: 001-50001 Rev. *M Min -40 -40 Units Notes C C The temperature rise from ambient to junction is package specific. See Thermal Impedances on page 24.The user must limit the power consumption to comply with this requirement. Page 20 of 35 CY8CPLC10 Datasheet DC Electrical Characteristics DC Power Supply The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C. Typical parameters apply to 5V at 25C and are for design guidance only. Table 8. DC Power Supply Symbol VDD IDD (TX Mode) IDD (RX Mode) Description Supply Voltage Supply current (TX Mode) Supply current (RX Mode) Min 4.75 Typ – 30 41 Max 5.25 Units V mA mA Notes Conditions are 5.0V, TA = 25C Conditions are 5.0V, TA = 25C DC I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9. DC I/O Specifications Symbol RPU RPD VOH VOL IOH Description Pull Up Resistor Pull Down Resistor High Output Level Low Output Level High Level Source Current Min 4 4 Vdd - 1.0 – 10 Typ 5.6 5.6 – – – Max 8 8 – 0.75 – Units k k V V mA IOL Low Level Sink Current 25 – – mA VIL VIH VH IIL CIN COUT Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output – 2.1 – – – – – – 60 1 3.5 3.5 0.8 V V mV nA pF pF – – 10 10 Notes IOH = 10 mA IOL = 25 mA VOH = Vdd-1.0V. See the limitations of the total current in the Note for VOH. VOL = 0.75V. See the limitations of the total current in the Note for VOL. Gross tested to 1 A. Pin dependent. Temp = 25C. Pin dependent. Temp = 25C. DC Modem Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10. DC Modem Specifications Symbol VFSK_OUTDC VFSK_INDC Description FSK_OUT DC Voltage FSK_IN DC Voltage Document Number: 001-50001 Rev. *M Min Typ VDD/2 VDD/2 Max Units V V Notes Page 21 of 35 CY8CPLC10 Datasheet DC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 11. DC I2C Specifications Min Typ Max Units VILI2C[4] Parameter Input low level Description – – 0.25 × VDD V 4.75 V VDD 5.25 V Notes VIHI2C[4] Input high level 0.7 × VDD – – V 4.75V VDD 5.25 V AC Electrical Characteristics AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 12. AC Chip-Level Specifications Symbol F32K2 Description External Crystal Oscillator Min – Typ 32.768 Max – Units kHz TXRST External Reset Pulse Width SRPOWER_UP Power Supply Slew Rate TPOWERUP Time from End of POR to Readiness for PLC and I2C Communication 10 – – – – 1.25 – 250 – s V/ms s Notes Accuracy is capacitor and crystal dependent. 50% duty cycle. Vdd slew rate during power up. Power up from 0V. AC Modem Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C. Typical parameters apply to 5V at 25C and are for design guidance only. Table 13. AC Modem Specifications Symbol Description VFSK_OUTH2 FSK_OUT Second Harmonic (Fundamental = 125 mVp-p) _125mV VFSK_OUTH3 FSK_OUT Third Harmonic (Fundamental = 125 mVp-p) _125mV VFSK_OUTH2 FSK_OUT Second Harmonic (Fundamental = 1.55Vp-p) _1.55V VFSK_OUTH3 FSK_OUT Third Harmonic (Fundamental = 1.55Vp-p) _1.55V VFSK_INMAX Maximum FSK_IN Signal Min – Typ –32 Max – Units dBC – –9 – dBC – –34 – dBC – –15 – dBC – VDD – Vp-p Notes AC I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 14. AC I/O Specifications Symbol TRiseS TFallS Description Rise Time, Cload = 50 pF Fall Time, Cload = 50 pF Min 10 10 Typ 27 22 Max – – Units[5] ns ns Notes 10% - 90% 10% - 90% Note 4. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO specifications sections.The I2C GPIO pins also meet the mentioned specs. Document Number: 001-50001 Rev. *M Page 22 of 35 CY8CPLC10 Datasheet Figure 11. I/O Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 15. AC Characteristics of the I2C SDA and SCL Pins Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. Fast-Mode Min Max 0 400 0.6 – 1.3 0.6 0.6 0 100[6] 0.6 500 0 Units Notes kHz s s s s s ns s s ns – – – – – – – 50 Figure 12. Definition for Timing on the I2C Bus Packaging Dimensions I2C_SDA TSUDATI2C THDSTAI2C TSPI2C THDDATI2CTSUSTAI2C TBUFI2C I2C_SCL THIGHI2C TLOWI2C S START Condition TSUSTOI2C Sr Repeated START Condition P S STOP Condition Notes 5. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period) 6. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-50001 Rev. *M Page 23 of 35 CY8CPLC10 Datasheet Packaging Information This section illustrates the packaging specifications for the CY8CPLC10 PLC device, along with the thermal impedances for the package and the typical package capacitance on crystal pins. Figure 13. 28-pin SSOP (210 Mils) O28.21 Package Outline, 51-85079 51-85079 *F Capacitance on Crystal Pins Thermal Impedances [8] Table 16. Thermal Impedances per Package Package 28-pin SSOP JA[7] Typical 94 C/W Table 17. Typical Package Capacitance on Crystal Pins Typical JC 29 C/W Package 28-pin SSOP Package Capacitance 2.8 pF Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 18. Solder Reflow Peak Temperature Package Maximum Peak Temperature Time at Maximum Peak Temperature 28-pin SSOP 260 C 20 s Notes 7. TJ = TA + POWER x JA 8. To achieve the thermal impedance specified for the QFN package,refer to "Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages" available at http://www.amkor.com. Document Number: 001-50001 Rev. *M Page 24 of 35 CY8CPLC10 Datasheet Development Tool Selection Development Kits The development kits do not have on-board Powerline capability, but can be used with a PLC kit for development purposes. All development tools and development kits are sold at the Cypress Online Store. CY3215A-DK Basic Development Kit The CY3215A-DK is for prototyping and development with PSoC Designer. This kit can be used in conjunction with the PLC kits to support in-circuit emulation. The software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. PSoC Designer also supports the advanced emulation features. The kit includes: ■ PSoC Designer Software CD ■ ICE-Cube In-Circuit Emulator ■ ICE Flex-Pod for CY8C29x66 Family ■ Cat-5 Adapter ■ Mini-Eval Programming Board ■ boarding space to meet all your evaluation needs. The kit includes: ■ Evaluation Board with LCD Module ■ MiniProg Programming Unit ■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator, and plenty of bread boarding space to meet all your evaluation needs. The kit includes: ■ PSoCEvalUSB Board 110 ~ 240 V Power Supply, Euro-Plug Adapter ■ LCD Module ■ iMAGEcraft C Compiler ■ MIniProg Programming Unit ■ ISSP Cable ■ Mini USB Cable ■ USB 2.0 Cable and Blue Cat-5 Cable ■ PSoC Designer and Example Projects CD ■ 2 CY8C29466-24PXI 28-PDIP Chip Samples ■ Getting Started Guide Evaluation Kits ■ Wire Pack CY3217-MiniProg1 Device Programmers The CY3217-MiniProg1 kit enables the user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC through a provided USB 2.0 cable. The kit includes: All device programmers are purchased from the Cypress Online Store. ■ MiniProg Programming Unit ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of bread Document Number: 001-50001 Rev. *M CY3217-MiniProg1 The CY3217-MiniProg1 kit enables the user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC through a provided USB 2.0 cable. The kit includes: ■ MiniProg Programming Unit ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable Page 25 of 35 CY8CPLC10 Datasheet Ordering Information The following table lists the CY8CPLC10 PLC device’s key package features and ordering codes. Table 19. CY8CPLC10 PLC Device Key Features and Ordering Information Package Ordering Code 28-pin (210 Mil) SSOP CY8CPLC10-28PVXI 28-pin (210 Mil) SSOP (Tape and Reel) CY8CPLC10-28PVXIT Temperature Range –40C to +85 C –40C to +85 C Ordering Code Definitions CY 8 C PLC 10 - xx xxx Package Type: PVX = SSOP Pb-Free Thermal Rating: I = Industrial Pin Count: 28 Fixed Function Device Family Code: Powerline Communication Solution Technology Code: C = CMOS Marketing Code: 8 = Cypress M8C Core Company ID: CY = Cypress Document Number: 001-50001 Rev. *M Page 26 of 35 CY8CPLC10 Datasheet Acronyms Acronyms Used Table 20 lists the acronyms that are used in this document. Table 20. Acronyms Used in this Datasheet Acronym AC Description Acronym Description Alternating Current LED Light-Emitting Diode BIU Band-In-Use LPF Low Pass Filter CMOS Complementary Metal Oxide Semiconductor MIPS Million Instructions Per Second CRC Cyclic Redundancy Check PCB Printed Circuit Board CSMA Carrier Sense Multiple Access PDIP Plastic Dual-In-Line Package DC Direct Current PLC Powerline Communication EEPROM Electrically Erasable Programmable Read-Only Memory PLL Phase-Locked Loop FSK Frequency-Shift Keying PLT Powerline Transceiver GPIO General-Purpose I/O POR Power On Reset I/O Input/Output PSoC® Programmable System-on-Chip ICE In-Circuit Emulator QFN Quad Flat No leads ISSP In-System Serial Programming SSOP Shrink Small-Outline Package LCD Liquid Crystal Display USB Universal Serial Bus Reference Documents CY8CPLC20 Datasheet, Powerline Communication Solution. AN58825 - Cypress Powerline Communication Debugging Tools. Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com. Document Conventions Units of Measure Table 21 lists the units of measures. Table 21. Units of Measure Symbol Unit of Measure Symbol Unit of Measure C degree Celsius mm millimeter kHz kilohertz ms millisecond k kilohm mV millivolt MHz megahertz nA nanoampere µA microampere ns nanosecond µF microfarad pF picofarad µs microsecond V volt µVrms microvolts root-mean-square W watt Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimals. Document Number: 001-50001 Rev. *M Page 27 of 35 CY8CPLC10 Datasheet Glossary active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. analog-to-digital (ADC) A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. Application programming interface (API) A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. bandwidth 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. bias 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler A program that translates a high level language, such as C, into machine language. Document Number: 001-50001 Rev. *M Page 28 of 35 CY8CPLC10 Datasheet Glossary (continued) configuration space In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. debugger A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition. digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. digital-to-analog (DAC) A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) converter performs the reverse operation. duty cycle The relationship of a clock period high time to its low time, expressed as a percent. emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. External Reset (XRES) An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. Flash An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is OFF. Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. frequency The number of cycles or events per unit of time, for a periodic function. gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts data from a system. Document Number: 001-50001 Rev. *M Page 29 of 35 CY8CPLC10 Datasheet Glossary (continued) interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (ISR) A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold. (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal The reference to a circuit containing both analog and digital techniques and components. modulator A device that imposes a signal on a carrier. noise 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. oscillator A circuit that may be crystal controlled and is used to generate a clock frequency. parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). Phase-locked loop (PLL) An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. port A group of pins, usually eight. Power on reset (POR) A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of hardware reset. PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark of Cypress. Document Number: 001-50001 Rev. *M Page 30 of 35 CY8CPLC10 Datasheet Glossary (continued) PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. register A storage device with a specific capacity, such as a bit or byte. reset A means of bringing a system back to a know state. See hardware reset and software reset. ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. serial 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. SRAM An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. stop bit A signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. Document Number: 001-50001 Rev. *M Page 31 of 35 CY8CPLC10 Datasheet Glossary (continued) VDD A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. VSS A name for a power net meaning "voltage source." The most negative power supply signal. watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. Document Number: 001-50001 Rev. *M Page 32 of 35 CY8CPLC10 Datasheet Document History Page Document Title: CY8CPLC10 Datasheet, Powerline Communication Solution Document Number: 001-50001 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 2606671 GHH / 11/13/08 New data sheet. PYRS *A 2662761 GHH / 02/20/09 Added: AESA - Configurable Baud Rates and FSK Frequencies - Configurable RX Gain *B 2748542 GHH / 08/05/2009 Converted from Preliminary to Final PYRS Modified: - Memory Map Structure (Added TX_Gain Register) - Pinout (Added option for external clocking: EXTCLK) *C 2752799 GHH 08/17/2009 Posting to external web. *D 2754780 GHH / 08/21/2009 Added PYRS - Optional external clock oscillator - Suppy current for TX and RX modes Removed - Noise strength from Memory map in Table3 *E 2759000 GHH 09/02/2009 Modified - DC Power Supply Specifications Added - DC Modem Specifications - AC Modem Specifications Updated Figures 5, 6, 7, 8, and 9. *F 2761019 GNKK 09/08/2009 Corrected revision in Page 1 *G 2778970 FRE 10/05/2009 Updated Figure 1 and Table 6 to state the requirement to use the external crystal for protocol timing Table 6 and Figure 10: Changed pin 9 from NC to RSVD Fixed minor typos *H 2846686 FRE 01/12/2010 Add Table of Contents. Update copyright and Sales URLs. Update 28-Pin SSOP package diagram. Update DC GPIO and AC Chip-Level Specifications as follows: Replace TRAMP (time) with SRPOWER_UP (slew rate). Replace TOS and TOSACC with TPOWERUP. Add IOH and IOL. *I 2903114 NJF 04/01/2010 Updated Cypress website links Added TBAKETEMP and TBAKETIME parameters Updated package diagram *J 2938300 CGX 05/27/10 Minor ECN to post to external website *K 3114960 NJF 12/19/10 Added DC I2C Specifications table. Updated Units of Measure, Acronyms, Glossary, and References sections. Updated solder reflow specifications. No specific changes was made to I2C Timing Diagram. It was updated for clearer understanding. Removed footnote reference for “Solder Reflow Peak Temperature” table. Changed the TBUFI2C parameter minimum from 1.3 to 500 µs Added a typical JC parameter to the Thermal Impedances table *L 4119144 ADIY 09/10/2013 Updated Packaging Information: spec 51-85079 – Changed revision from *D to *E. Updated to new template. Completing Sunset Review. Document Number: 001-50001 Rev. *M Page 33 of 35 CY8CPLC10 Datasheet Document History Page (continued) Document Title: CY8CPLC10 Datasheet, Powerline Communication Solution Document Number: 001-50001 Orig. of Submission Rev. ECN No. Description of Change Change Date *M 4841422 SREH 08/21/2015 Updated Document Title to read as “CY8CPLC10 Datasheet, Powerline Communication Solution”. Updated Detailed Description: Updated CY8CPLC10 Memory Map: Added detailed description below Table 4. Updated Packaging Information: spec 51-85079 – Changed revision from *E to *F. Updated Development Tool Selection: Updated Development Kits: Removed “CY3215-DK Basic Development Kit”. Added CY3215A-DK Basic Development Kit. Updated Evaluation Kits: Removed “CY3272 HV Evaluation Kit”. Removed “CY3273 LV Evaluation Kit”. Removed “CY3210-MiniProg1”. Added CY3217-MiniProg1. Updated Device Programmers: Removed “CY3216 Modular Programmer”. Removed “CY3207 ISSP In-System Serial Programmer (ISSP)”. Added CY3217-MiniProg1. Updated Reference Documents: Removed reference of spec 001-52478 as the spec is obsolete. Added “CY8CPLC20 Datasheet, Powerline Communication Solution”. Added “AN58825 - Cypress Powerline Communication Debugging Tools”. Updated to new template. Completing Sunset Review. Document Number: 001-50001 Rev. *M Page 34 of 35 CY8CPLC10 Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-50001 Rev. *M Revised August 21, 2015 Page 35 of 35 PSoC Designer™ and EZ-Color™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders,