IR3505 DATA SHEET XPHASE3TM PHASE IC DESCRIPTION TM The IR3505 Phase IC combined with an IR XPhase3 Control IC provides a full featured and flexible way to implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single TM phase of a multiphase converter. The XPhase3 architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. FEATURES 7V/2A gate drivers (4A GATEL sink current) Support converter output voltage up to 5.1 V (Limited to VCCL-1.4V) Support loss-less inductor current sensing Feed-forward voltage mode control Integrated boot-strap synchronous PFET Only four IC related external components per phase 3 wire analog bus connects Control and Phase ICs (VDAC, Error Amp, ISHARE) 3 wire digital bus for accurate daisy-chain phase timing control without external components Debugging function isolates phase IC from the converter Self-calibration of PWM ramp, current sense amplifier, and current share amplifier Single-wire bidirectional average current sharing Small thermally enhanced 16L 3 x 3mm MLPQ package RoHS compliant • • • • • • • • • • • • • APPLICATION CIRCUIT 12V VCC 13 14 CSIN+ GATEH BOOST GATEL PGND RCS VCCL 12 CIN 11 CBST L 10 VOUT+ 9 COUT VOUT- 8 PHSIN 7 4 LGND CLKIN 3 IR3505 PHASE IC DACIN 5 6 Wire Bus to Control IC SW 6 2 ISHARE PHSOUT 1 CSIN- EAIN 16 15 CCS CVCCL VCCL Page 1 of 19 th Mar 04 , 2008 IR3505 ORDERING INFORMATION Part Number IR3505MTRPBF Package 16 Lead MLPQ (3 x 3 mm body) 16 Lead MLPQ (3 x 3 mm body) * IR3505MPBF Order Quantity 3000 per reel 100 piece strips * Samples only ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. o o Operating Junction Temperature…………….. 0 C to 150 C o o Storage Temperature Range………………….-65 C to 150 C MSL Rating………………………………………2 o Reflow Temperature…………………………….260 C PIN # PIN NAME VMAX VMIN ISOURCE ISINK 1 2 3 4 5 6 ISHARE DACIN LGND PHSIN PHSOUT CLKIN 8V 3.3V n/a 8V 8V 8V -0.3V -0.3V n/a -0.3V -0.3V -0.3V 1mA 1mA n/a 1mA 2mA 1mA 1mA 1mA n/a 1mA 2mA 1mA 7 PGND 0.3V -0.3V n/a 8 GATEL 8V 9 VCCL 8V -0.3V DC, -5V for 100ns -0.3V 5A for 100ns, 200mA DC 5A for 100ns, 200mA DC n/a 10 BOOST 34V -0.3V 1A for 100ns, 100mA DC 5A for 100ns, 200mA DC 5A for 100ns, 200mA DC 3A for 100ns, 100mA DC 11 GATEH 34V -0.3V DC, -5V for 100ns 3A for 100ns, 100mA DC 3A for 100ns, 100mA DC 12 SW 34V VCC CSIN+ CSINEAIN 18V 8V 8V 8V 3A for 100ns, 100mA DC n/a 1mA 1mA 1mA n/a 13 14 15 16 -0.3V DC, -5V for 100ns -0.3V -0.3V -0.3V -0.3V 10mA 1mA 1mA 1mA Note: 1. Maximum GATEH – SW = 8V 2. Maximum BOOST – GATEH = 8V Page 2 of 19 th Mar 04 , 2008 IR3505 RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 8.0V ≤ VCC ≤ 16V, 4.75V ≤ VCCL ≤ 7.5V, 0.5V ≤ V(DACIN) ≤ 1.6V, 250kHz ≤ CLKIN ≤ 9MHz, 250kHz ≤ PHSIN o o ≤1.5MHz, 0 C ≤ TJ ≤ 125 C ELECTRICAL CHARACTERISTICS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. Typical values represent the median values, which are related to 25°C. CGATEH = 3.3nF, CGATEL = 6.8nF (unless otherwise specified). PARAMETER Gate Drivers GATEH Source Resistance GATEH Sink Resistance GATEL Source Resistance GATEL Sink Resistance GATEH Source Current GATEH Sink Current GATEL Source Current GATEL Sink Current GATEH Rise Time GATEH Fall Time GATEL Rise Time GATEL Fall Time GATEL low to GATEH high delay GATEH low to GATEL high delay Disable Pull-Down Resistance Clock CLKIN Threshold CLKIN Bias Current CLKIN Phase Delay PHSIN Threshold PHSOUT Propagation Delay PHSIN Pull-Down Resistance PHSOUT High Voltage PHSOUT Low Voltage Page 3 of 19 TEST CONDITION BOOST – SW = 7V. Note 1 BOOST – SW = 7V. Note 1 VCCL – PGND = 7V. Note 1 VCCL – PGND = 7V. Note 1 BOOST=7V, GATEH=2.5V, SW=0V. BOOST=7V, GATEH=2.5V, SW=0V. VCCL=7V, GATEL=2.5V, PGND=0V. VCCL=7V, GATEL=2.5V, PGND=0V. BOOST – SW = 7V, measure 1V to 4V transition time BOOST - SW = 7V, measure 4V to 1V transition time VCCL – PGND = 7V, Measure 1V to 4V transition time VCCL – PGND = 7V, Measure 4V to 1V transition time BOOST = VCCL = 7V, SW = PGND = 0V, measure time from GATEL falling to 1V to GATEH rising to 1V BOOST = VCCL = 7V, SW = PGND = 0V, measure time from GATEH falling to 1V to GATEL rising to 1V Note 1 Compare to V(VCCL) CLKIN = V(VCCL) Measure time from CLKIN<1V to GATEH>1V Compare to V(VCCL) Measure time from CLKIN > (VCCL * 50% ) o to PHSOUT > (VCCL *50%). 10pF @125 C I(PHSOUT) = -10mA, measure VCCL – PHSOUT I(PHSOUT) = 10mA MIN TYP MAX UNIT 1.0 1.0 1.0 0.4 2.0 2.0 2.0 4.0 5 2.5 2.5 2.5 1.0 10 Ω Ω Ω Ω A A A A ns 5 10 ns 10 20 ns 5 10 ns 10 20 40 ns 10 20 40 ns 30 80 130 kΩ 40 -0.5 40 45 0.0 75 57 0.5 125 % µA ns 35 4 50 15 55 35 % ns 30 100 170 kΩ 1 0.6 V 0.4 1 th Mar 04 , 2008 V IR3505 PARAMETER PWM Comparator TEST CONDITION PWM Ramp Slope Vin=12V Input Offset Voltage EAIN Bias Current Minimum Pulse Width Minimum GATEH Turn-off Time Current Sense Amplifier CSIN+/- Bias Current CSIN+/- Bias Current Mismatch Input Offset Voltage Note 1 0 ≤ EAIN ≤ 3V Note 1 Gain Unity Gain Bandwidth Slew Rate Differential Input Range Differential Input Range Common Mode Input Range o Rout at TJ = 25 C o Rout at TJ = 125 C ISHARE Source Current ISHARE Sink Current Share Adjust Amplifier Input Offset Voltage Differential Input Range Gain Unity Gain Bandwidth PWM Ramp Floor Voltage Maximum PWM Ramp Floor Voltage Minimum PWM Ramp Floor Voltage Body Brake Comparator Threshold Voltage with EAIN falling. Threshold Voltage with EAIN rising. Hysteresis Propagation Delay Page 4 of 19 Note 1 CSIN+ = CSIN- = DACIN. Measure input referred offset from DACIN 0.5V ≤ V(DACIN) < 1.6V C(ISHARE)=10pF. Measure at ISHARE. Note 1 MIN TYP MAX UNIT 42 -5 -5 52.5 0 -0.3 65 57 5 5 75 mV/ %DC mV µA ns 20 80 160 nS -200 -50 0 0 200 50 nA nA 1 mV 35 8.8 V/V MHz 50 50 Note2 3.7 5.4 2.9 2.9 V/µs mV mV V kΩ kΩ mA mA mV V V/V kHz mV -1 30 4.8 32.5 6.8 6 0.8V ≤ V(DACIN) ≤ 1.6V, Note 1 0.5V ≤ V(DACIN) < 0.8V, Note 1 Note 1 Note 1 -10 -5 0 2.3 3.6 0.500 0.500 Note 1 Note 1 CSIN+ = CSIN- = DACIN. Note 1 Note 1 ISHARE unconnected Measured Relative to DACIN ISHARE = DACIN - 200mV Measured relative to FLOOR with ISHARE unconnected ISHARE = DACIN + 200mV Measured relative to FLOOR with ISHARE unconnected -3 -1 4 4 -116 5.0 8.5 0 3 1 6 17 +116 120 180 240 -220 -160 -100 -300 -200 -110 mV -200 -100 -10 mV 70 40 105 65 130 90 mV ns Measured relative to PWM Ramp Floor Voltage Measured relative to PWM Ramp Floor Voltage VCCL = 5V. Measure time from EAIN < V(DACIN) (200mV overdrive) to GATEL transition to < 4V. 3.0 4.7 1.6 1.4 0 mV mV th Mar 04 , 2008 IR3505 PARAMETER OVP Comparator OVP Threshold TEST CONDITION Step V(ISHARE) up until GATEL drives high. Compare to V(VCCL) Propagation Delay V(VCCL)=5V, Step V(ISHARE) up from V(DACIN) to V(VCCL). Measure time to V(GATEL)>4V. Synchronous Rectification Disable Comparator Threshold Voltage The ratio of V(CSIN-) / V(DACIN), below which V(GATEL) is always low. Negative Current Comparator Input Offset Voltage Note 1 Propagation Delay Time Apply step voltage to V(CSIN+) – V(CSIN-). Measure time to V(GATEL)< 1V. Bootstrap Diode Forward Voltage I(BOOST) = 30mA, VCCL=6.5V Debug Comparator Threshold Voltage Compare to V(VCCL) General VCC Supply Current VCCL Supply Current BOOST Supply Current 4.75V ≤ V(BOOST)-V(SW) ≤ 8V DACIN Bias Current SW Bias Current MIN TYP MAX UNIT -1.0 -0.8 -0.4 V 15 40 70 nS 66 75 86 % -16 100 0 200 16 400 mV nS 180 260 480 mV -250 -150 -50 mV 1.1 3.1 1.2 3.0 6.7 3.5 6.1 12.1 5.8 mA mA mA -1.5 -0.5 -0.75 -1.8 1 µA -2.9 mA Note 1: Guaranteed by design, but not tested in production Note 2: VCCL-0.5V or VCC – 2.5V, whichever is lower Page 5 of 19 th Sept 26 , 2007 IR3505 PIN DESCRIPTION PIN# 1 PIN SYMBOL ISHARE 2 DACIN 3 4 5 LGND PHSIN PHSOUT 6 7 8 9 CLKIN PGND GATEL VCCL 10 BOOST 11 12 13 14 15 GATEH SW VCC CSIN+ CSIN- 16 EAIN Page 6 of 19 PIN DESCRIPTION Output of the Current Sense Amplifier is connected to this pin through a 3kΩ resistor. Voltage on this pin is equal to V(DACIN) + 32.5 [V(CSIN+) – V(CSIN-)]. Connecting all ISHARE pins together creates a share bus which provides an indication of the average current being supplied by all the phases. The signal is used by the Control IC for voltage positioning and over-current protection. OVP mode is initiated if the voltage on this pin rises above V(VCCL)- 0.8V. Reference voltage input from the Control IC. The Current Sense signal and PWM ramp is referenced to the voltage on this pin. Ground for internal IC circuits. IC substrate is connected to this pin. Phase clock input. Phase clock output. Clock input. Return for low side driver and reference for GATEH non-overlap comparator. Low-side driver output and input to GATEH non-overlap comparator. Supply for low-side driver. Internal bootstrap synchronous PFET is connected from this pin to the BOOST pin. Supply for high-side driver. Internal bootstrap synchronous PFET is connected between this pin and the VCCL pin. High-side driver output and input to GATEL non-overlap comparator. Return for high-side driver and reference for GATEL non-overlap comparator. Supply for internal IC circuits. Non-Inverting input to the current sense amplifier, and input to debug comparator. Inverting input to the current sense amplifier, and input to synchronous rectification disable comparator. PWM comparator input from the error amplifier output of Control IC. Body Braking mode is initiated if the voltage on this pin is less than V(DACIN). th Sept 26 , 2007 IR3505 SYSTEM THEORY OF OPERATION PWM Control Method TM The PWM block diagram of the XPhase architecture is shown in Figure 1. Feed-forward voltage mode control with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current. GATE DRIVE VOLTAGE CONTROL IC VIN PHSOUT PHASE IC CLOCK GENERATOR CLKOUT VCC CLKIN CLK Q VCCH D PHSOUT 1 PHSIN 1 2 D CBST VOSNS+ 4 Q SW 5 CLK Q VOUT R PWM COMPARATOR COUT - VCCL 3 PHSIN GATEH RESET DOMINANT 2 EAIN + GND PWM LATCH GATEL ENABLE + REMOTE SENSE AMPLIFIER PGND BODY BRAKING COMPARATOR + VID6 VOSNS- - - + - RAMP DISCHARGE CLAMP VO LDO AMPLIFIER VDAC LGND - ISHARE CURRENT SENSE AMPLIFIER VID6 VID6 - + + - 3K RCOMP VID6 VID6 + RFB1 RFB CCOMP FB RVSETPT IVSETPT IROSC VDRP AMP CSIN+ + CCOMP1 + CFB RCS CSIN- DACIN RDRP1 PHSOUT PHASE IC RDRP VSETPT CCS - + SHARE ADJUST ERROR AMPLIFIER EAOUT - VDAC + ERROR AMPLIFIER CDRP VDRP VCC CLK Q CLKIN + - D IIN 1 PHSIN 1 D Q CLK Q GATEH CBST 5 SW R 2 4 3 PWM COMPARATOR VCCH RESET DOMINANT 2 EAIN + VCCL PWM LATCH ENABLE + VID6 - RAMP DISCHARGE CLAMP GATEL BODY BRAKING COMPARATOR PGND - + SHARE ADJUST ERROR AMPLIFIER CURRENT SENSE AMPLIFIER + - VID6 VID6 + CSIN+ VID6 VID6 + + DACIN CCS RCS - - 3K + ISHARE CSIN- Figure 1 PWM Block Diagram Frequency and Phase Timing Control The oscillator is located in the Control IC and the system clock frequency is programmable from 250kHz to 9MHZ by an external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output (PHSOUT) is connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the second phase IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of the control IC. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 2 shows the phase timing for a four phase converter. The switching frequency is set by the resistor ROSC as shown in Figure 9. The clock frequency equals the number of phase times the switching frequency. Page 7 of 19 th Sept 26 , 2007 IR3505 Control IC CLKOUT (Phase IC CLKIN) Control IC PHSOUT (Phase IC1 PHSIN) Phase IC1 PWM Latch SET Phase IC 1 PHSOUT (Phase IC2 PHSIN) Phase IC 2 PHSOUT (Phase IC3 PHSIN) Phase IC 3 PHSOUT (Phase IC4 PHSIN) Phase IC4 PHSOUT (Control IC PHSIN) Figure 2 Four Phase Oscillator Waveforms PWM Operation The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is set; the PWM ramp voltage begins to increase; the low side driver is turned off, and the high side driver is turned on after the non-overlap time. When the PWM ramp voltage exceeds the error amplifier’s output voltage the PWM latch is reset. This turns off the high side driver, turns on the low side driver after the non-overlap time, and activates the ramp discharge clamp. The clamp drives the PWM ramp voltage to the level set by the share adjust amplifier until the next clock pulse. The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients. An additional advantage of this PWM modulator is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Figure 3 depicts PWM operating waveforms under various conditions. Page 8 of 19 th Sept 26 , 2007 IR3505 PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION DUTY CYCLE INCREASE DUE TO LOAD INCREASE DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD) DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCCLUV, OCP, VID=11111X) STEADY-STATE OPERATION Figure 3 PWM Operating Waveforms Body Braking TM In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; TSLEW = L * ( I MAX − I MIN ) VO The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is now; TSLEW = L * ( I MAX − I MIN ) VO + VBODYDIODE Since the voltage drop in the body diode is often comparable to the output voltage, the inductor current slew rate can be increased significantly. This patented technique is referred to as “body braking” and is accomplished through the “body braking comparator” located in the phase IC. If the error amplifier’s output voltage drops below the output voltage of the share adjust amplifier in the phase IC, this comparator turns off the low side gate driver. Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in Figure 4. The equation of the sensing network is, vC ( s ) = vL ( s ) 1 RL + sL = iL ( s ) 1 + sRCS CCS 1 + sRCS CCS Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current. Page 9 of 19 th Sept 26 , 2007 IR3505 vL iL Current Sense Amp L RL RCS CCS VO CO c vCS CSOUT Figure 4 Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors. Current Sense Amplifier A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 5. Its gain is nominally 32.5 and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop feedback path. The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and other phases through an on-chip 3KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are tied together and the voltage on the share bus represents the average current through all the inductors and is used by the control IC for voltage positioning and current limit protection. The input offset of this amplifier is calibrated to +/- 1mV in order to reduce the current sense error. The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This calibration algorithm creates ripple on ISHARE bus with a frequency of fsw/(32*28) in a multiphase architecture. Average Current Share Loop Current sharing between phases of the converter is achieved by the average current share loop in each phase IC. The output of the current sense amplifier is compared with the average current at the share bus. If current in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty cycle and output current. The current share amplifier is internally compensated so that the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. Page 10 of 19 th Sept 26 , 2007 IR3505 IR3505 THEORY OF OPERATION Block Diagram The Block diagram of the IR3505 is shown in Figure 5, and specific features are discussed in the following sections. CLKIN PHSOUT CLK Q GATEH DRIVER D PHSIN PWM LATCH 100% DUTY LATCH PWMQ GATEH PWMQ CLK Q D Q PWM_CLK CLK Q D R PWM_CLK PWM COMPARATOR EAIN RESET DOMINANT GATEH NONOVERLAP LATCH - Q + RMPOUT PHSIN VCC BOOST PWM RAMP GENERATOR VCC VCCL CALIBRATION - S + SET R DOMINANT PWM RESET 1V GATEL NONOVERLAP COMPARATOR 1V GATEL NONOVERLAP LATCH DACIN-SHARE_ADJ S + Q SET R DOMINANT - BODY BRAKING 100mV COMPARATOR 200mV GATEL DRIVER + - DACIN + OVP COMPARATOR SHARE_ADJ SW GATEH NONOVERLAP COMPARATOR NEGATIVE CURRENT LATCH VCCL GATEL PGND VCCL Q 0.8V + DEBUG OFF (LOW=OPEN) ISHARE RESET DOMINANT R SYNCHRONOUS RECTIFICATION DISABLE COMPARATOR S NEGATIVE CURRENT COMPARATOR SHARE ADJUST AMPLIFIER - 3K CSAOUT + + - + IROSC (CLKIN PHSIN DACIN CSIN- - X33 + CALIBRATION DACIN CURRENT SENSE AMPLIFIER + - CSIN+ + X 0.75 CALIBRATION DEBUG COMPARATOR 0.2V - IF 1-PHASE) LGND + IROSC Figure 5 Block diagram Tri-State Gate Drivers The gate drivers can deliver up to 2A peak current (4A sink current for bottom driver). An adaptive non-overlap circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot-through current while minimizing body diode conduction. The non-overlap latch is added to eliminate the error triggering caused by the switching noise. An enable signal is provided by the control IC to the phase IC without the addition of a dedicated signal line. The error amplifier output of the control IC drives low in response to any fault condition such as VCCL TM under voltage or output overload. The IR3505 Body Braking comparator detects this and drives bottom gate output low. This tri-state operation prevents negative inductor current and negative output voltage during powerdown. A synchronous rectification disable comparator is used to detect converter CSIN- pin voltage, which represents local converter output voltage. If the voltage is below 75% of VDAC and negative current is detected, GATEL drives low, which disables synchronous rectification and eliminates negative current during power-up. The gate drivers pull low if the supply voltages are below the normal operating range. An 80kΩ resistor is connected across the GATEH/GATEL and PGND pins to prevent the GATEH/GATEL voltage from rising due to leakage or other causes under these conditions. th Page 11 of 19 Sept 26 , 2007 IR3505 Over Voltage Protection (OVP) The IR3505 includes over-voltage protection that turns on the low side MOSFET to protect the load in the event of a shorted high-side MOSFET, converter out of regulation, or connection of the converter output to an excessive output voltage. As shown in Figure 6, if ISHARE pin voltage is above V(VCCL) – 0.8V, which represents over-voltage condition detected by control IC, the over-voltage latch is set. GATEL drives high and GATEH drives low. The OVP circuit overrides the normal PWM operation and within approximately 150ns will fully turn-on the low side MOSFET, which remains ON until ISHARE drops below V(VCCL) – 0.8V when over voltage ends. The over voltage fault is latched in control IC and can only be reset by cycling the power to control IC. The error amplifier output (EAIN) is pulled down by control IC and will remain low. The lower MOSFETs alone can not clamp the output voltage however an SCR or N-MOSFET could be triggered with the OVP output to prevent processor damage. OUTPUT VOLTAGE (VO) OVP THRESHOLD VCCL-800 mV ISHARE(IIN) GATEH GATEL FAULT LATCH (CONTROL IC) ERROR AMPLIFIER INPUT (EAIN) VDAC NORMAL OPERATION OVP CONDITION AFTER OVP Figure 6 - Over-voltage protection waveforms PWM Ramp Every time the phase IC is powered up PWM ramp magnitude is calibrated to generate a 50 mV/% ramp for a VCC=12V. For example, for a 15% duty ratio the ramp amplitude is 750mV for VCC=12V. Feed-forward control is achieved because the PWM ramp varies with VCC voltage proportionally after calibration. Debugging Mode If CSIN+ pin is pulled up to VCCL voltage, IR3505 enters into debugging mode. Both drivers are pulled low and ISHARE output is disconnected from the current share bus, which isolates this phase IC from other phases. However, the phase timing from PHSIN to PHSOUT does not change. Page 12 of 19 th Sept 26 , 2007 IR3505 Emulated Bootstrap Diode IR3505 integrates a PFET to emulate the bootstrap diode. An external bootstrap diode connected from VCCL pin to BOOST pin can be added to reduce the drop across the PFET but is not needed in most applications. APPLICATIONS INFORMATION IR3505 EXTERNAL COMPONENTS Inductor Current Sensing Capacitor CCS and Resistor RCS The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and capacitor CCS in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across the capacitor CCS represents the inductor current. If the two time constants are not the same, the AC component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch does not affect the average current sharing among the multiple phases, but does effect the current signal ISHARE as well as the output voltage during the load current transient if adaptive voltage positioning is adopted. Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS as follows. L RL (1) RCS = C CS Bootstrap Capacitor CBST Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is needed for the bootstrap circuit. Decoupling Capacitors for Phase IC A 0.1uF-1uF decoupling capacitor is required at the VCCL pin. CURRENT SHARE LOOP COMPENSATION The internal compensation of current share loop ensures that crossover frequency of the current share loop is at least one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated. The crossover frequency of current share loop is approximately 8 kHz. Output Voltage Bleed Resistor The floating high side driver draws bias current from the BOOST pin (3.5mA typical). This current flows out of the IR3505 through the SW pin and will charge up the output capacitor when the control IC is disabled. A bleed resistor connected from the converter output voltage to ground is required to prevent the output voltage from exceeding the control IC Over-Voltage protection threshold. The bleed resistor can be selected using the following equation. RBLEED = VBLEED / (5.8mA x N) (2) Where VBLEED is the maximum desired output voltage pre-bias and N is the number of IR3505 used in the converter. Optional phases A converter can be designed to support more or less phases. This can be quite useful in situations where the final load current is unknown or where increased load current may be required at some time in the future. Page 13 of 19 th Sept 26 , 2007 IR3505 Figure 7 provides an application circuit that allows adjustment to the number of phases. By populating zero ohm jumpers, or not; the number of phases can be adjusted by diverting the daisy chain timing from a 3505 to the next one in sequence. The effect of more or less phases on converter performance can be tested without actually removing a 3505 or it’s MOSFETs from the printed circuit board through use of a pull-up resistor from VCCL to the CSIN+ pin to enable de-bug mode. 14 15 13 GATEL VCCL 10 9 8 PGND 7 BOOST R31 0 ohm 13 14 CSIN+ VCC GATEH BOOST GATEL PHSIN PGND LGND SW IR3505 PHASE IC VCCL 8 R21 DACIN 7 4 15 16 3 9 CSIN- EAIN 10 ISHARE CLKIN 2 PHSOUT VCCL 1 11 6 14 13 VCC BOOST 12 5 PHSIN U3 GATEH GATEL LGND 8 R11 CSIN+ 4 IR3505 PHASE IC PGND 3 9 DACIN 7 10 15 16 EAIN 2 CLKIN 11 PHSOUT VCCL VCC CSIN+ 16 EAIN CSINCLKIN PHSOUT PHSIN 12 11 R33 0 ohm SW R22 0 ohm 12 11 10 9 R31 0 ohm 0 ohm R12 open LGND GATEH R32 open ISHARE 6 BOOST 1 5 8 PGND 7 GATEH GATEL IR3505 PHASE IC 12 CSIN- 13 U2 VCC 14 CSIN+ 15 16 EAIN PHSIN 4 SW IR3505 PHASE IC R23 Open SW CLKIN LGND PHSOUT 4 DACIN 5 CLKOUT 3 25 PHSIN PHSOUT 26 27 2 ISHARE 6 1 CSIN- U1 3 9 DACIN R22 open R13 Open IR3500 CONTROL IC 10 ISHARE 0 ohm R12 open Two Phase 2 R21 0 ohm U0 1 11 6 14 15 13 VCC VCCL 12 5 R11 BOOST GATEL PHSIN GATEH 8 LGND IR3505 PHASE IC PGND 4 DACIN 7 3 9 CSIN+ 16 10 CSIN- EAIN 2 SW CLKIN 11 R33 Open U3 ISHARE PHSOUT VCCL 1 6 14 15 13 VCC GATEL BOOST 12 5 5 GATEH 8 PHSIN PGND LGND IR3505 PHASE IC 7 4 SW CLKIN CLKOUT PHSIN PHSOUT 26 27 3 DACIN 25 Three Phase 2 R23 Open U2 ISHARE PHSOUT 1 CSIN+ EAIN U1 IR3500 CONTROL IC 6 U0 CSIN- 16 R13 Open open R32 open Figure 7 – Optional Phase application circuit Page 14 of 19 th Sept 26 , 2007 IR3505 LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. • Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND) and power ground plane (PGND). • Separate analog bus (EAIN, DACIN, and ISHARE) from digital bus (CLKIN, PHSIN, and PHSOUT) to reduce the noise coupling. • Connect PGND to LGND pins to their respective ground planes through vias. • Place current sense resistors and capacitors (RCS and CCS) close to phase IC. Use Kelvin connection for the inductor current sense wires, but separate the two wires by ground polygon. The wire from the inductor terminal to CSIN- should not cross over the fast transition nodes, i.e. switching nodes, gate drive outputs and bootstrap nodes. • Place the decoupling capacitor CVCCL as close as possible to the VCCL pin. • Place the phase IC as close as possible to the MOSFETs to reduce the parasitic resistance and inductance of the gate drive paths. • Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET. Use combination of different packages of ceramic capacitors. • There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor, output capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and the load. Route the switching power paths using wide and short traces or polygons; use multiple vias for connections between layers. To Gate Drive Voltage To Digital Bus LGND PLANE To VIN To Analog Bus To VIN ISHARE R DACIN LGND PHSIN ISHARE PHSIN LGNDDACIN EAIN PHSOUT CLKIN CSIN- - PGND CSIN+ GATEL VCC C VCCL CCS CS C SW SW GATEH VCCLBOOST VCC C RCS C C VCC GATEH BOOST VCCL VCCL D BST CS D To Bottom MOSFET PGND PLANE Page 15 of 19 C BST BST BST C To Switching Node To Top MOSFET To LGND Plane Ground Polygon To Inductor th Sept 26 , 2007 IR3505 PCB Metal and Component Placement • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. • Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. • Center pad land length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥ 0.23mm for 3 oz. Copper) • Four 0.3mm diameter vias shall be placed in the pad land spaced at 0.85mm, and connected to ground to minimize the noise effect on the IC, and to transfer heat to the PCB Page 16 of 19 th Sept 26 , 2007 IR3505 Solder Resist • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads. • The minimum solder resist width is 0.13mm. • At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ≥ 0.17mm remains. • The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. • Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. • The four vias in the land pad should be tented or plugged from bottom board side with solder resist. Page 17 of 19 th Sept 26 , 2007 IR3505 Stencil Design • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. • The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. • The land pad aperture should be approximately 70% area of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands will be open. • The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Page 18 of 19 th Sept 26 , 2007 IR3505 PACKAGE INFORMATION 16L MLPQ (3 x 3 mm Body) – θJA = 38oC/W, θJC = 3oC/W Data and specifications subject to change without notice. This product will be designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com Page 19 of 19 th Sept 26 , 2007