REVISIONS LTR DESCRIPTION A Add device type 02 and case outline Y. - phn Prepared in accordance with ASME Y14.24 DATE APPROVED 10-01-06 Thomas M. Hess Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing YY-MM-DD CHECKED BY TITLE Phu H. Nguyen 07-03-21 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO APPROVED BY MICROCIRCUIT, DIGITAL, DUAL 4-A HIGHSPEED LOW-SLIDE MOSFET DRIVER WITH ENABLE, MONOLITHIC SILICON Thomas M. Hess SIZE CODE IDENT. NO. A REV AMSC N/A DWG NO. V62/07624 16236 A PAGE 1 OF 10 5962-V016-10 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance dual 4-A high-speed low slide MOSFET driver with enable microcircuit, with an extended operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/07624 01 X E Drawing number Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device Generic 01 02 UCC27424-EP UCC27423-EP Circuit function Dual 4-A high-speed low slide MOSFET driver with enable Dual 4-A high-speed low slide MOSFET driver with enable 1.2.2 Case outline(s). The case outline are as specified herein. Outline letter Number of pins JEDEC PUB 95 X Y 8 8 JEDEC MO-187 JEDEC MS-012 Package style Plastic small outline package Plastic small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator A B C D E Z DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/07624 PAGE 2 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VDD) .................................................................................. Maximum output current: OUTA, OUTB: DC, IOUT_DC .............................................................................................. Pulse (0.5 μs), IOUT_PULSE ........................................................................ Input voltage range, INA, INB (VIN) ...................................................................... Enable voltage: ENBA, ENBB .............................................................................. Power dissipation at TA = 25°C: Case outline X ......................................................................................... Case outline Y ......................................................................................... Junction operating temperature range (TJ) ........................................................... Storage temperature range (TSTG)......................................................................... Lead temperature (soldering, 10 s) ...................................................................... -0.3 V to 16.0 V 0.2 A 4.5 A -5 V to 6 V or VDD + 0.3 V 3/ -0.3 V to 6 V or VDD + 0.3 V 3/ 3W 650 mW -55°C to +150°C -65°C to +150°C 300°C Dissipation Rating θJA Case θJC outline (°C/W) X 5/ 4.7 Y 42 84 to 160 344 to 655 mW 6/ 7/ Power rating Derating Factor (°C/W) TA = 70°C Above TA = 70°C 50 to 59 1370 mW 4/ 17.1 mW/°C 4/ 6.25 to 11.9 mW/°C 6/ 7/ 2. APPLICABLE DOCUMENTS JEDEC PUB 95 – Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industry Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or at http://www.jedec.org) 1/ 2/ 3/ 4/ 5/ 6/ 7/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Current are positive into and negative out of the specified terminal. whichever is larger. 150°C operating junction temperature is used for power rating calculations. The package X is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate, which is the ground of the device. The range of value indicates the effect of PC board. These values are intended to give system designer an indication of the best and worst case conditions. In general, the system designer should attempt to use lager traces on the PC board, where possible, in order to spread the heat away from the device more effectively. For more information see manufacturer data. 125°C operating junction temperature is used for power rating calculations. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/07624 PAGE 3 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.5.3 Function table. The function table shall be as specified on figure 3. 3.5.3 Block diagram. The functional block diagram shall be as specified on figure 4. 3.5.4 Switching waveform for Inverting and Noninverting driver. The switching waveforms for inverting and noninverting driver shall be as specified on figure 5. 3.5.5 Switching waveform for enable to output. The switching waveforms for enable to output shall be as specified on figure 6. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/07624 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Input (INA, INB) Logic 1 input threshold Logic 0 input threshold input current Output (OUTA, OUTB) Output current High level output voltage Low level output voltage Symbol VOH VOL 1/ 2/ 3/ 4/ 5/ tR tF tD1 tD2 VDD = 14 V 2/ 3/ VOH = VDD – VOUT, IOUT = -10 mA IOUT = 10 mA IOUT = -10 mA, VDD = 14 V TA = 25ºC 4/ TA = full range IOUT = -10 mA, VDD = 14 V TA = 25ºC 4/ TA = full range CLOAD = 1.8 nF CLOAD = 1.8 nF CLOAD = 1.8 nF CLOAD = 1.8 nF 4 Typ 25 18 1.9 1.2 500 2/ 2/ 2/ 2/ LOW to HIGH transaction HIGH to LOW transaction RENBL tD3 tD4 VDD = 14 V, ENBL = GND CLOAD = 1.8 nF, See figure 5 CLOAD = 1.8 nF, See figure 5 INA = 0 V INA = HIGH INA = 0 V INA = HIGH Min Max 450 40 35 45 2.5 4 2/ 2/ 2.9 2.2 0.9 140 60 150 INB = 0 V INB = HIGH INB = 0 V INB = HIGH INB = 0 V INB = HIGH INB = 0 V INB = HIGH 450 1100 1100 1800 450 700 700 900 V V μA 1 10 -10 4 Typ 450 40 25 35 14 45 1.9 2.5 0.95 4 500 AS mV mV Ω 40 40 55 60 ns 3.1 2.3 1.1 160 60 150 V V V kΩ ns ns 1350 1100 1100 900 450 700 700 900 μA 40 40 50 45 1.7 1.1 0.10 75 Unit 2 1 10 -10 VIN_H VIN_L IDD Max 2 0 V ≤ VIN ≤ VDD Output resistance low Disabled, VDD = 15 V, ENBA = ENBB = 0 V Min VIN_H VIN_L Output resistance high Latch up protection Switching time Rise time (OUTA, OUTB) Fall time (OUTA, OUTB) Delay, IN rising (IN to OUT) Delay IN falling (IN to OUT) Enable (ENBA, ENBB) High level input voltage Low level input voltage Hysteresis Enable impedance Propagation delay time Propagation delay time Overall Static operating current, VDD = 15 V, ENBA = ENBB = 15 V Limits Device type 01 Device type 02 Test conditions 4.5 V ≤ VDD ≤ 15 V -55ºC ≤ TA = TJ ≤ 125ºC unless otherwise specified 1.7 1.1 0.13 75 Ω mA Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Specified by design. Not tested in production. The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET transistors. The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.. The maximum output current depends on the input voltage. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/07624 PAGE 5 Case X Symbol A A1 b c D Millimeters Min Max 1.07 0.05 0.15 0.25 0.38 0.15 NOM 2.95 3.05 Symbol e E E1 L Millimeters Min Max 0.65 BSC 2.95 3.05 4.78 4.98 0.41 0.69 Notes: 1. All liner dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. 4. The package is designed to be soldered to a thermal pad on the board. See manufacturer data for details regarding the exposed thermal pad dimensions. 5. Falls within JEDEC MO-187. FIGURE 1. Case outline. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/07624 PAGE 6 Case Y Symbol Inches Min Max Dimensions Millimeters Symbol Min Max Inches Min Max Millimeters Min Max A A1 A2 b c .069 .004 .010 .010 TYP .012 .020 .005 .010 1.75 0.10 0.25 0.25 TYP 0.31 0.51 0.13 0.25 .189 .197 .150 .157 .228 .244 .050 BSC .016 .050 4.80 5.00 3.80 4.00 5.80 6.20 1.27 BSC 0.40 1.27 D E E1 e L Notes: 1. All liner dimensions are in inch (millimeters). 2. This drawing is subject to change without notice. 3. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 (0.15) per end.. 4. Body width does not include interlead flash. Interlead flash shall not exceed .017 (0.43) per side. 5. Falls within JEDEC MS-012 variation AA. FIGURE 1. Case outline - Continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/07624 PAGE 7 Case X and Y Terminal number Terminal symbol Terminal number Terminal symbol 1 2 3 4 ENBA INA GND INB 5 6 7 8 OTUB VDD OUTA ENBB FIGURE 2. Terminal connections. ENBA ENBB H H H H L H H H H L Inputs (VIN_L, VIN_H) INA INB L L H H X L H L H X Outputs OUTA OUTB L L H H L L H L H L FIGURE 3. Function table. FIGURE 4. Block diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/07624 PAGE 8 Note: The 10% and 90% threshold depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of the operation. FIGURE 5. Switching waveform for Inverting and Noninverting driver. Note: The 10% and 90% threshold depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of the operation. FIGURE 6. Switching waveform for enable to output DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/07624 PAGE 9 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ V62/07624-01XE V62/07624-02YE 1/ Device manufacturer CAGE code 01295 01295 Vendor part number UCC27424MDGNREP UCC27423MDREP The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 01295 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/07624 PAGE 10