REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV 1 PAGE 2 3 PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing YY MM DD CHECKED BY 09-05-20 Phu H. Nguyen APPROVED BY Thomas M. Hess SIZE A REV AMSC N/A 4 CODE IDENT. NO. 5 6 7 8 9 10 11 12 13 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 TITLE MICROCIRCUIT, DIGITAL RECEIVER, MONOLITHIC SILICON DWG NO. V62/09627 16236 PAGE 1 OF 13 5962-V055-09 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance digital receiver microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09627 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 TFP401A-EP Circuit function Digital receiver 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 X 100 MS-026 Package style Plastic Quad Flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE CODE IDENT NO. DWG NO. A 16236 V62/09627 REV PAGE 2 1.3 Absolute maximum ratings. 1/ Supply voltage, (DVDD, AVDD, OVDD, PVDD) .......................................................................... Input voltage, logic/analog signals ....................................................................................... Storage temperature range (TSTG) ....................................................................................... Operating temperature range ............................................................................................... Case temperature for 10 s ................................................................................................... Lead temperature (1.6 mm (1/16 in) from the case for 10 s) ............................................... Maximum package power dissipation: Soldered ....................................................................................................................... Not soldered ................................................................................................................. ESD protection, all pins ........................................................................................................ JEDEC latch up (EIA/JESD78) ............................................................................................ -0.3 V to 4.0 V -0.3 V to 4.0 V -65°C to 150°C -55°C to 125°C 260°C 260°C 2/ 4.3 W 3/ 2.7 W 4/ 25 kV, Human Body model 100 mA 1.4 Recommended operating conditions. 5/ Supply voltage VDD, (DVDD, AVDD, PVDD, OVDD) ................................................................... Pixel time, (tpix) ..................................................................................................................... Single ended analog input termination resistance, ............................................................. Operating free air temperature, (TA) ..................................................................................... 1/ 2/ 3/ 4/ 5/ 6/ 3.0 V to 3.6 V 6.06 ns to 40 ns 45 Ω to 75 Ω -55°C to 125°C 6/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. Specified with the bond pad on the backside of the package soldered to a 2 oz. Cu plate PCB thermal plane. Specified at maximum allowed operating temperature, 70°C. The bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating temperature, 70°C. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to tpix when in 1-pixel/clock mode and 2tpix when in 2-pixel/clock mode. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/09627 REV PAGE 3 2. APPLICABLE DOCUMENTS JEDEC PUB 95 – Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Function block diagram. The functional block diagram shall be as shown in figure 3. 3.5.4 Timing diagram. The timing diagram shall be as shown in figure 4-10. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/09627 REV PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol DC Specifications High level digital input voltage Low level digital input voltage VIH VIL High level output drive current IOH Low level output drive current IOL Hi-Z output leakage current IOZ Analog input differential voltage 3/ Analog input common mode voltage 3/ Open circuit analog input voltage Normal 2-pix/clock power supply current Power down current 5/ Output drive power down current Conditions 2/ ST = High ST = Low ST = High ST = Low Limits 4/ 5/ AC Specifications Differential input sensitivity 6/ Analog input intra pair (+ to -) differential skew 7/ Analog input inter pair or channel to channel skew 7/ Worse case differential input clock jitter tolerance 10/ 7/ 11/ IDD(2PIX) IPD IPDO Max 2 0 5 3 8 4 -1 DVDD 0.8 16.3 10.3 19 11 1 75 AVDD-300 AVDD-10 1200 AVDD-37 AVDD+10 370 10 PD = low or PDO = Low ODCK = 82.5 MHz 2-pix/clock PD = low 35 TYP PDO = Low VID 7/ tps tccs 150 tijit 50 Fall time of data and control signals 12/ 13/ 11/ tf1 Rise time of data and control signals 12/ 13/ 11/ tr1 Rise time of ODCK clock 11/ 12/ tr2 Fall time of ODCK clock 11/ 12/ tf2 Setup time, data and control signal to falling edge of ODCK 11/ Min VOH = 2.4 V VOH = 2.4 V VOL = 0.8 V VOL = 0.8 V VID VIC VI(OC) tsu1 Unit ST = Low, CL = 5 pF ST = High, CL = 10 pF ST = Low, CL = 5 pF ST = High, CL = 10 pF ST = Low, CL = 5 pF ST = High, CL = 10 pF ST = Low, CL = 5 pF ST = High, CL = 10 pF 1 pixel/clock, PIXS = low, OCK_INV = low 2 pixel/clock, PIXS = high, V mA µA mV mV mV mA mA mA 1560 0.4 1 mVp-p tbit 8/ tpix 9/ ps 2.4 1.9 2.4 1.9 2.4 1.9 2.4 1.9 ns 1.8 3.8 STAG = high, OCK_INV = low 2 pixel and STAG , PIXS = high, 0.6 STAG = low, OCK_INV = low See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/09627 REV PAGE 5 TABLE I. Electrical performance characteristics – Continued. Test Symbol Conditions 2/ Limits Min Unit Max AC Specifications Hold time, data and control signal to falling edge of ODCK 11/ th1 1 pixel/clock, PIXS = low, OCK_INV = low 0.6 2 pixel and STAG , PIXS = high, 2.5 ns STAG = low, OCK_INV = low 2 pixel/clock, PIXS = high, 2.9 STAG = high, OCK_INV = low Setup time, data and control signal to rising edge of ODCK 11/ tsu2 1 pixel/clock, PIXS = low, OCK_INV = high 2 pixel/clock, PIXS = high, 2.1 4 STAG = high, OCK_INV = high 2 pixel and STAG , PIXS = high, 1.5 STAG = low, OCK_INV = high Hold time, data and control signal to rising edge of ODCK 11/ th2 1 pixel/clock, PIXS = low, OCK_INV = high 0.3 2 pixel and STAG , PIXS = high, 2.4 STAG = low, OCK_INV = high 2 pixel/clock, PIXS = high, 2.1 STAG = high, OCK_INV = high ODCK frequency fODCK ODCK duty-cycle Propagation delay time from PD low to Hi-Z outputs 11/ tpd(PDL) 1/ PIX = low (1-PIX/CLK) PIX = High (2-PIX/CLK) 25 12.5 45% 165 82.5 75% 9 MHz ns Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Over operating free air temperature range, (unless otherwise noted). Specified as dc characteristic with no overshoot or undershoot. 2/ 3/ 4/ 5/ 6/ 7/ 8/ 9/ 10/ 11/ 12/ 13/ Alternating 2-pixel black/2-pixel white patter. ST = high, STAG = high, QE[23:0] and QO[23:0] CL = 10 pF. Analog inputs are open circuit (transmitter is disconnected from (TFP401A). Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection. By characterization. tbit is 1/10 the pixel time, tpix. tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in 2-pixel/clock mode. Measured differentially at 50% crossing using ODCK output clock as trigger. Not production test. Rise and fall time measured as time between 20% and 80% of signal amplitude. Data and control signals are: QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[3:1]. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/09627 REV PAGE 6 Case X Symbol A A1 A2 A3 b c Dimension Millimeters Symbol Min Max 1.20 D/E 0.95 1.05 D1/E1 0.25 Typ D2/E2 0.05 0.15 e 0.17 0.27 L1 0.13 NOM Millimeters Min Max 15.80 16.20 13.80 14.20 12.00 Typ 0.50 NOM 0.45 0.75 NOTES: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. 4. This package is designed to be soldered to a thermal pad on the board. Refer to the manufacturer data for information regarding recommended board layout. 5. Falls within JEDEC MS-026. FIGURE 1. Case outline. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/09627 REV PAGE 7 Case X Terminal number 1 2 3 4 5 6 7 Terminal symbol DFO PD ST PIXS GND DVDD STAG Terminal number 26 27 Terminal symbol QE14 QE15 Terminal number 51 52 Terminal symbol QO2 QO3 Terminal number 76 77 Terminal symbol OGND QO23 28 29 30 31 32 OGND OVDD QE16 QE17 QE18 53 54 55 56 57 QO4 QO5 QO6 QO7 OVDD 78 79 80 81 82 OVDD AGND Rx2+ Rx2AVDD QE19 QE20 58 59 OGND QO8 83 84 AGND AVDD QE21 QE22 QE23 DVDD GND CTL1 CTL2 CTL3 OVDD ODCK OGND DE VSYNC HSYNC QO0 QO1 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 QO9 QO10 QO11 QO12 QO13 QO14 QO15 DVDD GND QO16 QO17 QO18 QO19 QO20 QO21 QO22 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Rx1+ Rx1AGND AVDD AGND Rx0+ Rx0AGND RxC+ RxCAVDD EXT RES PVDD PGND RSVD OCK_INV 8 9 SCDT PDO 33 34 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 OVDD OGND QE8 QE9 QE10 QE11 QE12 QE13 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 FIGURE 2. Terminal connections. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/09627 REV PAGE 8 FIGURE 3. Functional block diagram. FIGURE 4. Timing diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/09627 REV PAGE 9 FIGURE 5. Timing diagram. FIGURE 6. Timing diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/09627 REV PAGE 10 FIGURE 7. Timing diagram. FIGURE 8. Timing diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/09627 REV PAGE 11 FIGURE 9 Timing diagram. FIGURE 10 Timing diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/09627 REV PAGE 12 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. 1/ Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/09627-01XE 01295 TFP401AMPZPEP The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 01295 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE CODE IDENT NO. DWG NO. A 16236 V62/09627 REV PAGE 13