INTEGRATED CIRCUITS FB2031 9-bit latched/registered/pass-thru Futurebus+ transceiver Product specification IC19 Data Handbook 1995 May 25 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver • Reduced BTL voltage swing produces less FEATURES • Latched, registered or straight through in • Controlled output ramp and multiple GND noise and reduces power consumption pins minimize ground bounce • Built-in precision band-gap reference either A to B or B to A path • Drives heavily loaded backplanes with • Glitch-free power up/power down operation • Low ICC current • Tight output skew • Supports live insertion provides accurate receiver thresholds and improved noise immunity equivalent load impedances down to 10Ω. • Compatible with IEEE Futurebus+ or • High drive 100mA BTL open collector proprietary BTL backplanes drivers on B-port • Each BTL driver has a dedicated Bus GND • Allows incident wave switching in heavily FB2031 for a signal return loaded backplane buses QUICK REFERENCE DATA SYMBOL TYPICAL UNIT tPLH tPHL Propagation delay An to Bn 2.7 ns tPLH tPHL Propagation delay Bn to An 4.4 4.2 ns CO Output capacitance (B0 – Bn only) IOL Output current (B0 – Bn only) ICC PARAMETER S Supply l currentt 6 pF 100 mA AIn to Bn (outputs Low or High) 17 mA Bn to AOn (outputs Low) 50 mA Bn to AOn (outputs High) 25 ORDERING INFORMATION PACKAGE COMMERCIAL RANGE VCC = 5V±10%; Tamb = 0°C to +70°C INDUSTRIAL RANGE VCC = 5V±10%; Tamb = –40°C to +85°C DRAWING NUMBER 52-pin Plastic Quad Flat Pack (QFP) FB2031BB CD3206BB SOT379-1 B0 TMS (option) BUS GND TCK (option) VCC OEB1 OEA OEB0 BIAS V VCC LOGIC GND A0 A1 PIN CONFIGURATION 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 A2 2 38 B1 LOGIC GND 3 37 BUS GND A3 4 36 B2 LOGIC GND 5 9-Bit latched/registered transceiver 35 BUS GND A4 6 FB2031 34 B3 LOGIC GND 7 33 BUS GND 32 B4 31 BUS GND A5 8 LOGIC GND 9 A6 10 30 B5 LOGIC GND 11 29 BUS GND A7 12 28 B6 13 27 BUS GND 52-lead PQFP 2 B7 B8 BUS GND VCC TDI (option) TDO (option) SEL0 LCAB BG GND 16 17 18 19 20 21 22 23 24 25 26 BG VCC A8 SEL1 14 15 LCBA LOGIC GND 1995 May 25 BUS GND LOGIC GND SG00060 853-1714 15279 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver DESCRIPTION The FB2031 is a 9-bit latched/registered transceiver featuring a latched, registered or pass-thru mode in either the A-to-B or B-to-A direction. The FB2031 is intended to provide the electrical interface to a high performance wired-OR bus. The TTL-level side (A port) has a common I/O. The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two mode select inputs (SEL0 and SEL1). A “00” configures latches in both directions. A “10” configures thru mode in both directions. A “01” configures register mode in both directions. A “11” configures register mode in the A-to-B direction and latch mode in the B-to-A direction. When configured in the buffer mode, the inverse of the input data appears at the output port. In the register mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-Low latch enables. Regardless of the mode, data is inverted from input to output. The 3-State A port is enabled by asserting a High level on OEA. The B port has two output enables, OEB0 and OEB1. Only when OEB0 is High and OEB1 is Low is the output enabled. When either OEB0 is Low or OEB1 is High, the B port is inactive and is pulled to the level of the pullup voltage. New data can be entered in the register and latched modes or can be retained while the associated outputs are in 3-State (A port) or inactive (B port). The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. The B-port interfaces to “Backplane Transceiver Logic” (see the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. Output clamps are provided on the BTL outputs to further reduce switching noise. The “VOH” clamp reduces inductive ringing effects during a Low-to-High transition. The “VOH” clamp is always active. The other clamp, the “trapped reflection” clamp, clamps out ringing below the BTL 0.5V VOL level. This clamp remains active for approximately 100ns after a High-to-Low transition. FB2031 To support live insertion, OEB0 is held Low during power on/off cycles to insure glitchfree B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL Standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a “hard” signal failure occurs instead of a pattern dependent error that may be infrequent and impossible to troubleshoot. As with any high power device, thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature. PACKAGE THERMAL CHARACTERISTICS PARAMETER θja θja θjc CONDITION Still air 300 Linear feet per minute air flow Thermally mounted on one side to heat sink 52-PIN PLASTIC QFP 80°C/W 58°C/W 20°C/W PIN DESCRIPTION SYMBOL A0 – A8 B0 – B8 OEB0 OEB1 OEA BUS GND LOGIC GND VCC BIAS V BG VCC BG GND SEL0 SEL1 LCAB LCBA TMS TCK TDI TDO 1995 May 25 PIN NUMBER 50, 52, 2, 4, 6, 8, 10, 12, 14 40, 38, 36, 34, 32, 30, 28, 26, 24 46 45 47 25, 27, 29, 31, 33, 35, 37, 39, 41 51, 1, 3, 5, 7, 9, 11, 13 23, 43, 49 48 17 19 20 15 18 16 42 44 22 21 TYPE I/O NAME AND FUNCTION BiCMOS data inputs/3-State outputs (TTL) I/O Data inputs/Open Collector outputs, High current drive (BTL) Input Input Input Enables the B outputs when High Enables the B outputs when Low Enables the A outputs when High GND Bus ground (0V) GND Power Power Power GND Input Input Input Input Input Input Input Output Logic ground (0V) Positive supply voltage Live insertion pre-bias pin Band Gap threshold voltage reference Band Gap threshold voltage reference ground Mode select Mode select A to B clock/latch enable (transparent latch when Low) B to A clock/latch enable (transparent latch when Low) Test Mode Select (optional, if not implemented then no connect) Test Clock (optional, if not implemented then no connect) Test Data In (optional, if not implemented then no connect) Test Data Out (optional, if not implemented then shorted to TDI) 3 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver FB2031 FUNCTION TABLE MODE An to Bn thru mode An to Bn transparent latch An to Bn latch and read Bn outputs latched and read (preconditioned latch) An to Bn register Bn to An thru mode Bn to An transparent latch Bn to An latch and read An outputs latched and read (preconditioned latch) Bn to An register Disable Bn outputs Disable An outputs INPUTS OUTPUTS An Bn* OEB0 OEB1 OEA LCAB LCBA SEL0 SEL1 An Bn L — H L L X X H L input H** H — H L L X X H L input L L — H L L L X L L input H** H — H L L L X L L input L l — H L L ↑ X L L input H** h — H L L ↑ X L L input L X — H L X H X L L X latched data H** l — H L L ↑ X X H input h — H L L ↑ X X H input L — L Disable H X X H L H input — H Disable H X X H L L input — L Disable H X L L L H input — H Disable H X L L L L input — L Disable H X L H H H input — H Disable H X L H H L input — l Disable H X ↑ L L H input — h Disable H X ↑ L L L input — l Disable H X ↑ H H H input — h Disable H X ↑ H H L input X — X X X H X H L L latched data — X X X H X H H H latched data X — l Disable H X ↑ L H H input — h Disable H X ↑ L H L input X X L X X X X X X X H** X X X H X X X X X X H** X X X X L X X X X Z X FUNCTION SELECT TABLE MODE SELECTED SEL0 H L Register mode (An to Bn) X H Latch mode (An to Bn) L L Register mode (Bn to An) L H Latch mode (Bn to An) NOTES: H = High voltage level L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High LCXX transition h = High voltage level one set-up time prior to the Low-to-High LCXX transition 1995 May 25 SEL1 Thru mode X Z — ↑ H** = = = = = L L H H Don’t care High-impedance (OFF) state Input not externally driven Low-to-High transition Goes to level of pull-up voltage 4 Bn* = Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state. Disable = OEB0 is Low or OEB1 is High. Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver FB2031 LOGIC DIAGRAM OEB0 OEB1 OEA 46 45 47 D Q E D A8 14 Q MUX 24 MUX Q Q A⇐ B D DD E Q Q D Clk E D A7 12 Q 26 MUX A⇒ B Clk 30 MUX Q A⇐ B 8 Q D 2 D E 6 4 Q 32 D 34 36 E D Q 38 B1 MUX A⇒ B 52 MUX Q A⇐ B D D E Q Q D Clk E D Q 40 MUX Clk A0 B0 A⇒ B 50 MUX Q A⇐ B LCAB 18 SEL0 20 Decode SEL1 15 In LCBA 16 TMS TCK TDI TDO 42 44 22 21 D E Q 1995 May 25 BTL Clk Clk A1 B7 28 10 TTL B8 A⇒ B Clk D Clk Out LOGIC GND BUS GND BIAS V VCC BG VCC BG GND (JTAG Boundary Scan pins) 5 = = = = = = 1, 3, 5, 7, 9, 11, 13, 51 25, 27, 29, 31, 33, 35, 37, 39, 41 48 23, 43, 49 17 19 SG00061 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver FB2031 ABSOLUTE MAXIMUM RATINGS Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL PARAMETER VCC Supply voltage VIN Input voltage IIN RATING UNIT -0.5 to +7.0 V All inputs except B0 – B8 -1.2 to +7.0 V B0 – B8 -1.2 to +3.5 Input current -40 to +5.0 VOUT Voltage applied to output in High output state IOUT Current applied to output in Low output state TSTG Storage temperature mA -0.5 to +VCC V 48 mA A0 – A8 B0 – B8 200 -65 to +150 °C RECOMMENDED OPERATING CONDITIONS (Industrial) SYMBOL PARAMETER VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage IIK Input clamp current LIMITS UNIT MIN TYP MAX 4.5 5.0 5.5 Except B0–B8 2.0 B0 – B8 1.62 V V 1.55 Except B0 – B8 0.8 B0 – B8 1.47 Control inputs -40 B0 – B8 & A0 – A8 -18 V mA IOH High-level output current A0 – A8 -3 mA IOL Low-level output current A0 – A8 24 mA B0 – B8 100 Except B0 – B8, VI = 0 to 5.5V, VCC = 0V 100 µA 7 pF +85 °C IIA Off device input current COB Output capacitance of B port Tamb Operating free-air temperature range 6 –40 RECOMMENDED OPERATING CONDITIONS (Commercial) SYMBOL PARAMETER VCC Supply voltage VIH High-level input voltage VIL IIK Low-level input voltage Input clamp current LIMITS UNIT MIN TYP MAX 4.5 5.0 5.5 Except B0–B8 2.0 B0 – B8 1.62 V V 1.55 Except B0 – B8 0.8 B0 – B8 1.47 Control inputs -40 B0 – B8 & A0 – A8 -18 V mA IOH High-level output current A0 – A8 -3 mA IOL Low-level output current A0 – A8 24 mA B0 – B8 100 Except B0 – B8, VI = 0 to 5.5V, VCC = 0V 100 µA 7 pF +70 °C IIA Off device input current COB Output capacitance of B port Tamb Operating free-air temperature range 1995 May 25 6 0 6 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver FB2031 DC ELECTRICAL CHARACTERISTICS (Industrial) Over recommended operating free-air temperature range unless otherwise noted. SYMBOL TEST CONDITIONS1 PARAMETER LIMITS MIN TYP2 UNIT MAX IOH High level output current B0 – B8 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 1.9V 100 µA IOFF Power-off output current B0 – B8 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 1.9V 200 µA VOH High-level output voltage A0 – A8 4 VCC = MIN, VIL = MAX, VIH = MIN, IOH = -24mA 2.0 VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA 2.5 2.85 .75 1.0 VOL Low-level output voltage A0 – A8 4 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA B0 – B8 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA V 0.5 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA VIK Input clamp voltage 1.15 0.5 Control pins VCC = MIN, II = IIK -0.5 A0 – A8 B0 – Bn VCC = MIN, II = -18mA -1.2 V µA II Input current at maximum input voltage Except B0–B8 VCC = MAX, VI = 0.5V or 5.5V ±50 20 High-level input current Except B0–B8 VCC = MAX, VI = 2.7V IIH B0 – B8 VCC = MAX, VI = 1.9V 100 VCC = MAX, VI = 3.5V 5 IIL Low-level input current 100 VCC = MAX, VI = 0.5V -20 B0 – B8 VCC = MAX, VI = 0.75V -100 50 Off-state I/O High current A0 – A8 VCC = MAX, VO = 2.7V IIL + IOZL Off-state I/O Low current A0 – A8 VCC = MAX, VO = 0.5V Short-circuit output current 3 A0 – A8 only VCC = MAX, VO = 0.0V An to Bn VCC = MAX, outputs Low or High 17 30 Bn to An VCC = MAX, outputs Low 50 78 Bn to An VCC = MAX, outputs High 25 45 ICCZ VCC = MAX, outputs 3-State 28 50 Worst case VCC = MAX, all A and B outputs on 50 78 ICC Supply current (total) µA mA Except B0–B8 IIH + IOZH IOS V 1.15 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 4mA 1.1 -45 µA µA -50 µA -150 mA mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 5. For B port input voltage between 3 and 5 volts IIH will be greater than 100µA, but the parts will continue to function normally. 6. B0 – B8 clamps remain active for a minimum of 80ns following a High-to-Low transition. 7. Temperature range: 0 to +85°C. 8. Temperature range: –40 to 0°C. 1995 May 25 7 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver FB2031 DC ELECTRICAL CHARACTERISTICS (Commercial) Over recommended operating free-air temperature range unless otherwise noted. SYMBOL TEST CONDITIONS1 PARAMETER LIMITS MIN TYP2 MAX UNIT IOH High level output current B0 – B8 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 1.9V 100 µA IOFF Power-off output current B0 – B8 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 1.9V 100 µA VOH O High level output voltage High-level A0 – A8 4 A0 – A8 4 VOL O Low level output voltage Low-level VCC = MIN, VIL = MAX, VIH = MIN, IOH = -24mA 2.0 VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA 2.5 2.85 .75 1.0 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA B0 – B8 VIK II IIH 1.1 1.15 VCC = MIN, II = IIK -0.5 Input clamp voltage A0 – A8 B0 – Bn VCC = MIN, II = -18mA -1.2 Input current at maximum input voltage Except B0–B8 VCC = MAX, VI = 0.0V or 5.5V ±50 Except B0–B8 VCC = MAX, VI = 2.7V 20 VCC = MAX, VI = 1.9V 100 Hi h l l input i t currentt High-level Low-level input current VCC = MAX, VI = 3.5V 5 V 0.5 Control pins B0 – B8 IIL 0.5 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 4mA V 100 V µA µA mA Except B0–B8 VCC = MAX, VI = 0.5V -20 B0 – B8 VCC = MAX, VI = 0.75V -100 µA µ IIH + IOZH Off-state I/O High current A0 – A8 VCC = MAX, VO = 2.7V 50 µA IIL + IOZL Off-state I/O Low current A0 – A8 VCC = MAX, VO = 0.5V -50 µA Short-circuit output current 3 A0 – A8 only VCC = MAX, VO = 0.0V -150 mA An to Bn VCC = MAX, outputs Low or High 17 30 Bn to An VCC = MAX, outputs Low 50 78 Bn to An VCC = MAX, outputs High 25 45 ICCZ VCC = MAX, outputs 3-State 28 50 Worst case VCC = MAX, all A and B outputs on 50 78 IOS ICC Supply current (total) -45 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 5. For B port input voltage between 3 and 5 volts IIH will be greater than 100µA, but the parts will continue to function normally. 6. B0 – B8 clamps remain active for a minimum of 80ns following a High-to-Low transition. 1995 May 25 8 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver FB2031 LIVE INSERTION SPECIFICATIONS SYMBOL VBIASV IBIASV LIMITS PARAMETER Bias pin voltage Bias pin in DC current MIN VCC = 0 to 5.25V, Bn = 0 to 2.0V NOM 4.5 MAX UNIT 5.5 V VCC = 0 to 4.75V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V 1 mA VCC = 4.5 to 5.5V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V 10 µA VBn Bus voltage during prebias B0 – B8 = 0V, Bias V = 5.0V ILM Fall current during prebias B0 – B8 = 2V, Bias V = 4.5 to 5.5V 1 µA IHM Rise current during prebias B0 – B8 = 1V, Bias V = 4.5 to 5.5V -1 µA IBnPEAK Peak bus current during insertion VCC = 0 to 5.25V, B0 – B8 = 0 to 2.0V, Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns 10 mA IOLOFF Power up u current VCC = 0 to 5.25V, OEB0 = 0.8V 100 VCC = 0 to 2.2V, OEB0 = 0 to 5V 100 µA tGR Input glitch rejection 1.62 VCC = 5.0V 2.1 1.35 V 1.0 ns AC ELECTRICAL CHARACTERISTICS (Industrial) A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, CL = 50pF, RL = 500Ω MIN TYP 120 150 Propagation delay (thru mode) Bn to An Waveform 1, 2 2.5 2.4 4.4 4.2 5.9 5.5 2.3 2.4 7.0 6.2 ns tPLH tPHL Propagation delay (transparent latch) Bn to An Waveform 1, 2 2.9 2.8 4.6 4.3 6.2 5.9 2.7 2.5 7.1 7.0 ns tPLH tPHL Propagation delay LCBA to An Waveform 1, 2 2.6 2.4 4.1 4.7 5.5 6.1 2.0 2.0 6.2 6.8 ns tPLH tPHL Propagation delay SEL0 or SEL1 to An Waveform 1, 2 1.5 1.7 3.8 3.9 5.2 6.0 1.2 1.5 6.2 6.5 ns tPZH tPZL Output enable time from High or Low OEA to An Waveform 5, 6 2.1 2.0 3.5 3.8 4.8 5.3 1.8 1.7 6.0 6.3 ns tPHZ tPLZ Output disable time to High or Low OEA to An Waveform 5, 6 1.9 1.7 3.4 3.2 4.8 4.8 1.6 1.5 5.5 5.5 ns tTLH tTHL Output transition time, An Port 10% to 90%, 90% to 10% Test Circuit and Waveforms 3.0 1.7 7.5 4.0 ns Maximum clock frequency tPLH tPHL tSK(o) tSK(p) Output to output skew for multiple channels1 2 Pulse skew tPHL – tPLH MAX MIN UNIT Waveform 4 fMAX MAX Tamb = –40 to +85°C, VCC = 5V±10%, CL = 50pF, RL = 500Ω MAX 100 MHz Waveform 3 0.5 1.0 1.5 ns Waveform 2 0.5 1.0 1.0 ns NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 5. For B port input voltage between 3 and 5 volts IIH will be greater than 100µA, but the parts will continue to function normally. 6. B0 – B8 clamps remain active for a minimum of 80ns following a High-to-Low transition. 1995 May 25 9 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver FB2031 AC ELECTRICAL CHARACTERISTICS (Industrial) B PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, CD = 30pF, RU = 16.5Ω Tamb = –40 to +85°C, VCC = 5V±10%, CD = 30pF, RU = 16.5Ω UNIT MIN TYP MAX MIN MAX Waveform 1, 2 1.0 1.0 3.0 2.7 5.0 4.0 1.5 1.5 5.7 4.5 ns Propagation delay (transparent latch) An to Bn Waveform 1, 2 1.0 1.0 3.2 3.1 5.0 4.2 1.5 1.5 5.5 5.0 ns tPLH tPHL Propagation delay LCAB to Bn Waveform 1, 2 2.0 1.5 4.0 4.0 5.5 5.5 1.5 1.5 6.5 6.0 ns tPLH tPHL Propagation delay SEL0 or SEL1 to Bn Waveform 1, 2 2.0 1.5 3.5 2.3 5.5 4.5 2.0 1.0 6.1 5.5 ns tPZH tPZL Enable/disable time OEB0 or OEB1 to Bn Waveform 1, 2 1.5 1.2 3.0 2.4 5.0 4.5 1.0 1.0 5.7 5.5 ns tTLH tTHL Output transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.0 0.6 2.0 3.0 0.9 0.6 3.0 3.0 ns tSK(o) Output to output skew for multiple channels1 Waveform 3 1.0 1.6 1.6 ns 1.5 ns tPLH tPHL Propagation delay (thru mode) An to Bn tPLH tPHL tSK(p) skew2 Pulse tPHL – tPLH MAX Waveform 2 0.4 0.3 1.0 NOTES: 1. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only). 1995 May 25 10 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver FB2031 AC ELECTRICAL CHARACTERISTICS (Commercial) A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, CL = 50pF, RL = 500Ω MIN TYP 120 150 Propagation delay (thru mode) Bn to An Waveform 1, 2 2.5 2.4 4.4 4.2 5.9 5.5 2.3 2.4 6.6 5.9 ns tPLH tPHL Propagation delay (transparent latch) Bn to An Waveform 1, 2 2.9 2.8 4.6 4.3 6.2 5.9 2.7 2.5 7.0 6.5 ns tPLH tPHL Propagation delay LCBA to An Waveform 1, 2 2.6 2.4 4.1 4.7 5.5 6.1 2.0 2.0 6.0 6.5 ns tPLH tPHL Propagation delay SEL0 or SEL1 to An Waveform 1, 2 1.5 1.7 3.8 3.9 5.2 6.0 1.2 1.5 6.0 6.5 ns tPZH tPZL Output enable time from High or Low OEA to An Waveform 5, 6 2.1 2.0 3.5 3.8 4.8 5.3 1.8 1.7 5.8 6.0 ns tPHZ tPLZ Output disable time to High or Low OEA to An Waveform 5, 6 1.9 1.7 3.4 3.2 4.8 4.8 1.6 1.5 5.4 5.4 ns tTLH tTHL Output transition time, An Port 10% to 90%, 90% to 10% Test Circuit and Waveforms 2.0 1.0 7.5 3.5 ns Maximum clock frequency tPLH tPHL MIN UNIT Waveform 4 fMAX MAX Tamb = 0 to +70°C, VCC = 5V±10%, CL = 50pF, RL = 500Ω MAX 100 MHz tSK(o) Output to output skew for multiple channels1 Waveform 3 0.5 1.0 1.5 ns tSK(p) Pulse skew 2 tPHL – tPLH MAX Waveform 2 0.5 1.0 1.0 ns NOTES: 1. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only). 1995 May 25 11 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver FB2031 AC ELECTRICAL CHARACTERISTICS (Commercial) B PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, CD = 30pF, RU = 16.5Ω Tamb = 0 to +70°C, VCC = 5V±10%, CD = 30pF, RU = 16.5Ω UNIT MIN TYP MAX MIN MAX Waveform 1, 2 1.0 1.0 3.0 2.7 5.0 4.0 1.0 0.5 5.5 4.5 ns Propagation delay (transparent latch) An to Bn Waveform 1, 2 1.0 1.0 3.2 3.1 5.0 4.2 1.0 0.8 5.5 4.5 ns tPLH tPHL Propagation delay LCAB to Bn Waveform 1, 2 2.0 1.5 4.0 4.0 5.5 5.5 1.5 1.0 6.0 6.0 ns tPLH tPHL Propagation delay SEL0 or SEL1 to Bn Waveform 1, 2 2.0 1.5 3.5 2.3 5.5 4.5 2.0 1.0 6.0 5.0 ns tPZH tPZL Enable/disable time OEB0 or OEB1 to Bn Waveform 1, 2 1.5 1.5 3.0 2.4 5.0 4.5 1.0 0.8 5.5 5.5 ns tTLH tTHL Output transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.0 0.6 2.0 3.0 1.0 0.6 2.3 2.3 ns tSK(o) Output to output skew for multiple channels1 tPLH tPHL Propagation delay (thru mode) An to Bn tPLH tPHL tSK(p) skew2 Pulse tPHL – tPLH MAX Waveform 3 0.4 1.0 1.6 ns Waveform 2 0.3 1.0 1.5 ns NOTES: 1. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only). AC SETUP REQUIREMENTS (Industrial) LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, Tamb = –40 to +85°C, VCC = 5V±10%, UNIT CL = 50pF (A side) / CD = 30pF (B side) RL = 500Ω (A side) / RU = 16.5Ω (B side) MIN TYP MAX MIN MAX ts(H) ts(L) Setup time An to LCAB Waveform 4 1.0 1.0 1.5 1.0 ns th(H) th(L) Hold time An to LCAB Waveform 4 1.0 1.0 2.0 1.0 ns ts(H) ts(L) Setup time Bn to LCBA Waveform 4 2.0 2.0 3.0 3.0 ns th(H) th(L) Hold time Bn to LCBA Waveform 4 0.0 0.0 0.0 0.0 ns tw(H) tw(L) Pulse width, High or Low LCAB or LCBA Waveform 4 3.0 3.0 3.0 3.0 ns 1995 May 25 12 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver FB2031 AC SETUP REQUIREMENTS (Commercial) LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, Tamb = 0 to +70°C, VCC = 5V±10%, UNIT CL = 50pF (A side) / CD = 30pF (B side) RL = 500Ω (A side) / RU = 16.5Ω (B side) MIN TYP MAX MIN MAX ts(H) ts(L) Setup time An to LCAB Waveform 4 1.0 1.0 1.5 1.0 ns th(H) th(L) Hold time An to LCAB Waveform 4 1.0 1.0 2.0 1.0 ns ts(H) ts(L) Setup time Bn to LCBA Waveform 4 2.0 2.0 3.0 3.0 ns th(H) th(L) Hold time Bn to LCBA Waveform 4 0.0 0.0 0.0 0.0 ns tw(H) tw(L) Pulse width, High or Low LCAB or LCBA Waveform 4 3.0 3.0 3.0 3.0 ns 1995 May 25 13 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver FB2031 AC WAVEFORMS VM Input tPLH VM Output tPLH tw (output) VM VM Waveform 2. Propagation Delay for Data or Output Enable to Output ÍÍ ÍÍÍÍ ÍÍ ÍÍÍÍÍÍ ÍÍ An, Bn VM VM ts tSK(o) An, Bn VM tw (input) tPHL Waveform 1. Propagation Delay for Data or Output Enable to Output An, Bn VM tPHL VM Output Input VM LCAB, LCBA VM th VM ts tw(L) tw(H) th VM 1/fMAX Waveform 3. Output to Output Skew OEA VM VM tPZH An Waveform 4. Setup and Hold Times, Pulse Widths and Maximum Frequency OEA tPHZ VM VOH -0.3V tPZL OV An Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level tPLZ VM VOL +0.3V Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level NOTE: VM = 1.55V for Bn, VM = 1.5V for all others. The shaded areas indicate when the input is permitted to change for predictable output performance. 1995 May 25 VM VM 14 SG00062 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver FB2031 TEST CIRCUIT AND WAVEFORMS VCC VIN RL VOUT PULSE GENERATOR tW 90% 7.0V NEGATIVE PULSE VM VM 10% D.U.T. RT CL AMP (V) 90% RL 10% tTHL (tf) tTLH (tr) LOW V tTLH (tr) tTHL (tf) AMP (V) 90% 90% POSITIVE PULSE Test Circuit for 3-State Outputs on A Port LOW V VM = 1.55V for Bn, VM = 1.5V for all others. Input Pulse Definitions SWITCH tPLZ, tPZL All other closed open VCC BIAS V VIN 2.0V (for RU = 9 Ω) 2.1V (for RU = 16.5 Ω) VOUT PULSE GENERATOR RU D.U.T. RT Test Circuit for Outputs on B Port 1995 May 25 10% tW SWITCH POSITION TEST VM VM 10% CD INPUT PULSE REQUIREMENTS Family FB+ Amplitude Low V Rep. Rate A Port 3.0V 0.0V 1MHz 500ns 2.5ns 2.5ns B Port 2.0V 1.0V 1MHz 500ns 2.0ns 2.0ns tW tTLH tTHL DEFINITIONS: RL = Load Resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. CD = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RU = Pull up resistor; see AC CHARACTERISTICS for value. SG00063 15 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm 1995 May 25 16 FB2031 SOT379-1 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver NOTES 1995 May 25 17 FB2031 Philips Semiconductors Product specification 9-bit latched/registered/pass-thru Futurebus+ transceiver FB2031 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1995 May 25 18 Date of release: 01-0006835 9397 750