INTEGRATED CIRCUITS DATA SHEET TDA8798 Dual 8-bit, 100 Msps A/D converter with DPGA Objective specification Supersedes data of 1998 Apr 15 File under Integrated Circuits, IC02 1999 Sep 16 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA TDA8798 FEATURES APPLICATIONS • Dual 8-bit Analog-to-Digital Converter (ADC) • High-dynamic range acquisition front-ends • Sampling rate up to 100 million samples per second (Msps) • Digital data storage read channels. • Dual 34 dBV 6-bit Digitally Programmable Gain Amplifier (DPGA) with optional power-off GENERAL DESCRIPTION The TDA8798 is a dual 8-bit ADC with DPGA. The 100 Msps maximum sampling rate and 34 dBV DPGA gain range optimizes the ADC for high dynamic range applications. • Optional external equalization filter with capacitive coupling between DPGA and ADC • Serial Interface (SI) for DPGA gain control using either parallel load mode or count-up/count-down mode • 3.3 V TTL/CMOS compatible I/O • Differential or single-ended TTL/CMOS clock interface • AC or DC coupling for DPGA inputs. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDA analog supply voltage 3.15 3.3 3.45 V VDDD digital supply voltage 3.0 3.3 3.6 V VDDO output stage supply voltage IDDA analog supply current 2.7 3.3 3.6 V with DPGAEN LOW − 106 − mA with DPGAEN HIGH − tbf − mA IDDD digital supply current − 30 − mA IDDO output stage supply current − 3 − mA INL DC integral non-linearity DNL DC differential non-linearity Vn(o)(rms) output referred noise (RMS value) B(−3dB)(ADC) ADC −3 dB analogue bandwidth B(−3dB)(DPGA) DPGA −3 dB bandwidth f(sample)(max) maximum sampling rate Ptot total power dissipation 1999 Sep 16 from IC analog input to digital output; ramp input; fCLK = 100 MHz with DPGA at G(min) − ±3.0 tbf LSB without DPGA − ±1.0 tbf LSB from IC analog input to digital output; ramp input; fCLK = 100 MHz with DPGA at G(min) − ±0.5 tbf LSB without DPGA − ±0.5 tbf LSB DPGA at G(max); Zi = 50 Ω; noise bandwidth = 15 MHz − tbf 2 mVrms at Vi(dif)(FS) − 120 − MHz at Vi(dif)(max) 30 tbf − MHz 100 − − Msps with DPGAEN LOW − 460 500 mW with DPGAEN HIGH − tbf tbf mW 2 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA TDA8798 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8798HL LQFP64 DESCRIPTION VERSION plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2 BLOCK DIAGRAM handbook, full pagewidth OPTIONAL EXTERNAL FILTER 2 to DPGA2 to DPGA2N DPGA2 DPGAC2 3 to BUF2N Voref2 BUF2N DPGA2N 2 to BUF2 1 BUF2 63 VSSA4 TE TEST 64 62 54 SR 55 OE VDDA4 60 52 61 51 58 59 REGULATOR analog VIN2N input 2 VIN2 VDDA2 VSSA2 VSSD1 VDDD1 DPGAEN VDDD2 VSSD2 VSSA1 VDDA1 analog input 1 VIN1 VIN1N 6 41 to 48 A 7 DPGA2 BUFFER D 5 4 ADC2 6 8 TDA8798 24 27 25 53 29 26 SERIAL INTERFACE 28 56 30 57 CLK2N digital output 2 B0 to B7 Vref2 SEN2 SCLK SMODE SDATA SEN1 9 13 6 12 ADC1 10 40 to 33 A 11 BUFFER DPGA1 D 23 REGULATOR 14 15 16 18 17 19 20 21 22 31 50 32 49 MGM863 DPGAC1 DPGA1N DPGA1 to DPGA1N to DPGA1 VDDA3 BUF1 BUF1N Voref1 OPTIONAL EXTERNAL FILTER 1 to BUF1N to BUF1 3 VDDO1 VSSA3 Fig.1 Block diagram. 1999 Sep 16 CLK2 VSSO1 VDDO2 VSSO2 Vref1 digital output 1 A0 to A7 CLK1 CLK1N Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA handbook, full pagewidth DPGA(1) 10 µH L Co(DPGA) IOUT TDA8798 100 nF BUF(2) C Ro(DPGA) Ri(ADC) Ci(ADC) Ri(ADC) Ci(ADC) R 1 kΩ −IOUT Ro(DPGA) DPGAN(3) Co(DPGA) L C 10 µH 100 nF BUFN(4) TDA8798 TDA8798 FCE267 External filtering may be used between DPGA and ADC to limit the noise bandwidth. 1 R ⁄ 2 + R o ( DPGA ) The external filter has a low-pass cut-off frequency of f l ( –3dB ) ≈ ------- × ------------------------------------------ . 2π L 1 1 and a high-pass cut-off frequency of f h ( –3dB ) ≈ ------- × -----------------------------2π R i ( ADC ) × C . Other types of filter may be used if DC biasing is correct. (1) (2) (3) (4) DPGA1/DPGA2 BUF1/BUF2 DPGA1N/DPGA2N BUF1N/BUF2N Fig.2 External filter. PINNING SYMBOL PIN DESCRIPTION DPGA2N 1 DPGA2 inverting output DPGA2 2 DPGA2 non-inverting output DPGAC2 3 DPGA2 bandwidth limitation control Vref2 4 ADC2 reference output VDDA2 5 DPGA2 analog supply voltage VIN2N 6 DPGA2 inverting input voltage VIN2 7 DPGA2 non-inverting input voltage VSSA2 8 DPGA2 analog ground VSSA1 9 DPGA1 analog ground VIN1 10 DPGA1 non-inverting input voltage VIN1N 11 DPGA1 inverting input voltage VDDA1 12 DPGA1 analog supply voltage Vref1 13 ADC1 reference output DPGAC1 14 DPGA1 bandwidth limitation control DPGA1 15 DPGA1 non-inverting output DPGA1N 16 DPGA1 inverting output 1999 Sep 16 4 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA SYMBOL BUF1 PIN 17 TDA8798 DESCRIPTION buffer1 non-inverting input BUF1N 18 buffer1 inverting input Voref1 19 buffer1 common mode reference output VDDA3 20 ADC1 analog supply voltage 3 VSSA3 21 ADC1 analog ground 3 CLK1N 22 ADC1 inverting clock input CLK1 23 ADC1 non-inverting clock input VSSD1 24 digital ground 1 VDDD1 25 digital supply voltage 1 SMODE 26 serial interface mode input SEN2 27 serial interface enable 2 (active low) SDATA 28 serial interface data input SCLK 29 serial interface clock input SEN1 30 serial interface enable 1 (active low) VDDO1 31 output stage supply voltage 1 VSSO1 32 output stage ground 1 A7 33 channel 1 output bit 7 (MSB) A6 34 channel 1 output bit 6 A5 35 channel 1 output bit 5 A4 36 channel 1 output bit 4 A3 37 channel 1 output bit 3 A2 38 channel 1 output bit 2 A1 39 channel 1 output bit 1 A0 40 channel 1 output bit 0 (LSB) B0 41 channel 2 output bit 0 (LSB) B1 42 channel 2 output bit 1 B2 43 channel 2 output bit 2 B3 44 channel 2 output bit 3 B4 45 channel 2 output bit 4 B5 46 channel 2 output bit 5 B6 47 channel 2 output bit 6 B7 48 channel 2 output bit 7 (MSB) VSSO2 49 output stage ground 2 VDDO2 50 output stage supply voltage 2 OE 51 digital output enable (active LOW) SR 52 digital output bit slew-rate control DPGAEN 53 DPGA enable (active LOW) TEST 54 test input (to be grounded) TE 55 track-and-hold enable (active LOW) VDDD2 56 digital supply voltage 2 VSSD2 57 digital ground 2 1999 Sep 16 5 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA PIN ADC2 inverting clock input 60 ADC2 analog ground 4 VDDA4 61 ADC2 analog supply voltage 4 55 TE 57 VSSD2 64 BUF2 handbook, full pagewidth 56 VDDD2 buffer2 non-inverting input 58 CLK2 64 59 CLK2N BUF2 60 VSSA4 buffer2 inverting input 61 VDDA4 buffer2 common mode reference output 63 62 Voref2 62 BUF2N 63 BUF2N Voref2 1 48 B7 DPGA2 2 47 B6 DPGAC2 3 46 B5 Vref2 4 45 B4 VDDA2 5 44 B3 VIN2N 6 43 B2 VIN2 7 42 B1 DPGA2N VSSA2 8 41 B0 TDA8798HL 6 VSSO1 32 33 A7 VDDO1 31 DPGA1N 16 SEN1 30 34 A6 SCLK 29 DPGA1 15 SDATA 28 35 A5 SEN2 27 DPGAC1 14 SMODE 26 36 A4 VDDD1 25 Vref1 13 VSSD1 24 37 A3 CLK1 23 VDDA1 12 CLK1N 22 38 A2 VSSA3 21 VIN1N 11 VDDA3 20 39 A1 Voref1 19 VIN1 10 BUF1N 18 40 A0 BUF1 17 VSSA1 9 Fig.3 Pin configuration. 1999 Sep 16 49 VSSO2 59 VSSA4 50 VDDO2 CLK2N 51 OE ADC2 non-inverting clock input 52 SR 58 53 DPGAEN CLK2 DESCRIPTION 54 TEST SYMBOL TDA8798 MGM864 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA TDA8798 FUNCTIONAL DESCRIPTION Serial Interface (SI) The TDA8798 comprises two independent fully differential signal chains each having a DPGA and a high-speed ADC. A serial interface allows the gain of each DPGA to be controlled independently. To improve signal conditions, an AC-coupled external filter can be connected between a DPGA and ADC. The TDA8798 can be used as a dual 8-bit ADC without DPGA functionality, using less power. The SI allows the gain of each DPGA to be controlled independently using either a parallel load mode or a count-up/count-down mode. The gain control mode is selected by the state of SMODE. The operation of DPGA gain control is shown in Timing diagram, (see Fig.4). Parallel load mode This mode loads gain control data serially into a decoder in the SI. Each of the six bits are loaded on the rising edge of SCLK. After the load has completed, SEN goes inactive, loading the data in parallel to a gain control register in the SI, changing the gain of the DPGA. Digitally Programmable Gain Amplifier (DPGA) The gain of the differential DPGA is programmable from 0 to 34 dBV in 63 equal steps by a 6-bit word output in parallel from a gain control register in the SI. For all gain settings, the DPGA signal bandwidth exceeds 30 MHz. The settling time between gain changes can be adjusted by an external decoupling capacitor connected to DPGAC1 (pin 14) and/or DPGAC2 (pin 3). The analog input signals can be either AC or DC coupled. When used only as a dual 8-bit ADC, both DPGAs can be disabled to reduce power consumption. Count-up/count-down mode Count-up/count-down mode is selected when SMODE is in the opposite state to parallel load mode. This mode either increments or decrements the SI gain control register in one-bit steps when SEN and SCLK are both active; the state of SDATA determines the count direction (up or down). This allows the gain of the DPGA to be changed asynchronously and intermittently. Analog-to-Digital Converter (ADC) The 8-bit ADC converts the differential analog input signal into a binary output format at a maximum conversion rate of 100 Msps. All digital input and output signals are TTL/CMOS compatible. ADC digital outputs Digital noise on the internal supply lines increases when the VDDO voltage increases, affecting the crosstalk between channels. This effect can be reduced by making SR (pin 52) HIGH, changing the slew-rate of the ADC digital outputs. The ADC clock signal can be from either a differential or a single-ended source; when single-ended, the unused clock input pin should be decoupled externally. The analog input to the ADC is AC coupled. When used only as a dual ADC, the ADC can be externally biased by regulator output Voref1 (pin 19) and/or Voref2 (pin 62) using series resistors of, for example, 50 Ω, connected to the ADC buffer inputs providing a lower input impedance. This requires Voref1 and/or Voref2 to be decoupled to ground by a 10 nF capacitor. Vref1 (pin 13) and/or Vref2 (pin 4) provide a voltage corresponding to the bias of the ADC which can be used as a reference output to an external control circuit. Alternatively, an external control voltage can be applied to these pins to adjust the full-scale range of the ADC. 1999 Sep 16 7 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA Table 1 TDA8798 Serial interface truth table; see notes 1 and 2 SMODE SEN1 SEN2 SDATA 1 1 U WAIT 0 1 1 Di SISR: SISR ← Di 0 0 1 1 0 SCLK X, ACTION SISR: SISR ← 1 GCR1: GCR1 + 1 0 0 1 0 SISR: SISR ← 0 GCR1: GCR1 − 1 0 1 0 1 SISR: SISR ← 1 GCR2: GCR2 + 1 0 1 0 0 SISR: SISR ← 0 GCR2: GCR2 − 1 0 0 0 1 SISR: SISR ← 1 GCR1: GCR1 + 1 GCR2: GCR2 + 1 0 0 0 0 SISR: SISR ← 0 GCR1: GCR1 − 1 GCR2: GCR2 − 1 1 X, 1 1 1 1 X, X, X, X, X, X, X, X, X, U WAIT Di SISR: SISR ← Di U GCR1: SISR U GCR2: SISR U GCR1: SISR GCR2: SISR Notes 1. ‘← Di’: shifting LSB and loading new LSB with value Di. 2. In count-up/count-down mode, the gain control register cannot be incremented above the maximum gain value of 63, or decremented below the minimum gain value of 0. 1999 Sep 16 8 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA Table 2 Abbreviations TDA8798 Table 4 SYMBOL SR truth table SR DESCRIPTION ADC DIGITAL OUTPUT SLEW RATE GCR1 DPGA1 gain control register value 0 maximum GCR2 DPGA2 gain control register value 1 minimum SISR Serial interface shift register value X can be either logic state 0 or logic state 1 Table 5 DPGAEN truth table DPGAEN rising edge DPGA FUNCTIONALITY 0 enabled 1 disabled falling edge Table 6 U can be either undefined logic state X rising edge or falling edge Di Data input Table 3 GAIN CONTROL REGISTER VALUE TE truth table TE Gain Control ADC TRACK-AND-HOLD GAIN (dBV) 000000 0.00 000001 0.54 000010 1.08 ... ... 0 track-and-hold enabled ... ... 1 track enabled ... ... 111110 33.46 111111 34.00 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDA analog supply voltage −0.3 +7.0 V VDDD digital supply voltage −0.3 +7.0 V VDDO output stage supply voltage −0.3 +7.0 V ∆VDDX supply voltage differences between VDDA and VDDD −1.0 +1.0 V VDDO and VDDD −1.0 +1.0 V −1.0 +1.0 V −0.3 +7.0 V VDDA and VDDO Vi(VIN) input voltage range on VIN1 and VIN2 (pins 10 and 7) IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb ambient temperature 0 70 °C Tj junction temperature − 104 °C 1999 Sep 16 referenced to VSSA 9 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA TDA8798 HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient VALUE UNIT 68 K/W in free air CHARACTERISTICS VDDA = V5 (or V12 or V20 or V61) to V8 (or V9 or V21 or V60) = 3.15 to 3.45 V; VDDD = V25 (or V56) to V24 (or V57) = 3.0 to 3.6 V; VDDO = V31 (or V50) to V32 (or V49) = 2.7 to 3.6 V; VSSA, VSSD and VSSO shorted together; VDDA to VDDD = −0.25 to +0.25 V; VDDD to VDDO = −0.25 to +0.90 V; VDDA to VDDO = −0.25 to +0.75 V; Tamb = 0 to 70 °C; typical values measured at VDDA = VDDD = VDDO = 3.3 V and Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA analog supply voltage 3.15 3.3 3.45 V VDDD digital supply voltage 3.0 3.3 3.6 V VDDO output stage supply voltage 2.7 3.3 3.6 V IDDA analog supply current DPGAEN LOW − 106 − mA DPGAEN HIGH − tbf − mA IDDD digital supply current − 30 − mA IDDO output stage supply current − 3 − mA at G(min) − 0.5 − V at G(max) − 10 − mV tbf 2.8 tbf V fCLK = 100 MHz; ramp input Digital programmable gain amplifiers ANALOG INPUTS (VIN1, VIN1N, VIN2 AND VIN2N) Vi(dif)(max)(p-p) maximum differential input voltage (peak-to-peak value) Vi(cm)(DPGA) common mode input voltage Ii(DPGA) input current − tbf − µA Ri(DPGA) input resistance 1 − − kΩ Ci(DPGA) input capacitance − − 5 pF at G(min) − 0.5 − V at G(max) − 0.5 − V − 3.1 − V − 115 160 Ω − − 5 pF at Vi(cm)(DPGA) ANALOG OUTPUTS (DPGA1, DPGA1N, DPGA2 AND DPGA2N) Vo(dif)(max)(p-p) maximum differential output voltage (peak-to-peak value) Vo(cm)(DPGA) common mode output voltage Ro(DPGA) output resistance Co(DPGA) output capacitance 1999 Sep 16 at Vo(cm)(DPGA) 10 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA SYMBOL PARAMETER TDA8798 CONDITIONS MIN. TYP. MAX. UNIT BANDWIDTH AND SETTLING B(−3dB)(DPGA) DPGA −3 dB bandwidth at Vi(dif)(max) 30 tbf − MHz tst settling time full-scale transition 10% to 90% 40 − − ns td(g) group delay fi up to 15 MHz at G(min) − tbf − ps at G(max) − tbf − ps GAIN G(min) minimum gain setting tbf 0 tbf dBV G(max) maximum gain setting tbf 34 tbf dBV Gstep gain step size − 0.54 − dBV Gstep(L) gain step size linearity (actual gain step/average − 1) −0.75 − +0.75 dBV G(m)(c-c) channel-to-channel gain matching at G(min) − tbf − dB at G(max) − tbf − dB ∆G/∆T amplifier gain stability as a function of temperature at G(min) − 8 tbf mdB/°C at G(max) − 8 tbf mdB/°C amplifier gain stability as a function of power supply voltage at G(min) − 0.4 tbf dB/V at G(max) − 0.8 tbf dB/V CL = 68 pF − 160 − ns − − 20 ns 40 − − dB 40 − − dB 00H 40 tbf − dB 20H 40 tbf − dB 3FH − tbf − dB tbf 50 − dB ∆G/∆VDD GAIN SWITCHING; TAMB = 25 °C tst(G-G) settling time between two consecutive gain settings tPD propagation delay REJECTION PSRR power supply rejection ratio CMRR common mode rejection ratio DC to 15 MHz at G(min) HARMONICS; TAMB = 25 °C HD2 HD3 second harmonic distortion third harmonic distortion fi = 15 MHz; at Vo(dif)(max); at gain control register: fi = 15 MHz; at Vo(dif)(max); at gain control register: 00H 1999 Sep 16 20H tbf 50 − dB 3FH − 50 − dB 11 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA SYMBOL PARAMETER TDA8798 CONDITIONS MIN. TYP. MAX. UNIT NOISE Vn(o)(rms) output referred noise (RMS value) DPGA at G(max); Zi = 50 Ω; noise bandwidth = 15 MHz − tbf 2 mVrms ADC (without DPGA; fCLK = 100 MHz; from buffer input to digital output) ANALOG INPUTS (BUF1, BUF1N, BUF2 AND BUF2N) Vi(dif)(FS)(p-p) differential input voltage full-scale amplitude; (peak-to-peak value) − 500 − mV Vi(cm)(ADC) common mode input voltage − tbf − V Ii(ADC) input current − tbf − µA Ri(ADC) input resistance − 20 − kΩ Ci(ADC) input capacitance − 3 − pF without DPGA − ±1.0 tbf LSB with DPGA at G(min) − ±3.0 tbf LSB without DPGA − ±0.5 tbf LSB with DPGA at G(min) − ±0.5 tbf LSB at Vi(cm)(ADC) STATIC LINEARITY NLdc(i) NLdc(dif) DC integral non-linearity DC differential non-linearity ramp input; ramp input; DYNAMIC PERFORMANCE THD total harmonic distortion fi = 4.43 MHz − −55 − dB S/N signal-to-noise ratio without harmonics − −46 − dB − 120 − MHz − −40 − dB − − 0.8 V BANDWIDTH B(−3dB)(ADC) ADC −3 dB analog bandwidth CROSSTALK BETWEEN ADC1 AND ADC2 αct crosstalk between channels CLOCK INPUTS: CLK1, CLK1N, CLK2 AND CLK2N; note 1 VIL LOW-level clock input voltage VIH HIGH-level clock input voltage 2.0 − VDDD V IIH HIGH-level clock input current − − 100 µA IIL LOW-level clock input current −100 − − µA − − 0.8 V DIGITAL CONTROL INPUTS (OE, TE, TEST, DPGAEN AND SR) VIL LOW-level input voltage VIH HIGH-level input voltage 2.0 − VDDD V IIH HIGH-level input current −5 − +5 µA IIL LOW-level input current −5 − +5 µA 1999 Sep 16 12 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA SYMBOL PARAMETER TDA8798 CONDITIONS MIN. TYP. MAX. UNIT DIGITAL OUTPUTS (A0 TO A7 AND B0 TO B7) VOL LOW-level output voltage IO = 1 mA − 0.4 V VOH HIGH-level output voltage IO = −1 mA VDDO − 0.4 V − − − V IOZ output current in 3-state mode VO > 0.4 V; VO < (VDDO − 0.4 V) −20 − +20 µA ADC CLOCK TIMING fCLK(max) maximum clock frequency 100 − − MHz tW(CLKL) clock pulse width LOW duration 4.0 − − ns tW(CLKH) clock pulse width HIGH duration 4.0 − − ns tr(CLK) clock pulse rise time 0.75 1 2 ns tf(CLK) clock pulse fall time 0.75 1 2 ns − − tbf ns DATA TIMING (see Fig.4); FCLK = 100 MHZ; CDPGAC = 10 PF td(s)(D) data sampling delay time td(Q) data output delay time th(Q) SR HIGH − 5.0 tbf ns SR LOW − tbf tbf ns SR HIGH tbf 5.0 − ns SR LOW tbf tbf − ns output delay enable at logic HIGH SR HIGH − tbf tbf ns SR LOW − tbf tbf ns output delay enable at logic LOW SR HIGH − tbf tbf ns SR LOW − tbf tbf ns output delay disable at logic HIGH SR HIGH − tbf tbf ns SR LOW − tbf tbf ns output delay disable at logic LOW SR HIGH − tbf tbf ns SR LOW − tbf tbf ns − 1.24 − V − − 10 Ω data output hold time 3-STATE OUTPUT DELAY TIMES (see Fig.6) tdZH tdZL tdHZ tdLZ ADC REFERENCE OUTPUTS (VREF1 AND VREF2) Vo(ref) ADC reference output voltage Ro(ref) ADC reference output resistance Io(ref)(max) ADC reference maximum output current − 4.0 − mA Co(ref) ADC reference output capacitance − − 3 pF 1999 Sep 16 at Vo(ref) 13 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA SYMBOL PARAMETER TDA8798 CONDITIONS MIN. TYP. MAX. UNIT COMMON MODE REFERENCE OUTPUTS (VOREF1 AND VOREF2) Vo(ref) reference output voltage − VDDA − 0.42 V − V Ro(ref) reference output resistance at Vo(cm)(ref) − 400 − Ω Io(ref) reference maximum output current at Vo(cm)(ref) − 0.2 V − 170 − µA Co(ref) reference output capacitance − − 3 pF Serial Interface DIGITAL INPUTS (SEN1, SEN2, SCLK, SDATA AND SMODE) VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2.0 − VDDD V IIH HIGH-level input current −5 0 +5 µA IIL LOW-level input current −5 0 +5 µA GAIN CONTROL DATA TIMING (see Fig.4) fSCLK(max) maximum clock frequency 5 − − MHz tW(SCLKH) clock pulse width HIGH 20 − − ns tW(SCLKL) clock pulse width LOW 20 − − ns tsu(SEN-SCLK) SEN to SCLK set-up time 5 − − ns th(SEN-SCLK) SEN to SCLK hold time 5 − − ns tsu(SDATA-SCLK) SDATA to SCLK set-up time 5 − − ns th(SMODE-SCLK) SMODE to SCLK hold time 5 − − ns th(SMODE-SEN) SMODE to SEN hold time 5 − − ns td(SEN-Q) delay SEN rising edge to change gain control register value − − 5 ns td(SCLK-Q) delay SCLK rising edge to change gain control register value − − 5 ns Note 1. Single-ended clock signal sources are allowed. The unused clock input is internally biased at the logical threshold (1.65 V for nominal supply conditions), and should be correctly decoupled. 1999 Sep 16 14 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 50% SMODE th(SMODE-SEN) 50% SEN th(SMODE-SCLK) t W(SCLKH) tsu(SEN-SCLK) t W(SCLKL) tsu(SEN-SCLK) tsu(SEN-SCLK) th(SEN-SCLK) 50% SCLK tsu(SDATA-SCLK) 15 up = 1 down = 0 SDATA D5 (MSB) D4 D3 D2 D1 up = 1 down = 0 D0 (LSB) Philips Semiconductors count-up/count-down mode Dual 8-bit, 100 Msps A/D converter with DPGA handbook, full pagewidth 1999 Sep 16 parallel load mode td(SEN-Q) td(SCLK-Q) SI GAIN CONTROL REGISTER D5 D4 D3 D2 D1 D0 REG +/−1 REG +/−1 tst(G-G) 10% DPGA OUTPUTS 90% tPD Objective specification TDA8798 Fig.4 Timing diagram of serial interface. MGM865 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA TDA8798 t W(CLKL) handbook, full pagewidth t W(CLKH) HIGH 50 % CLK LOW sample N sample N + 1 sample N + 2 Vi th(Q) td(s)(D) DATA A0 to A7 B0 to B7 HIGH DATA N−2 DATA N−1 DATA N DATA N+1 50 % LOW td(Q) MGM866 Fig.5 Timing diagram for the ADC. VDDO handbook, full pagewidth 50% OE 0V tdZH tdHZ logic HIGH 90% data output 50% tdLZ tdZL high impedance data output high impedance 50% logic LOW 10% VDDO TDA8798 OE A0 to A7 B0 to B7 3.3 kΩ S1 10 pF TEST S1 tdLZ VDDO tdZL VDDO tdHZ GND tdZH GND MGM868 Fig.6 Timing diagram and test conditions of 3-state output delay time. 1999 Sep 16 16 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA TDA8798 TEST AND APPLICATION INFORMATION handbook, full pagewidth 3.3 V 3.3 V 100 nF(1) 3.3 V 100 nF(1) 100 nF(1) 49 VSSO2 VDDO2 50 51 OE SR 52 DPGAEN 53 54 TEST TE 55 56 57 VDDD2 TE CLK2 VSSD2 CLK2 58 CLK2N 59 60 VSSA4 VDDA4 61 Voref2 62 VSSD 100 nF 100 nF(1) VSSD 3.3 V B5 B4 B3 B2 B1 B0 A0 A1 A2 A3 A4 A5 A6 A7 B7 B6 B5 B4 B3 B2 B1 B0 A0 A1 A2 A3 A4 A5 A6 A7 32 31 30 B6 VSSO 100 nF(1) VSSD 3.3 V B7 VSSO1 VDDO1 29 100 nF(1) VSSA SEN1 VSSA SEN1 (2) SCLK 100 nF (2) BUF2N 33 16 BUF1 100 nF 63 34 15 17 DPGA1N 35 14 28 DPGA1 SCLK 68 pF(3) 36 13 SDATA VSSA DPGAC1 37 12 27 VSSA Vref1 SDATA 100 nF(1) SEN2 3.3 V 38 11 SEN2 VDDA1 26 VIN1N 39 10 SMODE VIN1N SMODE 100 nF(4) 40 9 25 VIN1 VIN1 TDA8798HL 24 100 nF(4) 41 8 VDDD1 VSSA1 42 7 23 VSSA2 CLK1 VIN2 43 VSSD1 VIN2 44 6 CLK1 100 nF(4) 5 22 VIN2N CLK1N 100 nF(4) VIN2N 21 3.3 V 45 4 VSSA3 100 nF(1) V DDA2 46 3 20 Vref2 VSSA 47 2 VDDA3 DPGAC2 19 68 pF(3) VSSA 48 Voref1 DPGA2 VSSO 1 18 DPGA2N BUF1N (2) BUF2 100 nF (2) 64 100 nF VSSD 100 nF VSSD VSSA DPGAEN VSSD VSSO OE VSSD SR VSSA VSSO 3.3 V MGM867 Analog and digital supplies must be separate and decoupled. (1) Supply decoupling capacitor must be placed as close as possible to the chip’s pin. Value may need changing depending on the external filter characteristics. (2) Capacitor may be replaced when an external filter is used with AC coupling. (3) Capacitor value may be changed to adjust settling time between DPGA gain changes. (4) Capacitor value may need changing depending on the high-pass cut-off frequency of the external filter. Fig.7 Application diagram. 1999 Sep 16 17 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA TDA8798 INTERNAL PIN CONFIGURATIONS handbook, halfpage V DDA2 handbook, halfpage V DDA1 0.5 V VIN2 VIN2N 0.5 V VIN1 VIN1N 1 kΩ 1 kΩ VSSA2 VSSA1 MGM870 MGM869 Fig.8 DPGA1 analog input. Fig.9 DPGA2 analog input. handbook, V halfpage DDA3 handbook, V halfpage Voref1 Voref2 DDA4 BUF1 BUF1N 20 kΩ 0.42 V BUF2 BUF2N 20 kΩ VSSA4 VSSA3 MGM872 MGM871 Fig.10 ADC1 buffer input and Voref1 output. Fig.11 ADC2 buffer input and Voref2 output. handbook, halfpage V DDD1 handbook, halfpage V CLK1 CLK2 DDD2 CLK1N CLK2N 20 kΩ 20 kΩ 1.4 V 1.4 V VSSD1 VSSD2 MGM873 MGM874 Fig.12 ADC1 clock buffer input. 1999 Sep 16 0.42 V Fig.13 ADC2 clock buffer input. 18 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA handbook, halfpage TDA8798 handbook, halfpage VDDA3 VDDA4 VDDA2 VDDA1 100 Ω 100 Ω DPGA1 DPGA2 DPGA1N DPGA2N VSSA1 VSSA2 MGM876 MGM875 Fig.14 DPGA1 buffer output. handbook, halfpage Fig.15 DPGA2 buffer output. handbook, halfpage VDDD1 SMODE SEN1 SEN2 SDATA SCLK VDDD2 TE DPGAEN VSSD1 VSSD2 MGM877 MGM878 Fig.16 Serial Interface inputs. Fig.17 TE and DPGAEN inputs. handbook, halfpage VDDO1 OE handbook, halfpage V DDO2 OE SR A0N A0 VSSO2 MGM879 VSSO1 MGM880 Fig.18 OE and SR inputs. 1999 Sep 16 Fig.19 ADC1 A0 to A7 outputs. 19 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA handbook, halfpage TDA8798 VDDO2 VDDA3 OE Vref1 B0N B0 1.24 V VSSA3 VSSO2 FCE268 MGM881 Fig.20 ADC2 B0 to B7 outputs. Fig.21 Vref1 output. VDDA4 Vref2 1.24 V VSSA4 FCE269 Fig.22 Vref2 output. 1999 Sep 16 20 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA TDA8798 PACKAGE OUTLINE LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM θ bp pin 1 index 64 Lp L 17 1 detail X 16 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.5 HD HE 12.15 12.15 11.85 11.85 L Lp v w y 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 1.45 1.05 7 0o 1.45 1.05 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-12-19 97-08-01 SOT314-2 1999 Sep 16 EUROPEAN PROJECTION 21 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA • For packages with leads on two sides and a pitch (e): SOLDERING – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 1999 Sep 16 TDA8798 22 Philips Semiconductors Objective specification Dual 8-bit, 100 Msps A/D converter with DPGA TDA8798 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Sep 16 23 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SÃO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com SCA 68 © Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/25/02/pp24 Date of release: 1999 Sep 16 Document order number: 9397 750 05466