74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 02 — 30 August 2007 Product data sheet 1. General description The 74LVC1G18 is a 1-of-2 non-inverting demultiplexer with a 3-state output. The device buffers the data on input pin A and passes it either to output 1Y or 2Y, depending on whether the state of the select input (pin S) is LOW or HIGH. Input can be driven from either 3.3 or 5 V devices. These features allow the use of these devices in a mixed 3.3 and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features n n n n n n n n n n n Wide supply voltage range from 1.65 to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: u JESD8-7 (1.65 V to 1.95 V) u JESD8-5 (2.3 V to 2.7 V) u JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: u HBM EIA/JESD22-A114E exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V. ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels SOT363 and SOT457 package Specified from −40 to +85 °C and −40 to +125 °C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G18GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363 74LVC1G18GV −40 °C to +125 °C SC-74 plastic surface-mounted package (TSOP6); 5 leads SOT457 74LVC1G18 NXP Semiconductors 1-of-2 non-inverting demultiplexer with 3-state deselected output 4. Marking Table 2. Marking Type number Marking code 74LVC1G18GW VW 74LVC1G18GV V18 5. Functional diagram 1Y 6 S 1 A 3 2Y 4 mnb088 Fig 1. Logic symbol 6. Pinning information 6.1 Pinning 74LVC1G18 S 1 6 1Y GND 2 5 VCC A 3 4 2Y 001aag921 Fig 2. Pin configuration 6.2 Pin description Table 3. Pin description Symbol Pin Description S 1 data select GND 2 ground (0 V) A 3 data input 2Y 4 data output VCC 5 supply voltage 1Y 6 data output 74LVC1G18_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 August 2007 2 of 13 74LVC1G18 NXP Semiconductors 1-of-2 non-inverting demultiplexer with 3-state deselected output 7. Functional description Table 4. Function table[1] Input Output S A 1Y 2Y L L L Z L H H Z H L Z L H H Z H [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Min Max Unit −0.5 +6.5 V −50 - mA −0.5 +6.5 V mA - ±50 Active mode [1][2] −0.5 VCC + 0.5 V Power-down mode [1][2] −0.5 +6.5 V - ±50 mA VO > VCC or VO < 0 V IO output current ICC supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C - 300 mW total power dissipation Ptot VO = 0 V to VCC Tamb = −40 °C to +125 °C [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For SC-74 and SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature ∆t/∆V input transition rise and fall rate Conditions Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V Active mode 0 - VCC VO VCC = 0 V; Power-down mode 0 - 5.5 VO −40 - +125 °C VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 5.5 V - - 10 ns/V 74LVC1G18_2 Product data sheet Min © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 August 2007 3 of 13 74LVC1G18 NXP Semiconductors 1-of-2 non-inverting demultiplexer with 3-state deselected output 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit Tamb = −40 °C to +85 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 1.65 V to 1.95 V 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V VCC = 1.65 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 × VCC V IO = −100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V IO = −4 mA; VCC = 1.65 V 1.2 - - V IO = −8 mA; VCC = 2.3 V 1.9 - - V VI = VIH or VIL IO = −12 mA; VCC = 2.7 V 2.2 - - V IO = −24 mA; VCC = 3.0 V 2.3 - - V IO = −32 mA; VCC = 4.5 V 3.8 - - V VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.3 V IO = 12 mA; VCC = 2.7 V - - 0.4 V IO = 24 mA; VCC = 3.0 V - - 0.55 V IO = 32 mA; VCC = 4.5 V - - 0.55 V II input leakage current VCC = 0 V to 5.5 V; VI = 5.5 V or GND - ±0.1 ±5 µA IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL; VO = 5.5 V or GND - ±0.1 ±10 µA IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - ±0.1 ±10 µA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 10 µA ∆ICC additional supply current per pin; VCC = 2.3 V to 5.5 V; VI = VCC − 0.6 V; IO = 0 A - 5 500 µA CI input capacitance VCC = 3.3 V; VI = GND to VCC - 2.5 - pF Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V 74LVC1G18_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 August 2007 4 of 13 74LVC1G18 NXP Semiconductors 1-of-2 non-inverting demultiplexer with 3-state deselected output Table 7. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max VIL VCC = 1.65 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 × VCC V VCC − 0.1 - - V LOW-level input voltage VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 5.5 V LOW-level output voltage VOL Unit IO = −4 mA; VCC = 1.65 V 0.95 - - V IO = −8 mA; VCC = 2.3 V 1.7 - - V IO = −12 mA; VCC = 2.7 V 1.9 - - V IO = −24 mA; VCC = 3.0 V 2.0 - - V IO = −32 mA; VCC = 4.5 V 3.4 - - V IO = 100 µA; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.80 V VI = VIH or VIL II input leakage current VCC = 0 V to 5.5 V; VI = 5.5 V or GND - - ±20 µA IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL; VO = 5.5 V or GND - - ±20 µA IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - - ±20 µA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 40 µA ∆ICC additional supply current per pin; VCC = 2.3 V to 5.5 V; VI = VCC − 0.6 V; IO = 0 A - - 5000 µA [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 74LVC1G18_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 August 2007 5 of 13 74LVC1G18 NXP Semiconductors 1-of-2 non-inverting demultiplexer with 3-state deselected output 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 5. Symbol Parameter −40 °C to +85 °C Conditions enable time ten Max Min Max VCC = 1.65 V to 1.95 V 1.0 5.1 10.0 1.0 12.5 ns VCC = 2.3 V to 2.7 V 1.0 3.2 5.5 0.5 6.9 ns VCC = 2.7 V 1.0 3.2 5.4 0.5 6.8 ns VCC = 3.0 V to 3.6 V 1.0 3.0 5.0 0.5 6.3 ns VCC = 4.5 V to 5.5 V 1.0 2.3 3.8 0.5 4.8 ns 1.0 5.8 11.0 1.0 13.8 ns S to nY; see Figure 3 [2] [3] VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 1.0 3.6 6.2 0.5 7.8 ns VCC = 2.7 V 1.0 3.6 6.0 0.5 7.5 ns VCC = 3.0 V to 3.6 V 1.0 3.1 5.2 0.5 6.5 ns 1.0 2.4 3.6 0.5 4.5 ns VCC = 1.65 V to 1.95 V 1.0 4.8 9.0 1.0 11.3 ns VCC = 2.3 V to 2.7 V 1.0 2.7 5.3 0.5 6.6 ns VCC = 2.7 V 1.0 3.5 5.2 0.5 6.5 ns VCC = 3.0 V to 3.6 V 1.0 3.3 4.9 0.5 6.1 ns VCC = 4.5 V to 5.5 V 0.5 2.2 3.3 0.5 4.1 ns - 28.8 - - - pF VCC = 4.5 V to 5.5 V disable time tdis power dissipation capacitance CPD S to nY; see Figure 3 VI = GND to VCC; VCC = 3.3 V [4] [5] [1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL [3] ten is the same as tPZH and tPZL [4] tdis is the same as tPLZ and tPHZ [5] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74LVC1G18_2 Product data sheet Unit Min propagation delay A to nY; see Figure 3 tpd −40 °C to +125 °C Typ[1] © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 August 2007 6 of 13 74LVC1G18 NXP Semiconductors 1-of-2 non-inverting demultiplexer with 3-state deselected output 12. AC waveforms VI VM VM A input GND tPLH tPHL VOH VM nY output VM VOL mnb089 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 3. Input A to output Y propagation delays Table 9. Measurement points VCC VM 1.65 V to 1.95 V Input 0.5 × VCC VI tr = tf VCC ≤ 2.0 ns 2.3 V to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 V to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns 4.5 V to 5.5 V 0.5 × VCC VCC ≤ 2.5 ns VI S input VM GND t PLZ t PZL VCC nY output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY nY output HIGH-to-OFF OFF-to-HIGH VM GND output enabled output disabled output enabled mnb090 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. VX = VOL + 0.3 V at VCC ≥ 2.7 V. VX = VOL + 0.15 V at VCC < 2.7 V. VY = VOH − 0.3 V at VCC ≥ 2.7 V. VY = VOH − 0.15 V at VCC < 2.7 V. Fig 4. 3-state enable and disable times 74LVC1G18_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 August 2007 7 of 13 74LVC1G18 NXP Semiconductors 1-of-2 non-inverting demultiplexer with 3-state deselected output VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 5. Load circuitry for switching times Table 10. Test data VCC Input Load VEXT VI tr = t f CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open GND 2 × VCC 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open GND 6V 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open GND 6V 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open GND 2 × VCC 74LVC1G18_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 August 2007 8 of 13 74LVC1G18 NXP Semiconductors 1-of-2 non-inverting demultiplexer with 3-state deselected output 13. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT363 JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 6. Package outline SOT363 (SC-88) 74LVC1G18_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 August 2007 9 of 13 74LVC1G18 NXP Semiconductors 1-of-2 non-inverting demultiplexer with 3-state deselected output Plastic surface-mounted package (TSOP6); 6 leads D SOT457 E B y A HE 6 X v M A 4 5 Q pin 1 index A A1 c 1 2 3 Lp bp e w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT457 JEDEC JEITA SC-74 EUROPEAN PROJECTION ISSUE DATE 05-11-07 06-03-16 Fig 7. Package outline SOT457 (SC-74) 74LVC1G18_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 August 2007 10 of 13 74LVC1G18 NXP Semiconductors 1-of-2 non-inverting demultiplexer with 3-state deselected output 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G18_2 20070830 Product data sheet - 74LVC1G18_1 Modifications: 74LVC1G18_1 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • In Section 10 “Static characteristics”, changed conditions for input leakage and supply current. 20030725 Product specification 74LVC1G18_2 Product data sheet - - © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 August 2007 11 of 13 74LVC1G18 NXP Semiconductors 1-of-2 non-inverting demultiplexer with 3-state deselected output 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74LVC1G18_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 August 2007 12 of 13 74LVC1G18 NXP Semiconductors 1-of-2 non-inverting demultiplexer with 3-state deselected output 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 30 August 2007 Document identifier: 74LVC1G18_2