5
4
3
2
1
Revision History
Revision
Table of Contents TBD
D
POWER SECTION
RES MUX & MII CONN
VIDEO & AUDIO SECTION
CASPIAN SOC SALSA
CASPIAN SOC AUTOBR
DEBUG INTERFACE
CAN PHYSICAL INTERFACE
RESET & CLOCK SECTION
LIN & SCI PHYSICAL INTERFACE
LED & SWITCH SECTION
Sheet
Sheet
Sheet
Sheet
Sheet
Sheet
Sheet
Sheet
Sheet
Sheet
2
3
4
5
6
7
8
9
10
11
Date
Description
X1
4/09/13
Initial Draft based on SCH-27843 _A
X2
4/22/13
BOM & SCH Update
X3
4/23/13
Developement Release
A
5/26/13
Production Release
A1
06/06/13
Added dual footprint/part for CM701 [TDK ACT45L-201-2P]
B
09/18/13
Changed RESET circuit
D
C
C
MPC5606EEVB
7x7 keepout area
VHDCI
for BACES
GPIO
B
B
EXTAL
ADC Channel
I/P
ADC
XTAL
MPC5606E
TDI,TDO,TCK,TMS
RESET
JTAG &
RESET
VDD_HV
VDD_LV
VSS_HV
VSS_LV
OVDD_3V3
Clock
Microcontroller Solutions Group
A
A
6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to Freescale Semiconductor and shall not be used for
engineering design, procurement or manufacture in whole or in part without the express written permission
of Freescale Semiconductor.
ICAP Classification:
FCP: ____
FIUO: X
PUBI: ____
Designer:
Drawing Title:
ionDSN
Power Supply
Connectors
MPC5606EEVB
5
4
3
2
Drawn by:
PAVEL BOHACIK
Page Title:
Approved:
Size
C
Document Number
Date:
Tuesday, March 25, 2014
TITLE PAGE
Rev
B
SCH-27889 PDF: SPF-27889
Sheet
1
1
of
11
5
4
3
2
1
TP10
1
1.2V
HDR 1X1
JP4
Power supply input and filter
HDR 1X1
SW1
25136N
1
2
1
4
2
3
F1
1
VSwitched
3
2
Fuse Holder
C707
D2
1000PF
C706
2X51uH
JP8
1
JP22
HDR 1X1
1
JP1
47UH
+
B130LB-13
+
C10
1000UF
BAT_GND
HDR 1X1
JP7
1
1
TP5
D
1
1
JP10
TP8
1
GND
Oscope GND Loops
GND
Distribute Evenly over the board
GND
Power Supply 5.0 V
Power Supply 3.3V
3V3_FB
6
R21
40.2K
4
TP6
MP2380
0.1UF
D9
B530C
R60
C20
47UF
C21
C45
C46
C47
47UF
10UF
10UF
0.1UF
C42
1.0 UF
100K
PG
7
GND
5VFB
R57
40.2K
4
EN/SYNC GND
MP2380
R63
10.0K
GND
GND
D16
LED GREEN
R121
100
B
Power Supply 1.2V
R120
249
J9
8
3
HDR TH 1X3
Default: 2-3
6
R9
7
VCC
PG
C13
U8
BST
SW
FB
EN/SYNC GND
2
1
2
4.7UH
5
TP3
4
0.1UF
C11
1.0 UF
R8
162K
C9
1.2VFB
MP2380
R10
10.0K
0.1UF
D6
B530C
C8
47UF
C7
47UF
R7
324K
A
C15
10UF
1.2V
L2
1
0.1UF
C14
C16
10UF
100K
IN
1
5.0V
GND
VIN_VREG_1_2V
1
GND
EPAD
GND
9
3
2
1
Q1
MMBT3904LT1G
2
47UF
P12V
R1
100
1
C38
47UF
R55
7.68K
C
C
D17
LED GREEN
3
560
0.1UF
D15
B530C
C37
5.0V
A
A
R2
C
D1
LED GREEN
C
TP9
A
3.3V
3.3V
2
4.7UH
C39
R19
13K
GND
1.2V
1
0.1UF
5
FB
5.0V
L8
1
2
5
2
SW
1
4.7UH
U13
BST
2
VCC
1
IN
3
C19
R25
10.0K
8
2
2
1.0 UF
1
C
0.1UF
3.3V
L3
3V3_L
A
10UF
FB
EN/SYNC GND
1
C
10UF
C22
PG
0.1UF
2
C
C33
7
SW
A
1N4148WS
C44
A
C31
100K
U10
BST
1
R24
C29
VCC
2
6
C
IN
P12V
1
3
C27
2
8
EPAD
9
P12V
D14
C
9
C
1N4148WS
A
EPAD
D8
B
1
TP4
1
HDR 1X1
C5
68UF
TP1
1
HDR 1X1
1
JP2
1
HDR 1X1
JP5
HDR 1X1
1
JP6
TP7
A
0.1UF
P12V
VFused
1
1
HDR 1X1
1
JP3
TP2
HDR 1X1
2
12V-IN
C
CM1
1
2
3
JP23
HDR 1X1
1
JP9
L1
P4
1
JP11
5.0V
HDR 1X1
Main Power-In
POWER SWITCH
2.1mm Barrel
Connector
D
1
3.3V
HDR 1X1
GND
GND
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: ___
PUBI: X
MPC5606EEVB
Page Title:
POWER SECTION
5
4
3
2
Size
C
Document Number
Date:
Monday, March 24, 2014
Rev
B
SCH-27889 PDF: SPF-27889
Sheet
1
2
of
11
5
4
VID_DATA11_OMNI pg{4}
10
VID_DATA11_APTI pg{4}
DNP
pg{5,6} PORT_A12
R100
10
1
R117
VID_DATA2_APTI pg{4}
0
DNP
R65
SAI0_DATA0 pg{4}
DNP
0
DNP
10
VID_DATA10_OMNI pg{4}
R104
DNP
R103
D
R71
1
2
3
RESET_BR
pg{6}
0
VID_DATA10_APTI pg{4}
Default:
R79
J61
HDR TH 1X3
RESET_BR
pg{5,6} PORT_C2
R105
10
pg{5,6} PORT_A1
2
VID_DATA2_OMNI pg{4}
R116
R102
10
pg{5,6} PORT_A0
3
R101
10
Short 2-3
0
0
ETC0 pg{4}
DNP
D
SAI0_DATA1 pg{4}
DNP
R69
10
VID_DATA9_OMNI pg{4}
R98
CAN0_TXD pg{8}
R99
R77
10
pg{5,6} PORT_A2
0
pg{3,5,6} PORT_B0
VID_DATA9_APTI pg{4}
DNP
R97
0
SAI1_BCLK pg{4}
DNP
0
SAI0_DATA2 pg{4}
DNP
R68
10
VID_DATA8_OMNI pg{4}
R95
0
pg{3,5,6} PORT_B1
CAN0_RXD pg{8}
R96
10
pg{5,6} PORT_A3
VID_DATA8_APTI pg{4}
DNP
R94
R76
0
0
SAI1_DATA0 pg{4}
DNP
SAI0_DATA3 pg{4}
DNP
R81
0
R72
10
VID_DATA7_OMNI pg{4}
R92
VID_FRAME_SYNC_APTI pg{4}
DNP
0
pg{5,6} PORT_B2
LIN0_TXD pg{10}
R93
10
pg{5,6} PORT_A4
VID_DATA7_APTI pg{4}
DNP
R91
SAI0_SYNC pg{4}
DNP
C
L9
75 OHM
R80
0
R75
DNP
0
R67
DNP
0
0
1
2
VID_PIX_CLK_OMNI pg{4}
AN13 pg{4}
VID_RST_APTI pg{4}
pg{5,6} PORT_B3
C
LIN0_RXD pg{10}
L10
pg{5,6} PORT_A5
1
2
VID_PIX_CLK_APTI pg{4}
R74
0
DNP
R114
ETC2_AN14 pg{4}
0
DNP
SAI1_SYNC pg{4}
DNP
10
VID_VSYNC_OMNI pg{4}
R112
R113
pg{5,6} PORT_A6
10
VID_VSYNC_APTI pg{4}
DNP
R111
0
SAI2_SYNC pg{4}
DNP
R70
JP18
0
1
10
VID_HSYNC_OMNI pg{4}
R109
HDR 1X1
pg{5,6} PORT_C3
R110
pg{5,6} PORT_A7
10
DNP
R108
R78
VID_HSYNC_APTI pg{4}
0
DNP
0
ETC1 pg{4}
SAI0_BCLK pg{4}
DNP
10
B
VID_DATA6_OMNI pg{4}
R89
pg{5,6} PORT_A8
B
L11
75 OHM
R90
10
pg{5,6} CLK_OUT_25MH
1
2
MC_RGM_ABS0 pg{4,9}
VID_DATA6_APTI pg{4}
R88
DNP
0
L12
1
SAI2_DATA0 pg{4}
DNP
2
VID_CLK_IN_APTI pg{4}
DNP
10
VID_DATA5_OMNI pg{4}
R86
pg{5,6} PORT_A9
10
R115
0
SAI0_MCLK pg{4}
DNP
R87
VID_DATA5_APTI pg{4}
DNP
R85
0
SAI2_BCLK pg{4}
DNP
10
VID_DATA4_OMNI pg{4}
R82
R84
pg{5,6} PORT_A10
10
VID_DATA4_APTI pg{4}
DNP
R83
GPIO
0
J54
SAI2_MCLK pg{4}
DNP
pg{3,5,6} PORT_B0
R107
10
VID_DATA3_OMNI pg{4}
R118
pg{5,6} PORT_A11
R106
10
0
HDR 2X3
DNP
A
GND
JP21
0
2
4
6
SAI1_MCLK pg{4}
VID_DATA3_APTI pg{4}
DNP
R66
pg{3,5,6} PORT_B1
VID_PWDN_OMNI pg{4}
R119
A
0
pg{5,6} PORT_A15
1
3
5
1
DNP
HDR 1X1
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: ___
PUBI: X
MPC5606EEVB
Page Title:
RES MUX & MII CONN
5
4
3
2
Size
C
Document Number
Date:
Monday, March 24, 2014
Rev
B
SCH-27889 PDF: SPF-27889
Sheet
1
3
of
11
5
4
3
2
3.3V
J59
OMNIVISION VIDEO INTERFACE
pg{3} SAI0_DATA3
pg{3} SAI0_DATA2
pg{3} SAI0_DATA1
pg{3} SAI0_DATA0
pg{3} SAI0_BCLK
pg{3} SAI0_SYNC
pg{3} SAI0_MCLK
pg{3} ETC2_AN14
pg{4} AUD_IIC1_CLK
pg{4} AUD_IIC1_DATA
pg{3} SAI1_DATA0
pg{3} SAI1_BCLK
pg{3} ETC1
pg{3} SAI1_SYNC
pg{3} SAI1_MCLK
pg{4} AUD_IIC0_CLK
pg{4} AUD_IIC0_DATA
pg{3} SAI2_DATA0
pg{3} SAI2_BCLK
pg{3} SAI2_SYNC
pg{3} SAI2_MCLK
pg{3} ETC0
pg{3} AN13
5.0V
J58
pg{3}
pg{3}
pg{3}
pg{3}
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
VID_DATA5_OMNI
VID_DATA7_OMNI
VID_DATA9_OMNI
VID_DATA11_OMNI
5.0V
D
pg{3} VID_HSYNC_OMNI
pg{3} VID_VSYNC_OMNI
pg{3} VID_PIX_CLK_OMNI
pg{3} VID_DATA3_OMNI
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
VID_IIC_SDA_OMNI
VID_IIC_CLK_OMNI
VID_DATA4_OMNI pg{3}
VID_DATA6_OMNI pg{3}
VID_DATA8_OMNI pg{3}
VID_DATA10_OMNI pg{3}
VID_PWDN_OMNI pg{3}
MC_RGM_ABS0 pg{3,9}
VID_DATA2_OMNI pg{3}
HDR_2X16
Pin Numbering on this Omnivision mating connector
is mirror image of the numbering on the Omnivision
Daughter Card.
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
AUD_IIC1_CLK
AUD_IIC1_DATA
AUD_IIC0_CLK
AUD_IIC0_DATA
AUDIO INTERFACE
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
D
HDR_2X25
GND
VIDEO INTERFACES
GND
3.3V
R17
4.7K
APTINA VIDEO INTERFACE
J57
C
pg{3} VID_DATA5_APTI
pg{3} VID_DATA7_APTI
pg{3} VID_DATA9_APTI
pg{3} VID_DATA11_APTI
pg{3} VID_DATA3_APTI
pg{3} VID_FRAME_SYNC_APTI
5.0V
pg{3} VID_RST_APTI
pg{3} VID_CLK_IN_APTI
VID_IIC_SDA_APTI
2
4
6
8
10
12
14
16
18
20
22
24
26
1
3
5
7
9
11
13
15
17
19
21
23
25
VID_DATA4_APTI pg{3}
VID_DATA6_APTI pg{3}
VID_DATA8_APTI pg{3}
VID_DATA10_APTI pg{3}
VID_DATA2_APTI pg{3}
VID_HSYNC_APTI pg{3}
Default:
IIC1_CLK
Short 1-2
J19
pg{5,6} PORT_A13
C
3.3V
Default:
J20
1
2
3
R22
4.7K
5.0V
HDR TH 1X3
R33
AUD_IIC1_CLK
AUD_IIC1_CLK pg{4}
VID_VSYNC_APTI pg{3}
VID_IIC_CLK_APTI
Short 1-2
3.3V
1
2
3
4.7K
VID_IIC_CLK
HDR TH 1X3
VID_PIX_CLK_APTI pg{3}
Default:
IIC1_DATA
CON_2X13
Short 1-2
J28
3.3V
1
2
3
pg{5,6} PORT_A14
R39
HDR TH 1X3
VID_IIC_DATA
HDR TH 1X3
4.7K
GND
CON 2X13 SKT TH 100MIL
1
2
3
J29
Default:
AUD_IIC1_DATA
3.3V
Short 1-2
AUD_IIC1_DATA pg{4}
VID_IIC_SDA_OMNI
R49
4.7K
IIC0_CLK
pg{4} IIC0_CLK
J55
J39
1
2
3
IIC0_CLK
1
2
3
VID_IIC_DATA
Default:
OPEN
HDR TH 1X3
Short 1-2
VID_IIC_SDA_APTI
3.3V
B
HDR TH 1X3
Default:
AUD_IIC0_CLK
AUD_IIC0_CLK pg{4}
B
R50
4.7K
IIC0_DATA
pg{4} IIC0_DATA
J40
1
2
3
IIC0_DATA
VID_IIC_CLK_OMNI
Default:
OPEN
J56
HDR TH 1X3
1
2
3
VID_IIC_CLK
AUD_IIC0_DATA
AUD_IIC0_DATA pg{4}
HDR TH 1X3
Default:
Short 1-2
VID_IIC_CLK_APTI
MC_RGM_ABS2 pg{9}
HDR TH 1X3
1
2
3
pg{5,6} PORT_C5
Default:
Short 1-2
J38
IIC0_CLK
IIC0_CLK pg{4}
MC_RGM_FAB pg{9}
A
A
HDR TH 1X3
pg{5,6} PORT_C6
1
2
3
Default:
Short 1-2
ICAP Classification:
Drawing Title:
J41
FCP: ___
FIUO: ___
PUBI: X
MPC5606EEVB
Page Title:
VIDEO & AUDIO SECTION
IIC0_DATA
5
4
3
IIC0_DATA pg{4}
2
Size
C
Document Number
Date:
Monday, March 24, 2014
Rev
B
SCH-27889 PDF: SPF-27889
Sheet
1
4
of
11
5
4
3
2
1
D
3.3V
R733
10.0K
10.0K
D
3.3V
R51
EXTAL pg{6,9}
XTAL pg{6,9}
PW_ON_RESET_B pg{6,9}
VDD_HV_ADR
C759
0.01UF
Place Outside DC area
Default:
Short 1-2
VDD_HV_FLA0
VDD_HV_FLA1
VDD_HV_OSC0_REG0
A6
C768
VDD_HV_FLA
C766
GND
C773
C26
C767
C730
C734
0.1UF
0.01UF
C729
C24
C725
C726
0.1UF
0.01UF
Default:
0.1UF
0.01UF
1000PF 1000PF
C10
pg{6} FEC_MDIO
J11
G1
D11
33
HDR 1X2 TH
C727
1000PF 1000PF
A7
pg{6} FEC_RX_CLK
Short 1-2
G6
pg{3,6} CLK_OUT_25MH
GND
B[10]
L10
B[11]
C[1]
1000PF 1000PF
GND
C[4]
GND
3.3V
J35
V_BALLAST_IN_HDR
V_BALLAST_IN
1
2
3
Default:
Short 2-3
HDR TH 1X3
0.1UF
1.2V
F1
C721
C723
0.01UF
PPC5606EVMC
C25
C771
C724
C769
0.1UF 0.1UF
C770
C772
0.01UF
1000PF 1000PF
1000PF 1000PF
C774
C745
C741
0.1UF 0.1UF
1000PF
C762
C755
C750 VDD_LV
0.01UF 0.1UF
F11
E9
G11
G10
E11
pg{6} FEC_TXD3
pg{6} FEC_TXD2
pg{6} FEC_TXD1
pg{6} FEC_TXD0
pg{6} FEC_TX_EN
VDD_LV
GND
C722
C6
D8
C7
B8
G8
pg{6} FEC_RXD3
pg{6} FEC_RXD2
pg{6} FEC_RXD1
pg{6} FEC_RXD0
pg{6} FEC_RX_DV
2.55
1.2V
C[0]
B[15]
B[14]
B[13]
B[4]
B[0]
B[1]
B[2]
B[3]
B[8]
B[7]
B[6]
B[5]
B[9]
C[2]
C[3]
C[5]
C[6]
Place Outside DC area
0.1UF
Default:
1000PF
PPC5606EVMC
Short 1-2
J23
VPP_TEST
pg{6} VPP_TEST
NMI
Default:
L2
K1
K2
J2
B6
A2
B2
B1
pg{3,6}
pg{3,6}
pg{3,6}
pg{3,6}
PORT_C2
PORT_C3
PORT_C5
PORT_C6
pg{3,6}
pg{3,6}
pg{4,6}
pg{4,6}
R717
GND
B
PORT_B0
PORT_B1
PORT_B2
PORT_B3
D2
VDD_LV_PLL0
C754
C
B[12]
VPP_TEST
VDD_LV_COR0_1
VDD_LV_COR0_2
K11
A5
pg{3,6}
pg{3,6}
pg{3,6}
pg{3,6}
pg{3,6}
pg{3,6}
pg{3,6}
pg{3,6}
pg{3,6}
pg{3,6}
pg{3,6}
pg{3,6}
pg{3,6}
pg{4,6}
pg{4,6}
pg{3,6}
R731
V_BALLAST_IN_RES
1
2
3
PORT_A0
PORT_A1
PORT_A2
PORT_A3
PORT_A4
PORT_A5
PORT_A6
PORT_A7
PORT_A8
PORT_A9
PORT_A10
PORT_A11
PORT_A12
PORT_A13
PORT_A14
PORT_A15
Short 2-3
B11
VDD_HV_S_BALLAST0
V_BALLAST_IN
D1
D4
E4
E1
E3
E2
F2
H1
H5
J6
L9
K7
K9
K8
K10
A3
Place Outside DC area
Place Outside DC area
J34
K5
A10
pg{6} FEC_TX_CLK
U11A
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
A[11]
A[12]
A[13]
A[14]
A[15]
HDR TH 1X3
2
1
C
GND_A1
GND_A11
GND_A4
GND_A8
GND_C1
GND_D10
GND_D3
GND_D6
GND_E5
GND_E7
GND_F4
GND_F6
GND_F8
GND_G2
GND_G5
GND_G7
GND_G9
GND_H6
GND_J1
GND_J10
GND_J4
GND_J7
GND_L1
GND_L11
GND_L3
GND_L6
GND_L8
GND_C8
R20
1
2
A1
A11
A4
A8
C1
D10
D3
D6
E5
E7
F4
F6
F8
G2
G5
G7
G9
H6
J1
J10
J4
J7
L1
L11
L3
L6
L8
C8
pg{6} FEC_MDC
POR_B
3.3V
H2
Place Outside DC area
J50
VDD_HV_FLA
XTAL
G3
K4
EXTAL
VDD_HV_ADR0
JTAG-RST_B pg{6,7,9}
TMS pg{6,7}
TCK pg{6,7}
TDI pg{6,7}
TDO pg{6,7}
600OHM
HDR 1X2 TH
J31
1000PF 1000PF
H3
H11
J8
J9
F9
0.1UF
JTAG-RST_B
TMS
TCK
TDI
TDO
3.3V
L700
1
2
C760
VDD_ADR
RESET_B
TMS
TCK
TDI
TDO
U11B
C761
VDD_ADR
C758
VDD_HV_ADR
3.3V
GND
B
GND
GND
4.7K
3
2
1
GND
3.3V
Place Outside DC area
J21
Default:
J30
HDR TH 1X3
Short 1-2
pg{6} NMI
3
2
1
NMI
HDR TH 1X3
Place Outside DC area
Default:
OPEN
R716
4.7K
GND
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: ___
PUBI: X
MPC5606EEVB
Page Title:
CASPIAN SOC SALSA
5
4
3
2
Size
C
Document Number
Date:
Tuesday, March 25, 2014
Rev
B
SCH-27889 PDF: SPF-27889
Sheet
1
5
of
11
5
4
3
2
1
Place Outside DC area
J17
FB701
1
2
OVDD
470 Ohm
1
2
28
R18
C739
C735
1uF
C738
1uF
C718
1uF
R34
499
R40
GND
GND
GND
R36
45.3 C747
68PF
18.2
R41
100PF
L7
4.02
0.1UF
2
R38
Place close to MCU pins
L6
1
4.02
GND
2
R42
220nH
BR_N
C756
TRD0_M0_BR
1
220nH
DNP
2
J15
2
4
6
8
pg{5} FEC_MDIO
pg{5} FEC_MDC
TVS2
C746
3.3V
J18
22uF
1K
Short 1-2
Place Outside DC area
C717
BROADCOM 2 WIRE ETH OUTPUT
D
Default:
FB700
1uF
Short 1-2
3.3V
VDD_HV
470 Ohm
VDD_HV_FL
OVDD_FL
Default:
1
1
3
5
7
Default:
Short 3-4
Short 5-6
D
R23
4.7K
MDIO
MDC
CM701
1
PGB2010402KRHF
R35
68PF
C32
45.3
0.1UF
3
2
200uH @ 100KHz
ACT45L-201-2P
C742
HDR_2X4
GND
C18
100PF
45.3
R30
45.3 C740
4.02
R29
R31
68PF
68PF
TVS1
2
1
GND
4.02
L5
2
1
TRD0_P0_BR
1
L4
R32
18.2
Place Outside DC area
R27
100PF
C732
BR1
GND
499
R26
GND
0
DNP
R724
pg{7} TMS_BR
DNP
C
A
R736
86.6
DNP
0
0
DNP
4.7K
R727
C3
B3
B4
C4
R719
pg{7} TDO_BR
TDN0
BR2
TMS/ LED1
TDI/ LED2
TDO/ LED3
U1_SYNC_OUT
0
DNP 4 BR JTAG R718
GREEN
TDP0
GND
U11C
GND
MDC
MDIO
RXC
C11
MDC
B10
MDIO
B7
GND
FEC_RX_CLK pg{5}
pg{6} TRD0_P0
pg{6} TRD0_M0
0
R721
pg{7} TDI_BR
DS1
Caspian Activity LED
L5
PGB2010402KRHF
220nH
DNP 4 MB
1K
DNP
2
R28
220nH
OVDD_RGMII_3V3
L4
34793-0040
Molex
C17
100PF
C30
C5
BR_P
F7
1
2
3
4
OVDD_3V3
4
J60
LED1
LED2
LED3
LED4
XTALI
H7
R713
CLK_OUT_25MH
CLK_OUT_25MH pg{3,5,6}
150
Keep min 3x spacing on BGA area and 5x ouside
GND 3.3V
0 DNP
R737
GND
4.7K
DNP
DNP
BR JTAG EN
3.3V
BR JTAG
R712
R720
F5
F3
4.7K
4.7K
TEST2
TEST3
GTX_CLK
A9
FEC_TX_CLK pg{5}
GND
R741
LED1
0
DNP 4 BR JTAG
86.6
R726
C
B5
J3
PHYA0
TVCOI
RXD3
RXD2
RXD1
RXD0
RXDV
R732
JTAG-RST_B
0 DNP
C2
R53
pg{6} RESET_N
DNP 4 BR JTAG 0
L7
GND
RESET_N
RDAC
PPC5606EVMC
H4
G4
GND
PLLVDD_1V2
pg{7}
JTAG-RST_BR
TXD3
TXD2
TXD1
TXD0
TXEN
D7
D9
C9
B9
H8
FEC_RXD3 pg{5}
FEC_RXD2 pg{5}
FEC_RXD1 pg{5}
FEC_RXD0 pg{5}
FEC_RX_DV pg{5}
F10
E8
H10
H9
E10
FEC_TXD3 pg{5}
FEC_TXD2 pg{5}
FEC_TXD1 pg{5}
FEC_TXD0 pg{5}
FEC_TX_EN pg{5}
K3
3
2
SSMCX
DVDD_1V2
DVDD_1V2
J42
LED2
0
R739 DNP 4 BR JTAG
4.7K
R722
AVDD_3V3
AVDDL_1V2
U1_TVCOI
1
4.7K
D5
E6
R740
GND
DNP 4 BR JTAG
TCK/ PHYA0
R48
0
R730
4.7K
4
5
LED AMB
0
R738
pg{7} TCK_BR
J32
FB704
pg{3} RESET_BR
33
C763
10UF
C775
100PF
C751
1uF
R715
1.24K
GND
GND
DVDD_FL
GND
GND
C748
1uF
C749
1uF
C764
1uF
ALT_FOOTPRINT
FB1
1
2
600OHM
C23
C728
10UF
1uF
GND
AVDDL_FL
FB3
470 Ohm
Place Outside DC area
BIASVDD
C736
1uF
1
2
C753
1uF
AVDD_3V3 -> BALL J5
BIASVDD -> BALL H4
XTALVDD -> BALL G4
VDD_HV -> BALL C5
OVDD -> BALL F7
AVDDL -> BALL K6
DVDD -> BALL D5 & E6
PLLVDD -> BALL K3
pg{4,5} PORT_A14
pg{3,5} PORT_A12
pg{5,9} PW_ON_RESET_B
pg{3,5,6} CLK_OUT_25MH
pg{3,5}
pg{4,5}
pg{3,5}
pg{3,5}
CLK_OUT_25MH
PORT_A10
PORT_A13
PORT_A11
PORT_A9
pg{6} TRD0_P0
pg{6} TRD0_M0
A
pg{3,5} PORT_B0
pg{3,5} PORT_B2
pg{3,5} PORT_B1
pg{3,5} PORT_B3
pg{3,5} PORT_A8
pg{3,5} PORT_A7
pg{3,5} PORT_A6
pg{3,5} PORT_A5
pg{3,5} PORT_A3
pg{3,5} PORT_A1
pg{3,5} PORT_A0
pg{3,5} PORT_A4
pg{4,5} PORT_C6
pg{3,5} PORT_A2
pg{4,5} PORT_C5
pg{3,5} PORT_C3
GND
5
GND
J49
Place Outside DC area
Default:
GND
470 Ohm
C35
1uF
FB702
AVDD_3V3
AVDD_3V3_FL
GND
C720
C744
1uF
+
Short 1-2
AVDDL
B
Place Outside DC area
Default:
Short 1-2
J24
J22
Default:
Short 1-2
Place Outside DC area
3.3V
470 Ohm
C719
1uF
33uF
GND
DNP
GND
DNP
J44
SH1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
SH3
1.2V
J25
GND
Place caps close to IC pins.
1
2
MB 1.2V =
Short 1-2
Place Outside DC area
GND
XTALVDD
MB 3.3V =
C737
1uF
ALT_FOOTPRINT
FB703
1
2
600OHM
C743
10UF
C731
1uF
C752
1uF
FB2
3.3V
C34
1uF
Default:
DVDD
GND
XTALVDD_FL
Short 1-2
J51
1.2V
2
1
3.3V
B
Short 1-2
Place Outside DC area
BIASVDD_FL
OVDD_U1 = 3V3 [Salsa VDD_HV_IO]
Default:
Default:
PLLVDD
470 Ohm
PLLVDD_FL
2
1
R54
2
1
DNP
A
2
1
DS2
C
BIASVDD_3V3
XTALVDD_3V3
Link LED
J5
K6
C
J16
PLLVDD
SH2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
SH4
QSH-030-01-L-D-A-K-TR
V_BALLAST_IN
SH1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
SH3
VDD_HV_FLA
XTALVDD
BIASVDD
VDD_HV_ADR
M700
VDD_HV
0
DNP
JTAG-RST_B pg{5,7,9}
RESET_N pg{6}
XTAL pg{5,9}
M701
0
DNP
EXTAL pg{5,9}
OVDD
DVDD
3.3V
PORT_A15 pg{3,5}
PORT_C2 pg{3,5}
GND
4
MB 2 DC CONNs
PLACED ON TOP SIDE
3.3V
GND
SH2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
SH4
QSH-030-01-L-D-A-K-TR
3
TCK pg{5,7}
TDI pg{5,7}
TMS pg{5,7}
TDO pg{5,7}
VPP_TEST pg{5}
A
NMI pg{5}
AVDDL
3.3V
ICAP Classification:
Drawing Title:
AVDD_3V3
FCP: ___
FIUO: X
PUBI: ___
MPC5606EEVB
Page Title:
MPC5606E SOC AUTOBR
VDD_LV
Size
C
Document Number
Date:
Tuesday, March 25, 2014
Rev
B
SCH-27889 PDF: SPF-27889
GND
2
Sheet
1
6
of
11
5
4
3
2
1
D
D
JTAG INTERFACE
Place CAPS as close to
connector pins as
possible but do NOT fit
caps at board assembly.
C715
DNP
3.3V
47PF
C716
pg{6} TCK_BR
DNP
3.3V
pg{6} TDO_BR
R711
10.0K
pg{6} TDI_BR
pg{5,6} TDI
pg{5,6} TDO
pg{5,6} TCK
C
pg{5,6,9} JTAG-RST_B
47PF
R706
10.0K
R707
10.0K
DNP 4 BR JTAG
TDI
R14
0
TDO R13
0
TCK R12
0
JTAG-RST_B R15
JTAG Connector
GND
P7
1
3
5
7
9
11
13
0
DNP 4 BR JTAG
3.3V
2
4
6
8
10
12
14
(VSS)
(VSS)
(VSS)
(N/C)
R709
10.0K
C
(VSS)
CON_2X7
pg{6} JTAG-RST_BR
R710
10.0K
R708
10.0K
pg{9} JCOMP
pg{5,6} TMS
JCOMP
TMS R16
DNP
GND
DNP 4 BR JTAG
R11
0
0
DNP 4 BR JTAG
pg{6} TMS_BR
B
B
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: ___
PUBI: X
MPC5606EEVB
Page Title:
DEBUG INTERFACE
5
4
3
2
Size
C
Document Number
Date:
Monday, March 24, 2014
Rev
B
SCH-27889 PDF: SPF-27889
Sheet
1
7
of
11
5
4
3
2
1
D
D
Default: 1-2
J5
HDR 1X2 TH
P12V 5.0V
CAN-5V
1
2
1
2
CAN interface
C708
C705
0.1UF
1000PF
CAN-12V
J6
HDR 1X2 TH
Default: 1-2
M1
GND
C709
0.1UF
3.3V
1
6
2
7
3
8
4
9
5
1000PF
GND
C703
C704
0.1UF
1000PF
P3
C710
GND
J7
9
Default: 1-2
1
4
CANA-TX
CANA-RX
1
2
1
2
pg{3} CAN0_TXD
pg{3} CAN0_RXD
14
6
Default: 1-2
J4
HDR 1X2 TH
INH
ERR
DB9
VI/O
VBAT
VCC
7
8
CANH
CANL
13
CANA-CANH
CANA-CANL
12
STB
EN
SPLIT
11
R701
60.4
R700
60.4
GND
1
3
5
GND
C700
0.01UF
GND
3.3V
1
2
3
GND
TXD
RXD
TJA1041T
J1
C
P5
WAKE
GND
HDR 1X2 TH
U1
Default: OPEN
HDR 1X2 TH
2
1
2
J3
GND
5
10
3
M2
C
GND
2
4
6
Default:
Short 1-2
Short 3-4
Short 5-6
B
B
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: X
PUBI: ___
MPC5606EEVB
Page Title:
CAN PHYSICAL INTERFACE
5
4
3
2
Size
C
Document Number
Date:
Monday, March 24, 2014
Rev
B
SCH-27889 PDF: SPF-27889
Sheet
1
8
of
11
5
4
3
2
1
REMOVE XTAL jumper when driving EXTAL from
Oscillator Module or External Source
Power On Reset
U6B
R4
3
4
Default:
Short 2-3
HDR TH 1X3
D
4
1.5K
74LVC14AD
U5
VCC
RST
MR
VSS
1
EVB-EXTAL
2
3 (MCU Crystal Output)
Clock Circuit
2
JTAG-RST_B pg{5,6,7}
U3
STM6315RDW13F
18pF
2
C6
0.1UF
3
14
3.3V
R5
1
1
C712
0.1UF
SW3
KS11R23CQD
1.5K
pg{5,6} PW_ON_RESET_B
U4
1
2
3
GND
Connect to Caspian GND Pin
HDR TH 1X3
LED RED
D5
Default:
XTAL pg{5,6}
(MCU Crystal Input)
GND
Short 1-2
C
2
RST
C12
0.1UF
J52
J8
TRSEL
MR
GND
74LVC14AD
1
2
3
GND
HDR TH 1X3
3
C711
0.1UF
XTAL_J
GND
8
4
2
7
R702
2K
V2IN
V3IN
V4IN
VSS
3
5
6
0
18pF
STM6904TGEDS6F
VCC
U7
R61
R6
2
7
R703
12K
C43
U6A
VCC
1
10.0K
A
BAS70
1.2V
1
3
4
GND
GND
5.0V
R56
1.0M
Y2
25MHZ
3.3V
EXTAL pg{5,6}
EXTAL_J
LED RED
D4
C
SW2
KS11R23CQD
1
1
3
2
2
C41
1
D
J43
A
3.3V
GND
Default: 1-2
3
C
GND
1
U6C
BAS70
5
pg{7} JCOMP
Default:
U6D
U6E
11
13
C28
LED RED
D3
12
0.01UF
Y1
8MHz
1
74LVC14AD
Note - Internal
Pull-Up on Pin 1
GND
E/D
74LVC14AD
2
GND
VCC
4
Default:
OPEN
HDR TH 1X3
J33
3
2
1
3
GND
OUT
74LVC14AD
OPEN
HDR 1X2 TH
3.3V
U6F
10
J26
C
8
1.5K
1
2
74LVC14AD
9
R3
6
A
GND
2
4
C
OSC-MOD
EVB-EXTAL
GND
EXTAL-SMA
Boot Config
3.3V
Default:
3.3V
Default:
R46
B
CON_1_SMA
R47
4.7K
3
1
SMA style
Connector
3
2
1
3
2
1
3.3V
R62
4.7K
4.7K
Short 2-3
HDR TH 1X3
J37
Short 2-3
HDR TH 1X3
J48
2
Short 2-3
HDR TH 1X3
J36
3
2
1
Default:
B
4
MC_RGM_ABS0 pg{3,4}
MC_RGM_FAB pg{4}
5
MC_RGM_ABS2 pg{4}
R52
J53
R64
R44
R73
100
4.7K
4.7K
4.7K
GND
GND
GND
GND
STRAIGHT SMA CONNECTOR ,PLACE NEAR TO SOC
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: ___
PUBI: X
MPC5606EEVB
Page Title:
RESET & CLOCK SECTION
5
4
3
2
Size
C
Document Number
Date:
Monday, March 24, 2014
Rev
B
SCH-27889 PDF: SPF-27889
Sheet
1
9
of
11
5
4
3
2
1
J11
Default: OPEN
J13
LIN Interface
Default: 2-3
Default: 2-3
HDR 1X2 TH
3.3V
J10
HDR TH 1X3
UART_A_TX
3
2
LIN0_TXD pg{3}
1
U9
1
2
3
4
LINC-RX
1
2
D
HDR 1X2 TH
D7
A
1
2
Default: On/Off
Default: Short 1-2
LINC-TX
R704
J14
HDR TH 1X3
3 UART_A_RX
2
LIN0_RXD pg{3}
1
N16966294
RXD
EN
WAKE
TXD
8
7
6
5
INH
VSUP
LIN
GND
GND
R705
P12V
1.0K
C
1
2
3
4
GF1A
LINC-VSUP
LINC-LIN
MC33661PEF
10.0K
Master Mode Pullup Enable
C713
C714
1000PF
0.1UF
P6
4Pin Header
D
HDR_1X4
GND
GND
J12
1
2
3
4
GND
GND
LIN Molex Connector
CON PLUG 4
GND
C
C
SCI Interface
J2
3.3V
1
2
HDR 1X2 TH
Default: 1-2
GND
U2
C2
2
4
0.1UF
5
6
B
C1
13
12
0.1UF
15
10
UART_A_TX
UART_A_RX
1
14
GND
C1+
C1-
19
M1
V+
T1OUT
T2OUT
T1IN
T2IN
R1IN
R2IN
17
8
M2
GND
GND
B
DB9
16
9
3.3V
R1OUT
R2OUT
EN
FORCEON
3
0.1UF
C2+
C2-
P2
1
6
2
7
3
8
4
9
5
C702
VCC
1000PF
INVALID
FORCEOFF
GND
C4
0.1UF
18
C3
V-
11
20
GND
7
C701
MAX3223
0.1UF
GND
GND
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: ___
PUBI: X
MPC5606EEVB
Page Title:
LIN & SCI PHYSICAL INTERFACE
5
4
3
2
Size
C
Document Number
Date:
Monday, March 24, 2014
Rev
B
SCH-27889 PDF: SPF-27889
Sheet
1
10
of
11
5
4
3
User LED's
2
1
3.3V
HDR 1X1
YELLOW LED
C
1
1
YELLOW LED
C
1
YELLOW LED
C
1
1
YELLOW LED
C
A
D12
8
3
2
A
6
1
4
A
3
2
49.9
6
RN2C
5
D
49.9
8
RN2A
7
49.9
RN1D
49.9
D11
JP14
HDR 1X1
RN1B
49.9
RN1C
D10
JP13
HDR 1X1
JP15
A
D13
JP12
HDR 1X1
D
RN1A
7
RN2B
49.9
4
49.9
5
RN2D
49.9
LED's are SMD (1206) Yellow
Default:
User switches
OPEN
HDR TH 1X3
J45
GND
3
2
1
3.3V
C
C
3.3V
R735
10.0K
J46
HDR 1X1
1
1
SW4
2
JP16
3
2
1
3
4
C777
Default:
OPEN
HDR TH 1X3
SPST PB NO
0.1UF
GND
GND
B
B
R734
10.0K
HDR 1X1
1
1
SW5
2
JP17
3
4
C776
0.1UF
SPST PB NO
GND
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: ___
PUBI: X
MPC5606EEVB
Page Title:
LED & SWITCH SECTION
5
4
3
2
Size
C
Document Number
Date:
Monday, March 24, 2014
Rev
B
SCH-27889 PDF: SPF-27889
Sheet
1
11
of
11