Freescale Semiconductor Users Guide Documentation Number: KT34717UG Rev. 3.0, 1/2009 Using the 5.0 A 1.0 MHz Fully Integrated Dual Switch-Mode Power Supply (KIT34717EPEVBE) 1 Introduction This User’s Guide will help the designer get better acquainted with the 34717 IC and Evaluation board. It contains a procedure to configure each block of the 34717 in a practical way, which is based on a working Evaluation Board designed by Freescale (KIT34717EPEVBE). 2 34717 Specification The 34717 is a highly integrated, space efficient, low cost, dual synchronous buck switching regulator with integrated N-channel power MOSFETs. It is a high performance dual point-of-load (PoL) power supply with many desired features for the 3.3 V and 5.0 V environments. Both channels can provide up to 5.0 A of continuous output current capability with high efficiency and tight output regulation. The second channel has the ability to track an external reference voltage in different configurations. © Freescale Semiconductor, Inc., 2007-2009. All rights reserved. Contents 1 2 3 4 5 6 7 8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 34717 Specification. . . . . . . . . . . . . . . . . . . . . 1 Application Diagram . . . . . . . . . . . . . . . . . . . . 2 Board’s Specifications . . . . . . . . . . . . . . . . . . 2 Component Selection for 34717 Eval Board. 3 Layout Design . . . . . . . . . . . . . . . . . . . . . . . . 15 Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 References. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application Diagram 3 Application Diagram 3.0 V to 6.0 V VIN 34717 CIN CBOOT1 VOUT1 L1 RS1 R11 CO1 VIN PVIN1 BOOT1 SW1 VOUT1 PVIN2 BOOT2 SW2 VOUT2 CS1 R21 RF1 CX1 CF1 RI2H RI1H R FQH RFQL CVDDI INV1 INV2 COMP1 COMP2 PGND1 PGND2 VDDI PG FREQ SD ILIM1 CBOOT1 ILIM2 MCU VOUT2 RS2 R12 CO2 CS2 RF2 CX2 CF2 R22 VIN 1k VMASTER RI1L RI2L VOUT1 L2 R3 VREFIN R4 GND Figure 1. Application diagram for 34717 4 Board’s Specifications The Board was designed to have an operating range defined by: Channel #1 Channel #2 PVIN_MAX 6.0 V PVIN_MAX 6.0 V PVIN_MIN 3.0 V PVIN_MIN 3.0 V VOUT_MAX 3.6 V VOUT_MAX 3.6 V VOUT_MIN 0.7 V VOUT_MIN 0.7 V IOUT_MAX 5.0 A IOUT_MAX 5.0 A IOUT_MIN 0.0 A IOUT_MIN 0.0 A Using the 34717, Rev. 3.0 2 Freescale Semiconductor Component Selection for 34717 Eval Board 5 Component Selection for 34717 Eval Board 5.1 I/O Parameters: VIN = PVIN1 = PVIN2 = 5.0V FSW = 1 MHz VOUT1 = 1.8 V IOUT1 = 5.0 A VOUT1 = 1.5 V IOUT2 = 5.0 A VREFIN =VOUT1 5.2 Configuring the Output Voltage: Both channels for the 34717 are General purpose DC-DC converter, the resistor divider to the INV node is the responsible for setting the output voltage. The equation is: ⎛ R1 ⎞ VOUT = V REF ⎜ + 1⎟ ⎝ R2 ⎠ For channel 1: VREF = VBG = 0.7V. For channel 2: The second channel of 34717 has an internal reference selector, thus VREF can be either the voltage at the VREFIN terminal, or the internal reference voltage VBG. The reference value is given by the following condition: VREF = VREFIN if VREFIN is less than VBG = 0.7V. Otherwise, VREF = VBG. Usually the output regulation voltage is calculated using the internal reference VBG, and the condition VREF = VREFIN is used for tracking purposes. Then, for channel 1 at 1.8 V, we choose R1 = 20KΩ and R2 is calculated. R2 = VREF R1 = 12.78 KΩ VOUT − VREF And for channel 2 at 1.5V and R1 = 20KΩ, R2 is calculated as follows: R2 = VREF R1 = 17.5 KΩ VOUT − VREF Using the 34717, Rev. 3.0 Freescale Semiconductor 3 Component Selection for 34717 Eval Board 5.3 Switching Frequency Configuration The switching frequency will have a value of 1.0 MHz by connecting the FREQ terminal to the GND. If the smallest frequency value of 200 KHz is desired, then connect the FREQ terminal to VDDI. To program the switching frequency to another value, an external resistor divider will be connected to the FREQ terminal to achieve the voltages given by the Frequency Selection Table. Frequency KHz Voltage applied to pin FREQ [V] 200 2.341 – 2.500 253 2.185 - 2.340 307 2.029 - 2.184 360 1.873 - 2.028 413 1.717 – 1.872 466 1.561 – 1.716 520 1.405 - 1.560 573 1.249 - 1.404 627 1.093 - 1.248 680 0.936 - 1.092 733 0.781 - 0.936 787 0.625 - 0.780 840 0.469 - 0.624 893 0.313 - 0.468 947 0.157 - 0.312 1000 0.000 - 0.156 Table 1. Frequency Selection Table The EVB frequency is set to 1 MHz, connecting the FREQ terminal directly to GND. Using the 34717, Rev. 3.0 4 Freescale Semiconductor Component Selection for 34717 Eval Board 5.4 Selecting Inductor Inductor calculation process is the same for both Channels. The equation is the following: (V + I * ( Rds (on) _ ls + r _ w)) L = D'MAX ∗T ∗ OUT OUT ∆I OUT D'MAX = 1 − VOUT Vin _ max Maximum Off time percentage T = 1µs Switching period Rds (on) _ ls = 45mΩ Drain – to – source resistance of FET r _ w = 10mΩ Winding resistance of Inductor ∆I OUT = 0.4 * I OUT Output current ripple L1 = 0.72uH and L 2 = 0.75uH However, since channel 1 can serve as power supply for channel 2, we have to locate the LC poles at different frequencies in order to ensure that the input impedance of the second converter is always higher than the output impedance of the first converter and thus ensure system stability. To move the LC poles, we can select different values of “L” for each channel, for instance, L1 = 1.0µH and L2 = 1.5µH, to allow some operating margin for each channel. 5.5 Input Capacitors for PVIN1 and PVIN2 Input capacitor selection process is the same for both channels, and should be based on the current ripple allowed on the input line. The input capacitor should provide the ripple current generated during the inductor charge time. This ripple is dependent on the output current sourced by 34717 so that: I RMS = I OUT D(1 − D) Where: IRMSis the RMS value of the input capacitor current. IOUTis the output current, D= VOUT/Vinis the duty cycle. For a buck converter, IRMS has its maximum at PVIN = 2VOUT Using the 34717, Rev. 3.0 Freescale Semiconductor 5 Component Selection for 34717 Eval Board Since I RMS_MAX = PMAX ESR Where PMAX is the maximum power dissipation of the capacitor and is a constant based on physical size (generally given in the datasheets under the heading AC power dissipation.). We derive that the lower the ESR, the higher would be the ripple current capability. In other words, a low ESR capacitor (i.e., with high ripple current capability) can withstand high ripple current levels without overheating. Therefore, for greater efficiency and because the overall voltage ripple on the input line also depends on the input capacitor ESR, we recommend using low ESR capacitors. CinMIN = 0.5 * L * ( I RMS ) 2 ∆VOUT *Vin For a ∆VOUT = 0.5*Vin, Then CinMIN = 30.4µF To ensure better performance on regulation, an array of low ESR ceramic capacitors were used to get a total of 300 µF in both input terminals. 5.6 Selecting the Output Filter Capacitor For the output capacitor, the following considerations are most important and not the actual Farad value: the physical size, the ESR of the capacitor, and the voltage rating. Calculate the minimum output capacitor using the following formula: C0 = ∆Iout 8 ∗ FSW ∗ ∆Vout A more significative calculation must include the transient response in order to calculate the real minimum capacitor value and assure a good performance. Using the 34717, Rev. 3.0 6 Freescale Semiconductor Component Selection for 34717 Eval Board . Transient Response percentage Maximum Transient Voltage TR_% TR_V_dip = VOUT*TR_% Maximum current step ∆Iout _ step = (Vin _ min − Vout ) * D _ max Fsw * L Inductor Current rise time dt _ I _ rise = T * Iout ∆Iout _ step Iout * dt _ I _ rise TR _ V _ dip To find the Maximum allowed ESR, the following formula was used: ∆Vout * Fsw * L ESRmax = Vout (1 − D min) Co = 5.7 Bootstrap Capacitor Freescale recommends a 0.1 µF for capacitor CBOOT1 and CBOOT2. 5.8 Compensation Network Compensation network is calculated exactly in the same way for both channels. Since we are using different values for L, the LC poles will be located at different frequencies to ensure stability of the system when converter 1 is supplying the power voltage of converter 2. 1. Choose a value for R1 (in this case, R1 = 20KΩ for both channels) 2. Using a Crossover frequency of 100 kHz, set the Zero pole frequency to Fcross/10 FP 0 = 1 1 Fcross = 10 2π * R1C F CF = 1 2π * R1 FPO 3. Knowing the LC frequency, the Frequency of Zero 1 and Zero 2 in the compensation network are equal to FLC FLC = 1 = FZ 1 = FZ 2 2π LX Co X RF = 1 2π * C F FZ 1 FZ 1 = 1 2π * RF C F CS = FZ 2 = 1 2π * R1CS 1 2π * R1 FZ 2 4. Calculate RS by placing the first pole at the ESR zero frequency. Using the 34717, Rev. 3.0 Freescale Semiconductor 7 Component Selection for 34717 Eval Board FESR = 1 = FP1 2π * Co X * ESR FP1 = 1 2π * RS C S RS = 1 2π * FP1C S 5. Set the second pole at Crossover Frequency to achieve a faster response and a proper phase margin. FP 2 = 5.9 1 CX = C F Cx 2π * RF CF + Cx CF 2π * RF C F FP 2 − 1 For Channel 1 For Channel 2 FLC = 9.19 KHz FESR = 265.26 KHz (For ESR = 2.0mΩ) FCROSS = 100 KHz FPO = 10 KHz FLC = 7.5 KHz FESR = 265.26 KHz (For ESR = 2.0mΩ) FCROSS = 100 KHz FPO = 10 KHz R1 = 20 KΩ CF = 0.75 nF RF = 22 KΩ CS = 0.91 nF RS = 0.560 KΩ CX = 0.015 nF R1 = 20 KΩ CF = 1.8 nF RF = 15 KΩ CS = 1 nF RS = 300 KΩ CX = 0.020 nF Soft Start Table 2 shows the voltage that should be applied to terminals ILIM1 and ILIM2 to get the desired configuration of the soft start. The voltage can be achieved by connecting a resistor divided from Output VDDI (2.5V) to the ILIM Terminals. Soft Start [ms] Voltage applied to ILIM 3.2 1.25 - 1.49V 1.6 1.50 - 1.81V 0.8 1.82 - 2.13V 0.4 2.14 - 2.50V Table 2. Soft Start Configuration ILIM1 and ILIM2 are directly connected to VDDI to achieve a soft start of 0.4ms on both outputs. Using the 34717, Rev. 3.0 8 Freescale Semiconductor Component Selection for 34717 Eval Board 5.10 Tracking Configurations This device allows two tracking configurations: Ratiometric and Co-incidental Tracking. 5.10.1 Ratiometric Tracking Circuit Configuration: The master voltage feedback resistor divider network will be used in place of R3 and R4 as shown in Figure 4. The slave output is connected through its own feedback resistor divider network to the INV- terminal, resistors R1 and R2. All four resistors will affect the accuracy of the system and need to be 1% accurate resistors. The master voltage must be connected in the way shown to achieve this tracking, and cannot be directly connected to the VREFIN terminal. Figure 2. Radiometric Tracking Figure 3. Co-incidental Tracking Using the 34717, Rev. 3.0 Freescale Semiconductor 9 Component Selection for 34717 Eval Board VMASTER VBG VREFIN R3 To INV- of Vmaster R4 Reference selector VSLAVE Rs + EA - INV R1 Cs CX RF CF CO R2 COMP Figure 4. Radiometric Tracking Circuit Connections Equations: • VM = VBG_M(1+R3/R4) • VREFIN = VM * R4/(R3+R4) • VREFOUT = VREFIN • VS = VREFOUT(1+R1/R2) = VM* R4/(R3+R4)*(R2+R1)/R2, if VREFOUT < VBG_S • VS = VBG_S(1+R1/R2), if VREFOUT ≥ VBG_S Figure 5. Radiometric Tracking Plot Using the 34717, Rev. 3.0 10 Freescale Semiconductor Component Selection for 34717 Eval Board 5.10.2 Co-incidental Tracking Circuit Configuration: Connect a three resistor divider to the Master Voltage (VM) and route the upper tap point of the divider to the VREFIN terminal, resistors R3, R4, and R5 as shown in Figure 6. This resistor divider must be the same ratio as the slave output’s (VS) feedback resistor divider, which in turn connects to the INV- terminal, resistors R1 and R2 (Condition: R1 = R3 and R2 = R4 + R5). The master’s feedback resistor divider would be (R3+R4) and R5. All five resistors will affect the accuracy of the system and must be 1% accurate resistors. The master voltage must be connected in the way shown to achieve this tracking, and cannot be directly connected to the VREFIN terminal. VMASTER VBG VREFIN R3 R4 Reference selector To INV- of Vmaster R5 VSLAVE Rs + EA - INV R1 Cs CX RF CF CO R2 COMP Figure 6. Co-incidental Tracking Circuit Connections Equations: • VM = VBG_M[1+(R3+R4)/R5] • VREFIN = VM*(R4+R5)/(R3+R4+R5) • VREFOUT = VREFIN • VS = VREFOUT(1+R1/R2) = VM*(R4+R5)/(R3+R4+R5)*(R2+R1)/R2 = VM if VREFOUT < VBG_S • VS = VBG_S(1+R1/R2), if VREFOUT ≥ VBG_S Using the 34717, Rev. 3.0 Freescale Semiconductor 11 Component Selection for 34717 Eval Board Figure 7. Co-incidental Tracking Circuit Connections 5.10.3 Non-DDR Mode (Source Only Mode) This is the case when no tracking is needed. VREFIN should be connected to VDDI and the reference selection block will use the internal band gap voltage as the Error Amplifier’s reference voltage. A user can potentially apply a voltage to the VREFIN terminal directly, or through a resistor divider to get a buffered output for use in this application. The condition here is, the voltage applied on VREFIN terminal is larger than VBG, to guarantee that the reference selection block will not switch back to the VREFOUT voltage The VREFIN pin on the EVB is left opened, so that the user can either connect directly to VOUT1 with a jumper, or use an external master voltage to track, in either of these configurations. Using the 34717, Rev. 3.0 12 Freescale Semiconductor Component Selection for 34717 Eval Board 5.11 EVB Schematic Design GND VDDI FREQ ILIM2 ILIM1 VIN PVIN1 PVIN2 17 PVIN2 3 SW1 SW2 16 SW2 FREQ VDDI VIN PVIN2 2 VIN PVIN1 17 1 GND PVIN1 2 N/C ILIM1 19 BOOT2 18 C28 SW1 ILIM2 20 22 BOOT2 21 23 26 24 U2 BOOT1 25 BOOT1 ILIM1 ILIM2 FREQ VIN VDDI C14 0.1uF BOOT1 C15 BOOT2 SW2 0.1uF 0.1uF PVIN2 PVIN1 SW1 SW1 SW2 MC34717 3 SW1 SW2 16 4 PGND1 PGND2 15 4 PGND1 PGND2 15 5 VOUT1 VOUT2 14 GND GND GND VO2 INV2 /SHTD COMP2 C11 /PGOOD N/C 0.1uF VREFIN INV1 VO1 COMP1 C27 0.1uF INV1 PG COMP1 12 13 COMP2 INV2 11 10 SD PG 8 VREFIN 9 7 INV1 6 VOUT2 COMP1 VOUT1 COMP2 INV2 SD VREFIN C13 0.1uF C12 0.1uF COMPENSATION NETWORK SW2 COMPENSATION NETWORK SW1 VO1 VO2 C20 0.910nF C23 1nF R1 20k INV1 C18 COMP1 15pF R15 COMP2 R18 300 20pF C19 R4 20k INV2 C21 R14 560 R19 R2 C22 R17 12.7k 22k 17.4k 15k 0.75nF BUCK CONVERTER 1 Vo1_1 1.8nF BUCK CONVERTER 2 Vo1_2 Vo2_1 L1 SW1 1 SW2 1 1uH D3 R20 4.7_nopop PMEG2010EA_nopop VO2_2 L2 VO1 2 VO2 2 1.5uH C10 100uF C24 100uF C25 100uF D2 R3 4.7_nopop C6 100uF C7 100uF C8 100uF PMEG2010EA_nopop C26 1nF_nopop C9 1nF_nopop Figure 8. KIT34717EPEVBE Schematic Part 1 Using the 34717, Rev. 3.0 Freescale Semiconductor 13 Component Selection for 34717 Eval Board I/O SIGNALS VIN CAPACITORS VIN PVIN1 3 2 1 C17 10uF C16 0.1uF R7 1k J3 PVIN2 VO2 GND R8 10k VMASTER D1 LED 3 2 1 R9 10k J4 VM VM LED 3 2 1 JUMPERS ILIM1,ILIM2,FREQ VO1 VMASTER STBY_nopop 1 2 1 LED 1 3 5 7 9 2 4 6 8 10 VDDI J1 VREFIN VDDI VIN GND R16 10k PG R10 10k R12 10k_nopop SD ILIM1 CON10A 2 VDDI VO1 VMASTER VIN J2 GND PGOOD LED R22 10k_nopop SD ILIM2 R13 10k_nopop FREQ R11 10k PVIN1 CAPACITORS PVIN2 CAPACITORS PVIN1 PVIN2 C1 0.1uF C2 1uF C3 100uF C4 100uF C5 100uF C30 0.1uF C31 1uF C32 100uF C33 100uF C29 100uF TRIMPOTS nopop VDDI ILIM1 ILIM2 R21 R5 POT_50K_nopop POT_50K_nopop FREQ R6 POT_50K_nopop Figure 9. KIT34717EPEVBE Schematic Part 2 Using the 34717, Rev. 3.0 14 Freescale Semiconductor Layout Design 6 Layout Design Figure 10. PCB Top View Layout Design Figure 11. PCB Bottom View Layout Design Using the 34717, Rev. 3.0 Freescale Semiconductor 15 Layout Design Figure 12. PCB Inner View Layout Design 6.1 PCB Layout Recommendations • • • • • Place decoupling capacitors as close as possible to their corresponding pad(s) Try to place all components on just one Layer. Do not place a Ground Plane on component and routing side. Create a Ground plane layer and tie it to ground signals with vias. To effectively transfer heat from the center thermal pad on the top layer to the ground plane, vias need to be used in the center pad. Use 5 to 9 vias spaced evenly with a finished diameter of 0.3mm. • Place Test vias as close as possible to the IC to ensure a good measurement value. • PVIN, VIN, VOUT signals have to be tracked with a widely and straight copper area • Never trace the Feedback signal in parallel to the SW signal. • Ensure the SW Inductor is placed as close as possible to its pads. • SW track has to be as thin and short as possible. • Make sure the I/O connectors are capable to manage the Load current. Note: Freescale does not recommend connecting the PGND pins to the thermal pad. The thermal pad is connected to the signal ground and should not be used to make the connection from the PGND pins to the ground plane. Doing so can cause ground bounce on the signal ground from the high di/dt switch current and parasitic trace inductance. Using the 34717, Rev. 3.0 16 Freescale Semiconductor Layout Design 6.2 Bill of Materials Table 3. BILL OF MATERIALS KIT34717 EVB Number: KIT34717EPEVBE Item Qty Reference Value Description Footprint 1 23 VOUT1,SW1,PVIN1,INV1,ILIM1,COMP1, BOOT1,VOUT2,SW2,PVIN2,INV2,ILIM2, COMP2,BOOT2,VREFOUT,VREFIN,VIN, VDDI,STBY,SD,PG,GND,FREQ not populated PC Test point miniature SMT TP 2 2 C2,C31 1.0µF Cap Cer 1.0 µF 6.3V 10% X5R 0603 SM/C_0603 3 12 C3,C4,C5,C6,C7,C8,C10,C24,C25,C29, C32,C33 100µF Cap Cer 100 µF 6.3V 10% X5R 1210 SM/C_1210 4 2 C9,C26 not populated 5 10 C1,C11,C12,C13,C14,C15,C16,C27,C28, C30 0.1µF Cap Cer 0.1 µF 50V 10% X7R 0603 SM/C_0603 6 1 C17 10µF Cap Cer 10 µF 6.3V 20% X5R 0603 SM/C_0603 7 1 C18 15pF Cap Cer 15pF 50V 1% C0G 0603 SM/C_0603 8 1 C19 750pF Cap Cer 750pF 50V 5% C0G 0603 SM/C_0603 9 1 C20 910pF Cap Cer 910pF 50V 5% C0G 0603 SM/C_0603 10 1 C21 20pF Cap Cer 20pF 50V 5% C0G 0603 SM/C_0603 11 1 C22 1.8nF Cap Cer 1800pF 50V 5% C0G 0603 SM/C_0603 12 1 C23 1.0nF Cap Cer 1000pF 25V 5% C0G 0603 SM/C_0603 13 1 D1 LED LED Green 0603 SMD SM/C_0603 14 2 D2,D3 not populated 15 1 J1 Pin Header (2 x 5) HDR 2X5 TH 100mil CTR 330H AU 0.1" (2.54mm) 16 3 100mils jumpers Jumpers 17 3 J2,J3,J4 not populated 100mils Using the 34717, Rev. 3.0 Freescale Semiconductor 17 Layout Design 18 1 J5 not populated 19 1 L1 1.0µH Inductor Power 1.0µH 7.5A SMD B82464G 20 1 L2 1.5µH Inductor Power 1.5µH 7.0A SMD B82464G 21 2 R1,R4 20kΩ Res MF 20kΩ 1/10W 1% 0603 SMD SM/C_0603 22 1 R2 12.7kΩ Res MF 12.7kΩ 1/10W 1% 0603 SMD SM/C_0603 23 2 R3,R20 not populated 24 3 R5,R6,R21 not populated 25 1 R7 1kΩ Res MF 1.0kΩ 1/10W 1% 0603 SM/C_0603 26 1 R10 10kΩ Res MF 10kΩ 1/10W 1% 0603 SM/C_0603 27 3 R12,R13,R22 not populated 28 4 R8,R9,R11,R16 10kΩ Res MF 10kΩ 1/10W 1% 0603 SM/C_0603 29 1 R14 560Ω Res MF 560Ω 1/10W 1% 0603 SM/C_0603 30 1 R15 22kΩ Res MF 22kΩ 1/10W 5% 0603 SM/C_0603 31 1 R17 17.4kΩ Res MF 17.4kΩ 1/10W 1% 0603 SM/C_0603 32 1 R18 300Ω Res MF 300Ω 1/10W 5% 0603 SM/C_0603 33 1 R19 15kΩ Res MF 15kΩ 1/10W 1% 0603 SM/C_0603 34 1 SD Push_Button Switch Tact Mini 200GF SLV Gwing 35 1 STBY not populated Switch Tact Mini 200GF SLV Gwing 36 1 U2 MC34717 QFN_26 Notes: Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application. Using the 34717, Rev. 3.0 18 Freescale Semiconductor Conclusion 7 Conclusion With this User Guide, the user will be capable of configuring the 34717 as a double switching power supply for devices that can make use of some of the capabilities that the 34717 offers. The board is fully configured to work at any desirable input voltage within 3V and 6V. However, it is highly recommended to calculate all components for the specific application situation in order to assure a better efficiency and stability of the IC. 8 References • 34717 Datasheet, 5A and 5A 1MHz fully integrated double switch-mode power supply, Freescale semiconductor, Inc. • Application Note “AN1989 MC34701 and MC34702 Component Selection Guide”, Freescale Semiconductor, Inc. • Sanjaya Maniktala, “Switching Power Supplies A to Z”, Newnes, 2006. Using the 34717, Rev. 3.0 Freescale Semiconductor 19 How to Reach Us: Home Page: www.freescale.com RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. Web Support: http://www.freescale.com/support For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 [email protected] For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 [email protected] KT34717UG Rev. 3.0 1/2009 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2007-2009. All rights reserved.