REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing YY MM DD CHECKED BY 14-06-24 4 Phu H. Nguyen APPROVED BY Thomas M. Hess SIZE A REV AMSC N/A CODE IDENT. NO. 5 6 7 8 9 10 11 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil/ TITLE MICROCIRCUIT, DIGITAL-LINEAR, 256-TAPS DUAL CHANNEL DIGITAL POTENTIOMETER WITH NON-VOLATILE MEMORY, MONOLITHIC SILICON DWG NO. V62/14613 16236 PAGE 1 OF 11 5962-V078-14 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 256-Taps dual channel digital potentiometer with non-volatile memory microcircuit, with an operating temperature range of -40°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/14613 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 TPL0102-EP Circuit function 256-Taps dual channel digital potentiometer with non-volatile memory 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins X 14 JEDEC PUB 95 Package style JEDEC MO-153 Plastic Small Outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z 1.3 Absolute maximum ratings. Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other 1/ 2/ 3/ Supply voltage: VDD to GND ...................................................................................... VSS to GND ...................................................................................... Maximum VDD to VSS ........................................................................ Voltage at resistor pins, (VH, VL, VW) ....................................................... Digital input current, (VI) .......................................................................... Maximum pulse current, (IH, IL, IW) .......................................................... Maximum continuous current, (IH, IL, IW) ................................................. Storage temperature range (Tstg) ............................................................. 1/ 2/ 3/ -0.3 V to 7 V -7 V to 0.3 V 7V VSS – 0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V ±20 mA ±2 mA -65°C to 150°C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. All voltages are with respect to ground, unless otherwise specified. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14613 PAGE 2 1.4 Recommended operating conditions. 4/ Single supply operation, (VDD, VSS) (VSS = 0) .......................................... Dual supply operation, (VDD, VSS) (VSS = 0) ............................................. Pin voltage, (VH, VL) ................................................................................ Voltage input high, (VIH) (SCL, SDA, A0, A1, A2) .................................... Voltage input low, (VIL) (SCL, SDA, A0, A1, A2) ..................................... Maximum wipe current, (IW) .................................................................... Junction temperature (TJ) ......................................................................... 2.7 V to 5.5 V ±2.25 V to ±2.75 V VSS to VDD 0.7 x VDD to 5.5 V 0 V to 0.3 x VDD ±2 mA -40°C to 125°C 1.5 Thermal characteristics. Thermal metric 5/ Junction to ambient thermal resistance, RθJA 6/ Junction to case (top) thermal resistance,RθJCtop 7/ Junction to board thermal resistance, RθJB 8/ Junction to top characterization parameter, ΨJT 9/ Junction to board characterization parameter, ΨJB 10/ Junction to case (bottom) thermal resistance, RθJCbot 11/ Case outline X 112.9 39.9 55.9 3.5 55.2 N/A Units °C/W 2. APPLICABLE DOCUMENTS JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 JESD51-2a JESD51-7 JESD51-8 – – – – Registered and Standard Outlines for Semiconductor Devices Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air) High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages Integrated Circuits Thermal Test Method Environment Conditions – Junction-to-board (Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201-2107). AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD ANSI SEMI STANDARD G30-88 – Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http://www.ansi.org) _________________________ 4/ 5/ 6/ 7/ 8/ 9/ 10/ 11/ Over operating free-air temperature range (unless otherwise noted) For more information about traditional and new thermal metrics, see manufacturer data. The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-Kboard, as specified in JESD51-7, in an environment described in JESD51-2a. The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction to top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction to board characterization parameter, ΨJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14613 PAGE 3 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3. 3.5.4 Digital Potentiometer Macromodel. The digital Potentiometer Macromodel shall be as shown in figure 4. 3.5.5 Voltage divide mode. The voltage divide mode shall be as shown in figure 5. 3.5.6 DPOT configurations. The DPOT configurations shall be as shown in figure 6. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14613 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol End-to-end Resistance (Between H and L terminals) Pin resistance Wiper resistance Pin capacitance 3/ 4/ Wiper capacitance 3/ 4/ Terminal Leakage current RH, RL RW CH, CL 3/ 4/ Resistance temperature coefficient TCR Channel-to-channel resistance match Voltage divider mode Integral non-linearity Differential non-linearity Zero-scale error Full-scale error Channel-to-Channel matching Test conditions 2/ RTOT CW 3/ 4/ ILKG Limits Min 80 Typ 100 Max 120 60 25 22 16 0.1 200 120 VH = VSS to VDD, VL = Floating or VL = VSS to VDD, VH = Floating Input Code = 0x80h Ratio metric temperature coefficient TCV Bandwidth BW Wiper setting time TSW THD 1 Wiper at the same tap position, same voltage at all H and same voltage at all L pins Wiper set at mid-scale Wiper set at mid-scale CLOAD = 10 pF 0.1 -0.1 Ω µA ppm/°C % 0.1 -0.5 -0.25 0 -2 -2 kΩ pF 92 RTOT,MATCH INL 5/ 6/ DNL 5/ 7/ ZSERROR 8/ 9/ FSERROR 8/ 10/ VMATCH 8/ 11/ Unit 0.5 0.25 2 0 2 4 LSB ppm/°C kHz 229 3.6 VH = 1 VRMS at 1 kHz, 0.03 Total harmonic distortion VL = (VDD – VSS)/2, Measurement at W fH = 1 kHz, VL = GND, -82 XTALK Cross talk Measurement at W RHEOSTAT MODE (Measurements between W and L with H not connected, or between W and H with L not connected) Integral non-linearity RINL 12/ 13/ -1 1 Differential non-linearity RDNL 12/ 14/ -0.5 0.5 Offset ROFFSET 15/ 16/ 0 0.2 2 Channel-to-Channel matching RMATCH 15/ 17/ -2 2 Code = 0x00h, L Floating, 54 Bandwidth RBW Input applied to W, Measure at H, CLOAD = 10 pF µs % dB LSB MHz See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14613 PAGE 5 TABLE I. Electrical performance characteristics - Continued. 1/ Test VDD standby current Symbol Limits Test conditions 2/ Min OPERATING CHARACTERISTICS VDD = 2.75 V, VSS = –2.75 V, 2 IDD(STBY) I C interface in standby mode -40°C 25°C Unit Typ Max 0.2 1.5 1 16 125°C ISS(STBY) VDD = 2.75 V, VSS = –2.75 V, 2 I C interface in standby mode VDD shutdown current IDD(SHUTDOWN) VDD = 2.75 V, VSS = –2.75 V, 2 I C interface in standby mode VSS shutdown current ISS(SHUTDOWN) VDD = 2.75 V, VSS = –2.75 V, 2 I C interface in standby mode VSS standby current VDD current during non-volatile write VSS current during non-volatile write Digital pins leakage current (A0, A1, A2, SDA, and SCL) Power on recall voltage EEPROM Specification EEPROM endurance EEPROM retention Non-volatile write cycle time Wiper timing characteristics Wiper response time Wiper position recall time from shutdown mode Power-up delay IDD ISS -40°C -1.5 25°C 125°C -1 -16 1 16 -40°C -1.5 25°C -1 125°C -16 350 tD Pin capacitance 2 I C interface specifications Input high voltage CIN Input low voltage VIL Output low voltage Pin capacitance VOL CIN 1 Minimum VDD at which memory recall occurs TJ = 125°C tSHUTDOWNREC -0.2 -350 -1 tWC tWRT 1.5 25°C 125°C ILKG-DIG VPOR -0.2 0.2 -40°C VDD = 2.75 V, VSS = –2.75 V VDD = 2.75 V, VSS = –2.75 V µA SCL falling edge of last bit of wiper data byte to wiper new position SCL falling edge of last bit of ACR data byte to wiper stored position and H connection VDD above VPOR, to wiper initial value 2 register recall completed, and I C interface in standby mode A0, A1, A2, SDA SCL pins VIH 2 V 100,000 100,000 20 Cycles Hours ms 600 ns 800 35 100 µs 7 0.7 x VDD 0 SDA pin, IOL = 4 mA A0, A1, A2, SDA SCL pins pF 5.5 V 0.3 x VDD 0.4 7 pF See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14613 PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Standard Mode I2C Bus Min Max Fast Mode I2C Bus Min Max Unit TIMING REQUIREMENTS 2 I C interface timing requirements 2 I C clock frequency 2 I C clock high time 2 I C clock low time 2 I C spike time 2 I C serial data setup time 2 I C serial data hold time 2 I C input rise time 2 I C input fall time 2 I C output fall time, 10 pF to 400 pF bus 2 I C bus free time between stop and start 2 I C start or repeater start conditions setup time 2 I C start or repeater start condition hold time 2 I C stop condition setup time Valid data time, SCL low to SDA output valid Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low 1/ 2/ 3/ 0 4 4.7 0 250 0 tSCL tsp tSDS tSDH tICR 100 50 1000 300 300 tICF tICF tBUF 4.7 4.7 4 4 tSTS tSTH tSPS tVD(DATA) 0 0.6 1.3 0 100 0 20 + 0.1Cb 18/ 20 + 0.1Cb 18/ 20 + 0.1Cb 18/ 1.3 1.3 0.6 0.6 1 1 tVD(DATA) 400 kHz µs 50 ns 300 300 300 µs 1 1 Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. VDD = 2.7V to 5.5V, VSS = 0V, VH= VDD, VL= GND, TJ = –40°C to 125°C (unless otherwise noted). Typical values are at VDD= 5V, TJ = 25°C (unless otherwise noted). Pin and Wiper Capacitance extracted from self admittance of three port network measurement: Yii = 4/ 5/ 6/ 7/ 8/ 9/ 10/ 11/ 12/ 13/ 14/ 15/ 16/ 17/ 18/ fSCL tSCH Ii Vi | Vk = 0 for k ≠ i Digital Potentiometer Macromodel (See FIGURE 4). LSB = (VMEAS[code 255] – VMEAS[code 0]) / 255 INL = ((VMEAS[code x] – VMEAS[code 0]) / LSB) - [code x] DNL = ((VMEAS[code x] – VMEAS[code x-1]) / LSB) – 1 IDEAL_LSB = (VH-VL) / 256 ZSERROR = VMEAS[code 0] / IDEAL_LSB FSERROR = [(VMEAS[code 255] – (VH-VL)) / IDEAL_LSB] + 1 VMATCH = (VMEAS_A[code x] – VMEAS_B[code x]) / IDEAL_LSB RLSB = (RMEAS[code 255] – RMEAS[code 0]) / 255 RINL =( (RMEAS[code x] – RMEAS[code 0]) / RLSB) - [code x] RDNL =( (RMEAS[code x] – RMEAS[code x-1]) / RLSB )– 1 IDEAL_RLSB = RTOT / 256 ROFFSET = RMEAS[code 0] / IDEAL_RLSB RMATCH = (RMEAS_A[code x] – RMEAS_B[code x]) / IDEAL_RLSB Cb = total capacitance of one bus line in pF. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14613 PAGE 7 Case X b e 14 0.10(.004) M 8 c E 0°-8° E1 GAGE PLANE 1 7 0.25(.010) L DETAIL A D SEE DETAIL A A1 A SEATING PLANE Symbol A A1 b c D 0.10(.004) Dimensions Millimeters Symbol Min Max 0.05 0.19 0.09 4.90 1.20 0.15 0.30 0.20 5.10 E E1 e L Millimeters Min Max 4.30 4.50 6.40 BSC 0.65 BSC 0.45 0.75 NOTES: 1. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. This drawing is subject to change without notice. 3. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 each side. 4. Body width does not include interlead flash. Interlead flash shall not exceed 0.25 each side 5. Falls within JEDEC MO-153. FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14613 PAGE 8 Case outline X Terminal Terminal symbol number HA 14 LA 13 WA 12 Terminal number 1 2 3 Terminal symbol VDD A0 A1 4 5 HB LB 11 10 GND 6 7 WB A2 9 8 SDA VSS SCL FIGURE 2. Terminal connections. A0 A1 A2 SCL VDD I 2 C INTERFACE SDA HA VSS HB VOLATILE REGISTERS WA WB NON-VOLATILE REGISTERS GND LA LB FIGURE 3. Function block diagram. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14613 PAGE 9 H CH TOTA RL W CW L CL FIGURE 4. Digital Potentiometer Macromodel. VH V HW V H- V L V WL V HW=(V H -V L )x(1-(D/256)) W V WL =(V H -V L )xD/256 WHERE D=DECIMAL VALUE OF WIPER CODE VL FIGURE 5. Voltage divide mode. RHEOSTAT MODE A H R TOT H(FLOATING) R TOT W OR W R WL R WL L L RHEOSTAT MODE B H H R HW R HW R TOT R WL =R TOT xD/256 WHERE D=DECIMAL VALUE OF WIPER CODE R TOT W OR L W R HW=(R TOT x(1-(D/256)) WHERE D=DECIMAL VALUE OF WIPER CODE L(FLOATING) FIGURE 6. DPOT configurations. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14613 PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/14613-01XE 01295 TPL0102-100QPWREP EL-100EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 01295 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV DWG NO. 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