NXP Semiconductors Data Sheet: Technical Data KV5XP144M240 Rev. 4, 06/2016 KV5x Data Sheet 240 MHz Cortex-M7 based MCU for Real-time, high performance connected control The Kinetis KV5x family of MCU is a high-performance solution offering exceptional precision, sensing, and control targeting Motor Control, Industrial Drives and Automation, and Power Conversion. Apart from the high performance Cortex-M7 core, it features top notch real time control peripherals such as high resolution pulse-width modulation (PWM) with 260 ps resolution, 4 Fast 12-bit ADCs with 5 MSps, up to 44 PWM channels for supporting multi-motor systems. It also comes with multiple communication peripherals including 3 FlexCAN modules, optional Ethernet Communications, and multiple UART, SPI, and I2C modules. The KV5x is supported by a comprehensive enablement suite from NXP and third-party resources including reference designs, software libraries, and motor configuration tools. Core • ARM® Cortex®-M7 core up to 240 MHz with single precision Floating Point Unit (FPU) Memories • Up to 1 MB program flash memory • Up to 256 KB RAM • External memory interface (FlexBus) System peripherals • 32-channel DMA controller • Low-leakage wakeup unit • SWD debug interface • Advanced independent clocked watchdog • JTAG debug interface MKV58F1M0Vxx24 MKV56F1M0Vxx24 MKV58F512Vxx24 MKV56F512Vxx24 144 LQFP 20 x 20 x 1.4 mm Pitch 0.5 mm 144 BGA 13 x 13 x 1.23 mm Pitch 1.0 mm 100 LQFP 14 x 14 x 1.4 mm Pitch 0.5 mm Communication interfaces • Six UART/FlexSCI modules with programmable 8or 9-bit data format • Three 16-bit SPI modules • Two I2C modules • Three FlexCAN modules • Ethernet Module (Optional) Analog Modules • Four 12-bit SAR High Speed ADCs with 5 MSPS sample rate • One 16-bit ADC • Four CMPs with a 6-bit DAC and programmable reference input • One 12-bit DAC Clocks Timers • 32 to 40 kHz or 3 to 32 MHz crystal oscillator • Two eFlexPWM with 4 sub-modules, with 12 PWM • MCG with FLL and PLL referencing internal or external outputs, one eFlexPWM module with less than 285 reference clock ps resolution provided by nano-edge module. • Two 8-channel FlexTimers (FTM0 and FTM3) Operating Characteristics • Two 2-channel FlexTimers (FTM1 and FTM2) • Voltage range: 1.71 to 3.6 V • Four Periodic interrupt timers (PIT) • Temperature range: –40 to 105 °C • Two Programmable Delay Blocks (PDB) • Quadrature Encoder/Decoder (ENC) Human-machine interface • General-purpose input/output Security and integrity modules NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. • Hardware CRC module to support fast cyclic redundancy checks • External Watchdog Monitor (EWM) • True Random Number Generator (TRNG) • Memory mapped Cryptographic Acceleration Unit (MMCAU) • Advanced Watchdog (WDOG) timer modules Orderable part numbers summary1 NXP part number CPU frequency (MHz) Ambient operating temperat ure (°C) Package Flash/ SRAM Ethernet CAN GPIO MKV58F1M0VMD242 240 105 144 MAPBGA 1 MB/256 KB Yes 3 111 MKV58F1M0VLQ24 240 105 144 LQFP 1 MB/256 KB Yes 3 111 MKV58F1M0VLL24 240 105 100 LQFP 1 MB/256 KB Yes 3 74 MKV56F1M0VMD242 240 105 144 MAPBGA 1 MB/256 KB No 2 111 MKV56F1M0VLQ24 240 105 144 LQFP 1 MB/256 KB No 2 111 MKV56F1M0VLL24 240 105 100 LQFP 1 MB/256 KB No 2 74 MKV58F512VMD242 240 105 144 MAPBGA 512 KB/128 KB Yes 3 111 MKV58F512VLQ24 240 105 144 LQFP 512 KB/128 KB Yes 3 111 MKV58F512VLL24 240 105 100 LQFP 512 KB/128 KB Yes 3 74 MKV56F512VMD242 240 105 144 MAPBGA 512 KB/128 KB No 2 111 MKV56F512VLQ24 240 105 144 LQFP 512 KB/128 KB No 2 111 MKV56F512VLL24 240 105 100 LQFP 512 KB/128 KB No 2 74 1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search. 2. The 144-pin MAPBGA package for this product is not yet available. However, it is included in a Package Your Way program for Kinetis MCUs. Visit nxp.com/KPYW for more details. Related Resources Type Selector Guide Description The Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Resource Solution Advisor Table continues on the next page... 2 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Related Resources (continued) Type Description Resource Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KV5XP144M240RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. KV5XP144M2401 Chip Errata The chip mask set Errata provides additional or corrective information for KINETIS_V_0N86P1 a particular device mask set. KINETIS_V_1N86P1 Package drawing Package dimensions are provided in package drawings. • MAPBGA 144-pin: 98ASA00222D1 • LQFP 144-pin: 98ASS23177W1 • LQFP 100-pin: 98ASS23308W1 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. KV5x Data Sheet, Rev. 4, 06/2016 3 NXP Semiconductors MMCAU Trace Port JTAG & PPB SWJ-DP Serial Wire AHBD 64b TCM 64KB ITCM 32b TCM 64KB DTCM 32b TCM 64KB DTCM ETM NVIC MPU ITM DSP FPB SFPU DWT Cache Controller 8 KB D$ 16 KB I$ TCM 32b AHBS S0 S1 OSC ARM Cortex-M7 Core TPIU PIT IRC IRC FLL WIC MCG 32-39kHz 4 MHz PLL LPO DMA MUX 32b AHBP 1588 tmr 10/100 ENET eDMA 32 ch 64b AXIM PL301 M0 M1 M1 M0 S0 S1 Crossbar Switch (AXBS x32) S6 SMPU S4 M3 M2 S5 S2 SMPU Port Split OCRAM0 Flash Controller FlexBus S3 64K RAM BME2 RGPIO AHB to IPS x2 x256 Flash 1M Byte flexPWM x4 subm NanoEdge CRC flexPWM x4 subm FlexTimer PMC 3 x flexCAN 8ch + 8ch+ 2ch+2ch 5MSPS-ADC x4 16bit SAR ADC Low-power Timer FlexSCI x6 12-bit DAC TRNG XBARA XBARB AOI ENC DSPI x3 WDOG PDB x2 PIT I2C x2 HSCMP x4 with 6b DAC? EWM Figure 1. KV5x block diagram 4 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Table of Contents 1 Ratings.................................................................................. 6 1.1 Thermal handling ratings............................................... 6 1.2 Moisture handling ratings...............................................6 1.3 ESD handling ratings..................................................... 6 1.4 Voltage and current operating ratings............................6 2 General................................................................................. 7 2.1 AC electrical characteristics...........................................7 2.2 Nonswitching electrical specifications............................7 2.2.1 Operating Requirements....................................7 2.2.2 HVD, LVD, and POR operating requirements....8 2.2.3 PORT Voltage and current operating behaviors 9 2.2.4 Power mode transition operating behaviors.......10 2.2.5 Power consumption operating behaviors...........11 2.2.6 EMC radiated emissions operating behaviors... 15 2.2.7 Designing with radiated emissions in mind........ 16 2.2.8 Capacitance attributes....................................... 16 2.3 Switching specifications................................................. 16 2.3.1 Typical device clock specifications.................... 16 2.3.2 General switching specifications........................17 2.4 Thermal specifications................................................... 18 2.4.1 Thermal operating requirements........................18 2.4.2 Thermal attributes.............................................. 19 3 Peripheral operating requirements and behaviors................ 19 3.1 Core modules................................................................ 19 3.1.1 SWD Electricals ................................................ 19 3.1.2 Debug trace timing specifications...................... 21 3.1.3 JTAG electricals.................................................22 3.2 System modules............................................................ 25 3.3 Clock modules............................................................... 25 3.3.1 MCG specifications............................................ 25 3.3.2 Oscillator electrical specifications...................... 27 3.4 Memories and memory interfaces................................. 29 3.4.1 Flash (FTFE) electrical specifications................ 29 3.5 Flexbus switching specifications.................................... 31 3.6 Security and integrity modules.......................................34 3.7 Analog............................................................................34 3.7.1 12-bit SAR High Speed Analog-to-Digital Converter (HSADC) parameters........................ 35 KV5x Data Sheet, Rev. 4, 06/2016 4 5 6 7 8 3.7.2 ADC electrical specifications..............................37 3.7.3 CMP and 6-bit DAC electrical specifications......42 3.7.4 12-bit DAC electrical characteristics.................. 43 3.8 Timers............................................................................ 46 3.8.1 Enhanced NanoEdge PWM characteristics....... 46 3.9 Communication interfaces............................................. 47 3.9.1 CAN switching specifications............................. 47 3.9.2 Ethernet switching specifications....................... 47 3.9.3 DSPI switching specifications (limited voltage range).................................................................49 3.9.4 DSPI switching specifications (full voltage range).................................................................50 3.9.5 I2C..................................................................... 52 3.9.6 UART................................................................. 52 Dimensions........................................................................... 52 4.1 Obtaining package dimensions......................................52 Pinouts and Packaging......................................................... 53 5.1 KV5x Signal Multiplexing and Pin Assignments............ 53 5.2 KV5x Pinouts................................................................. 62 Ordering parts....................................................................... 64 6.1 Determining valid orderable parts.................................. 64 Part identification...................................................................65 7.1 Description..................................................................... 65 7.2 Format........................................................................... 65 7.3 Fields............................................................................. 65 7.4 Example......................................................................... 66 Terminology and guidelines.................................................. 66 8.1 Definition: Operating requirement.................................. 66 8.2 Definition: Operating behavior....................................... 66 8.3 Definition: Attribute........................................................ 67 8.4 Definition: Rating........................................................... 67 8.5 Result of exceeding a rating.......................................... 67 8.6 Relationship between ratings and operating requirements.................................................................. 68 8.7 Guidelines for ratings and operating requirements........ 68 8.8 Definition: Typical value................................................. 69 8.9 Typical Value Conditions............................................... 70 9 Revision History.................................................................... 70 5 NXP Semiconductors Ratings 1 Ratings 1.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human-body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105 °C -100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-up Test. 1.4 Voltage and current operating ratings 6 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 General Symbol VDD IDD VIO ID VDDA Description Min. Max. Unit Digital supply voltage –0.3 3.6 V — 2201 Digital supply current mA 0.32 Digital pin input voltage (except open drain pins) –0.3 VDD + Instantaneous maximum current single pin limit (applies to all port pins) –25 25 mA VDD – 0.3 VDD + 0.3 V Analog supply voltage V 1. All VDD/VSS pins must be utilized for this value to be valid. 2. Maximum value of VIO must be 3.8 V. 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. VIH Input Signal High Low 80% 50% 20% Midpoint1 Fall Time VIL Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 2. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume: 1. output pins • have CL=30pF loads, • are slew rate disabled, and • are normal drive strength 2.2 Nonswitching electrical specifications KV5x Data Sheet, Rev. 4, 06/2016 7 NXP Semiconductors General 2.2.1 Operating Requirements This section includes information about recommended operating conditions. NOTE Recommended VDD ramp rate is between 1 ms and 200 ms. Table 1. Operating Requirements (VREFLx=0V, VSSA=0V, VSS=0V) Symbol Notes1 Description Min Max Unit VDD Digital supply voltage 1.71 3.6 V VDDA Analog supply voltage VDD 3.6 V VREFHx ADC Reference Voltage High 1.8 VDDA V ΔVDD Voltage difference VDD to VDDA -0.1 0.1 V ΔVSS Voltage difference VSS to VSSA -0.1 0.1 V 0.04 100 MHz 0 240 0.7 x VDD — V 0.35 x VDD V 105 °C F_MCGOU T Device Clock Frequency using internal RC oscillator using external clock source • • VIH Input Voltage High (digital inputs) VIL Input Voltage Low (digital inputs) TA Ambient Operating Temperature -40 1. Default Mode • Pin Group 1: GPIO, TDI, TDO, TMS, TCK • Pin Group 2: RESET • Pin Group 3: ADC and Comparator Analog Inputs • Pin Group 4: XTAL, EXTAL • Pin Group 5: DAC analog output • Pin Group 6: PTB0, PTB1, PTD4, PTD5, PTD6, PTD7, PTC3, and PTC4. have high output current capability 2.2.2 HVD, LVD, and POR operating requirements Table 2. VDD supply HVD, LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold — high range (LVDV=01) 2.48 2.56 2.64 V Low-voltage warning thresholds — high range 1 VLVW1H • Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H • Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H • Level 3 falling (LVWV=10) 2.82 2.90 2.98 V VLVW4H • Level 4 falling (LVWV=11) 2.92 3.00 3.08 V — ±80 — mV VHYSH Low-voltage inhibit reset/recover hysteresis — high range Notes Table continues on the next page... 8 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 General Table 2. VDD supply HVD, LVD and POR operating requirements (continued) Symbol Description Min. Typ. Max. Unit VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VHVDH High Voltage Detect (High Trip Point) — 3.7202 — V VHVDL High Voltage Detect (Low Trip Point) — 3.4582 — V Notes Low-voltage warning thresholds — low range 1 VLVW1L • Level 1 falling (LVWV=00) 1.74 1.80 1.86 V VLVW2L • Level 2 falling (LVWV=01) 1.84 1.90 1.96 V VLVW3L • Level 3 falling (LVWV=10) 1.94 2.00 2.06 V VLVW4L • Level 4 falling (LVWV=11) 2.04 2.10 2.16 V — ±60 — mV VHYSL Low-voltage inhibit reset/recover hysteresis — low range VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage 2.2.3 PORT Voltage and current operating behaviors Table 3. Voltage and current operating behaviors Symbol Min. Typ. Max. Unit Notes 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10 mA VDD – 0.5 — — V 1 1.71 V ≤ VDD ≤ 2.7 V, IOH = -5 mA VDD – 0.5 — — V 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA VDD – 0.5 — — V 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA VDD – 0.5 — — V IOHT Output high current total for all ports — — 100 mA VOL Output low voltage — Normal drive pad except RESET_B 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA — — 0.5 V 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA — — 0.5 V 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA — — 0.5 V 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA — — 0.5 V VOH VOH VOL VOL Description Output high voltage — Normal drive pad except RESET_B Output high voltage — High drive pad except RESET_B 1 1 Output low voltage — High drive pad except RESET_B 1 Output low voltage — RESET_B Table continues on the next page... KV5x Data Sheet, Rev. 4, 06/2016 9 NXP Semiconductors General Table 3. Voltage and current operating behaviors (continued) Symbol IOLT IIN IICIO Description Min. Typ. Max. Unit 2.7 V ≤ VDD ≤ 3.6 V, IOL = 3 mA — — 0.5 V 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA — — 0.5 V Output low current total for all ports — — 100 mA All pins other than high drive port pins — 0.002 0.5 μA High drive port pins — 0.004 0.5 μA IO pin negative DC injection current – single pin. -3 — — mA Notes Input leakage current (per pin) for full temperature range 1, 2 3 VIN < VSS – 0.3V IICcont Contiguous pin DC injection current – regional limit, includes sum of negative injection currents of 16 contiguous pins -25 — — mA VODPU Open drain pullup voltage level VDD — VDD mA 4 RPU Internal pullup resistors 20 — 50 kΩ 5 RPD Internal pulldown resistors 20 — 50 kΩ 6 1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. Measured at VDD=3.6V 3. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN is greater than VIO_MIN (= VSS-0.3 V), then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 4. Open drain outputs must be pulled to VDD. 5. Measured at VDD supply voltage = VDD min and Vinput = VSS 6. Measured at VDD supply voltage = VDD min and Vinput = VDD 2.2.4 Power mode transition operating behaviors All specifications except tPOR and VLLSx→RUN recovery times in the following table assume this clock configuration: • CPU and system clocks = 100 MHz • Bus and flash clock = 25 MHz • FEI clock mode Table 4. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the Min. Typ. Max. Unit — — 300 μs Notes Table continues on the next page... 10 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 General Table 4. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit — — 149 μs — — 149 μs — — 79 μs — — 5.7 μs — — 5.7 μs Notes first instruction across the operating temperature range of the chip. • VLLS0 → RUN • VLLS1 → RUN • VLLS3 → RUN • VLPS → RUN • STOP → RUN 2.2.5 Power consumption operating behaviors NOTE In the following table, the maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3σ). Table 5. Power consumption operating behaviors Symbol IDDA IDD_RUN Description Analog supply current Run mode current — all peripheral clocks disabled, code executing from flash, while(1) loop, excludes ADC IDDA • @ 1.8V Min. Typ. Max. Unit Notes — 5 8 mA HSADC0 and HSADC1 with 66.6 MHz clock, ADC0 with 25 MHz clock. Core frequency of 25 MHz — 7.5 36 mA — 7.6 39 mA • @ 3.0V IDD_RUN Run mode current — all peripheral clocks disabled, code executing from flash, while(1) loop, excludes ADC IDDA • @ 1.8V • @ 3.0V Core frequency of 50 MHz — 10.8 — mA — 10.8 — mA Table continues on the next page... KV5x Data Sheet, Rev. 4, 06/2016 11 NXP Semiconductors General Table 5. Power consumption operating behaviors (continued) Symbol Description Min. IDD_RUN Run mode current — all peripheral clocks disabled, code executing from flash, while(1) loop, excludes ADC IDDA • @ 3.0V • @25°C • @105°C IDD_RUN Typ. Max. Unit Core frequency of 160 MHz. — 27.9 30.0 mA — 44.3 55.7 mA Run mode current — all peripheral clocks disabled, running benchmark code from flash, excludes ADC IDDA • @ 3.0V • @25°C • @105°C — 70.0 — mA — 79.9 — mA IDD_HSRUN Run mode current — all peripheral clocks disabled, code executing from flash, while(1) loop, excludes ADC IDDA • @ 3.0V • @25°C • @105°C Notes CoreMark benchmark compiled using IAR 7.50 with optimization level set to High for Speed with no size constraints option selected. Clock frequencies configured as follows: • Core clock is 160 MHz • Fast Peripher al clock is 80 MHz • Flexbus clock is 26.67 MHz • Bus/ Flash clock is 26.67 MHz Core frequency of 240 MHz. — 43.8 47.1 mA — 62.5 80.8 mA IDD_HSRUN Run mode current — all peripheral clocks enabled, code executing from flash, while(1) loop, excludes ADC IDDA • @ 3.0V Core frequency of 240 MHz. Nanoedge module at 120 MHz. Table continues on the next page... 12 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 General Table 5. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit • @ 25°C — 70.8 74.1 mA • @ 105°C — 92.3 107.9 mA IDD_HSRUN HSRun mode current — all peripheral clocks disabled, running benchmark code from flash, excludes ADC IDDA • @ 3.0V Notes CoreMark benchmark compiled using IAR 7.50 with optimization level set to High for Speed with no size constraints option selected. Clock frequencies configured as follows: • Core clock is 240 MHz • Fast Peripher al clock is 120 MHz • Flexbus clock is 30 MHz • Bus/ Flash clock is 24 MHz — 116 — mA — 132.9 — mA Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 16.3 — mA 160 MHz PEE mode, Fast Peripheral clock = 80 MHz, Flexbus clock = 80 MHz, Bus/ Flash clock = 20 MHz IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 0.729 7.6 mA CPU frequency 4 MHz IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — 1.2 9.4 mA CPU frequency 4 MHz IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled — 0.33 0.43 mA 4 MHz System/ Core clock, Fast peripheral clock, and Flexbus clock. • @ 25°C • @ 105°C IDD_WAIT Table continues on the next page... KV5x Data Sheet, Rev. 4, 06/2016 13 NXP Semiconductors General Table 5. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes 1 MHz bus/ flash clock. All peripheral clocks disabled. Temp = 25°C. IDD_STOP Stop mode current at 3.0 V • @ –40 to 25°C — 0.55 0.91 mA • @ 105°C — 11.1 18.3 mA • @ –40 to 25°C — 0.107 0.33 mA • @ 105°C — 4.0 7.6 mA • @ –40 to 25°C — 5.2 8.6 μA • @ 70°C — 29.8 85 μA • @ 105°C — 122.4 185 μA • @ –40 to 25°C — 3.2 4.8 μA • @ 70°C — 11.6 45 μA • @ 105°C — 47.2 71 μA • @ –40 to 25°C — 0.778 2.6 μA • @ 70°C — 3.9 21 μA • @ 105°C — 18.8 36 μA • @ –40 to 25°C — 0.5 2.1 μA • @ 70°C — 3.4 21 μA • @ 105°C — 18.2 36 μA • @ –40 to 25°C — 0.147 1.69 μA • @ 70°C — 3.0 16.8 μA • @ 105°C — 17.6 29.2 μA IDD_VLPS Very-low-power stop mode current at 3.0 V IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V IDD_VLLS0B Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled IDD_VLLS0A Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled 14 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 General Table 6. Low power mode peripheral adders — typical value Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. 56 56 56 56 56 56 µA IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 32 kHz IRC enabled. 52 52 52 52 52 52 µA IEREFSTEN4MHz External 4 MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled. 206 228 237 245 251 258 uA IEREFSTEN32KHz External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled. nA VLLS1 VLLS3 440 490 540 560 570 580 LLS 440 490 540 560 570 580 VLPS 490 490 540 560 570 680 STOP 510 560 560 560 610 680 510 560 560 560 610 680 22 22 22 22 22 22 ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. MCGIRCLK (4 MHz internal reference clock) OSCERCLK (4 MHz external crystal) IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode. KV5x Data Sheet, Rev. 4, 06/2016 µA µA 66 66 66 66 66 66 214 234 246 254 260 268 45 45 45 45 45 45 µA 15 NXP Semiconductors General 2.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors Symbol VEME Conditions Device configuration, test conditions and EM testing per standard IEC 61967-2. • Supply voltage VDD = 3.3 V • Temperature = 25 °C Clocks Frequency band (MHz) Typ. Unit Notes • fOSC= 20 MHz (crystal) • fSYS = 150 MHz 0.15–50 14 dBμV 1 50–150 25 dBμV 150–500 23 dBμV 500–1000 16 dBμV 0.15–1000 K — 2 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 2.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.nxp.com. 2. Perform a keyword search for “EMC design.” 2.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins — 7 pF CIN_D Input capacitance: digital pins — 7 pF 2.3 Switching specifications 16 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 General 2.3.1 Typical device clock specifications Table 9. Device clock specifications Symbol Description Min. Max. Unit — 240 MHz Notes High Speed run mode fsys System (CPU) clock Normal run mode (and High Speed run mode unless otherwise specified above) fsys System (CPU) clock — 160 MHz Fast Peripheral Clock — 120 MHz FB_CLK FlexBus clock — 60 MHz fBus_Flash Bus / Flash clock — 27.5 MHz — 24 MHz System (CPU) clock — 4 MHz Fast Peripheral Clock — 4 MHz FB_CLK FlexBus clock — 4 MHz fBus_Flash Bus / Flash Clock — 500 kHz fERCLK External reference clock — 16 MHz fLPTMR LPTMR clock — 24 MHz fFastPeripheral fLPTMR LPTMR clock 1 VLPR mode fsys fFastPeripheral 2 1. When using this clock to supply the nano-edge module, this clock must be 1/2 of the system clock. 2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is a clock input connected to the EXTAL pin with the OSC configured for bypass (external clock) operation. 2.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, FlexCAN, and I2C signals. Table 10. General switching specifications Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.5 — Bus clock cycles 1 GPIO pin interrupt pulse width (digital glitch filter enabled, analog filter disabled) — Asynchronous path 80 — ns 2 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) — Asynchronous path 50 — ns 2 External RESET and NMI pin interrupt pulse width — Asynchronous path 100 — ns 2 GPIO pin interrupt pulse width — Asynchronous path 10 — ns 2 Normal drive fast pins 3, 4 • 2.7≤ VDD ≤ 3.6 V Table continues on the next page... KV5x Data Sheet, Rev. 4, 06/2016 17 NXP Semiconductors General Table 10. General switching specifications (continued) Description Min. Max. Unit • Fast slew rate — 0.7 ns • Slow slew rate • 1.71≤ VDD < 2.7 V • Fast slew rate — 16 ns Notes 2.15 16 • Slow slew rate High drive fast pins (normal/low drive enabled) • 2.7≤ VDD ≤ 3.6 V • Fast slew rate • Slow slew rate • 1.71≤ VDD < 2.7 V • Fast slew rate 3, 5 — 0.7 ns — 15.65 ns 2.35 35.3 • Slow slew rate High drive fast pins (high drive enabled) • 2.7≤ VDD ≤ 3.6 V • Fast slew rate • Slow slew rate • 1.71≤ VDD < 2.7 V • Fast slew rate — 3 ns — 16.5 ns 6.5 36.3 • Slow slew rate 1. The synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. For high drive pins with high drive enabled, load is 75pF; other pins load (normal/low drive) is 25pF. Fast slew rate is enabled by clearing PORTx_PCRn[SRE]. 4. Normal drive fast pins: All other GPIO pins that are not high drive fast pins. 5. High drive fast pins: PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7. High drive capability is enabled by setting PORTx_PCRn[DSE] 2.4 Thermal specifications 2.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C Notes 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to determine TJ is: TJ = TA + RθJA x chip power dissipation 18 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors 2.4.2 Thermal attributes Table 12. Thermal attributes Board type Symbol Single-layer (1S) RθJA Four-layer (2s2p) Description 144 MAPBG A1 144 LQFP 100 LQFP Unit Notes Thermal resistance, junction to ambient (natural convection) — 51 51 °C/W 2 RθJA Thermal resistance, junction to ambient (natural convection) — 42 38 °C/W Single-layer (1S) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) — 42 41 °C/W Four-layer (2s2p) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) — 36 32 °C/W — RθJB Thermal resistance, junction to board — 30 23 °C/W 3 — RθJC Thermal resistance, junction to case — 11 10 °C/W 4 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) — 2 2 °C/W 5 1. Package Your Way 2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 3. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 4. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 5. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 3 Peripheral operating requirements and behaviors 3.1 Core modules KV5x Data Sheet, Rev. 4, 06/2016 19 NXP Semiconductors Peripheral operating requirements and behaviors 3.1.1 SWD Electricals Table 13. SWD full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V 0 25 MHz 1/J1 — ns 20 — ns SWD_CLK frequency of operation • Serial wire debug J2 SWD_CLK cycle period J3 SWD_CLK clock pulse width • Serial wire debug J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J2 J3 J3 SWD_CLK (input) J4 J4 Figure 3. Serial wire clock input timing 20 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors SWD_CLK J9 SWD_DIO J10 Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 4. Serial wire data timing 3.1.2 Debug trace timing specifications Table 14. Debug trace operating behaviors Symbol Description Tcyc Clock period Twl Low pulse width 2 — ns Twh High pulse width 2 — ns Tr Clock and data rise time — 3 ns Tf Clock and data fall time — 3 ns Ts Data setup 3 1.5 ns Th Data hold 2 1.0 ns KV5x Data Sheet, Rev. 4, 06/2016 Min. Max. Unit Frequency dependent MHz 21 NXP Semiconductors Peripheral operating requirements and behaviors TRACECLK Tr Tf Twh Twl Tcyc Figure 5. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Th Ts Th TRACE_D[3:0] Figure 6. Trace data specifications 3.1.3 JTAG electricals Table 15. JTAG limited voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 3.6 V TCLK frequency of operation MHz • Boundary Scan 0 10 • JTAG and CJTAG 0 25 • Serial Wire Debug 0 50 1/J1 — ns • Boundary Scan 50 — ns • JTAG and CJTAG 20 — ns • Serial Wire Debug 10 — ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.0 — ns J7 TCLK low to boundary scan output data valid — 28 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J2 TCLK cycle period J3 TCLK clock pulse width Table continues on the next page... 22 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors Table 15. JTAG limited voltage range electricals (continued) Symbol Description Min. Max. Unit J11 TCLK low to TDO data valid — 19 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns Table 16. JTAG full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V TCLK frequency of operation MHz • Boundary Scan 0 10 • JTAG and CJTAG 0 20 • Serial Wire Debug 0 40 1/J1 — ns • Boundary Scan 50 — ns • JTAG and CJTAG 25 — ns • Serial Wire Debug 12.5 — ns J2 TCLK cycle period J3 TCLK clock pulse width J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.0 — ns J7 TCLK low to boundary scan output data valid — 30.6 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.0 — ns J11 TCLK low to TDO data valid — 19.0 ns J12 TCLK low to TDO high-Z — 17.0 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns J2 J3 J3 TCLK (input) J4 J4 Figure 7. Test clock input timing KV5x Data Sheet, Rev. 4, 06/2016 23 NXP Semiconductors Peripheral operating requirements and behaviors TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 8. Boundary scan (JTAG) timing TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 9. Test Access Port timing 24 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors TCLK J14 J13 TRST Figure 10. TRST timing 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 3.3.1 MCG specifications Table 17. MCG specifications Symbol Description Min. Typ. Max. Unit Notes fints_ft Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C — 32.768 — kHz fints_t Internal reference frequency (slow clock) — user trimmed 31.25 — 39.0625 kHz Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM — ± 0.3 ± 0.6 %fdco 1 Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM only — ± 0.2 ± 0.5 %fdco 1 ± 0.5 ±2 %fdco 1, ±1 %fdco 1 Δfdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature — Δfdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70°C — fintf_ft Internal reference frequency (fast clock) — factory trimmed at nominal VDD and 25°C — 4 — MHz fintf_t Internal reference frequency (fast clock) — user trimmed at nominal VDD and 25 °C 3 — 5 MHz (3/5) x fints_t — — kHz floc_low Loss of external clock minimum frequency — RANGE = 00 Table continues on the next page... KV5x Data Sheet, Rev. 4, 06/2016 25 NXP Semiconductors Peripheral operating requirements and behaviors Table 17. MCG specifications (continued) Symbol Description floc_high Loss of external clock minimum frequency — RANGE = 01, 10, or 11 Min. Typ. Max. Unit (16/5) x fints_t — — kHz 31.25 — 39.0625 kHz 20 20.97 25 MHz 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz — 23.99 — MHz — 47.97 — MHz — 71.99 — MHz — 95.98 — MHz — 180 — — 150 — — — 1 ms Notes FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS=00) 2, 3 640 × ffll_ref Mid range (DRS=01) 1280 × ffll_ref Mid-high range (DRS=10) 1920 × ffll_ref High range (DRS=11) 2560 × ffll_ref fdco_t_DMX3 DCO output frequency 2 Low range (DRS=00) 4, 5 732 × ffll_ref Mid range (DRS=01) 1464 × ffll_ref Mid-high range (DRS=10) 2197 × ffll_ref High range (DRS=11) 2929 × ffll_ref Jcyc_fll FLL period jitter • fDCO = 48 MHz • fDCO = 98 MHz tfll_acquire FLL target frequency acquisition time ps 6 PLL 8 — 16 MHz fvcoclk_2x fpll_ref VCO output frequency 220 — 480 MHz fvcoclk PLL output frequency 110 — 240 MHz PLL quadrature output frequency 110 — 240 MHz — 2.8 — mA — 4.7 — mA fvcoclk_90 PLL reference frequency range Ipll PLL operating current • VCO @ 176 MHz (fosc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 22) Ipll PLL operating current • VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 45) Jcyc_pll Jacc_pll PLL period jitter (RMS) 7 7 8 • fvco = 48 MHz — 120 — ps • fvco = 120 MHz — 75 — ps PLL accumulated jitter over 1µs (RMS) 8 Table continues on the next page... 26 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors Table 17. MCG specifications (continued) Symbol Dunl tpll_lock Description Min. Typ. Max. Unit • fvco = 48 MHz — 1350 — ps • fvco = 120 MHz — 600 — ps ± 4.47 — ± 5.97 Lock exit frequency tolerance Lock detector detection time — — 10-6 150 × + 1075(1/ fpll_ref) Notes % s 9 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Excludes any oscillator currents that are also consuming power while PLL is in operation. 8. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.3.2 Oscillator electrical specifications 3.3.2.1 Oscillator DC electrical specifications Table 18. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDOSC IDDOSC Supply current — low-power mode (HGO=0) 1 • 32 kHz — 500 — nA • 4 MHz — 200 — μA • 8 MHz — 300 — μA • 16 MHz — 950 — μA • 24 MHz — 1.2 — mA • 32 MHz — 1.5 — mA Supply current — high gain mode (HGO=1) • 4 MHz Notes 1 — 400 — μA Table continues on the next page... KV5x Data Sheet, Rev. 4, 06/2016 27 NXP Semiconductors Peripheral operating requirements and behaviors Table 18. Oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit • 8 MHz — 500 — μA • 16 MHz — 2.5 — mA • 24 MHz — 3 — mA • 32 MHz — 4 — mA Notes Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, lowpower mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ — 0 — kΩ Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V RS 2, 4 Series resistor — high-frequency, high-gain mode (HGO=1) 5 Vpp 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 28 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors 3.3.2.2 Symbol Oscillator frequency specifications Table 19. Oscillator frequency specifications Min. Typ. Max. Unit Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00) 32 — 40 kHz fec_extal Input clock frequency (external clock mode) — — 48 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) — 1000 — ms fosc_lo tcst Description Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. NOTE The 32 kHz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 3.4 Memories and memory interfaces 3.4.1 Flash (FTFE) electrical specifications This section describes the electrical characteristics of the FTFE module. NOTE All flash programerase functions can only be performed when the MCU is in Normal Run mode. Programming or erasing the flash in HSRUN mode is not allowed. 3.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 20. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm8 Program Phrase high-voltage time — 7.5 18 μs thversscr Erase Flash Sector high-voltage time — 13 113 ms Notes 1 Table continues on the next page... KV5x Data Sheet, Rev. 4, 06/2016 29 NXP Semiconductors Peripheral operating requirements and behaviors Table 20. NVM program/erase timing specifications (continued) Symbol Description thversall1m Erase All Blocks high-voltage time for 1 MB Min. Typ. Max. Unit Notes — 832 7232 ms 1 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Flash timing specifications — commands Table 21. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes trd1sec8k Read 1s Section execution time (8 KB flash) — — 200 μs 1 tpgmchk Program Check execution time — — 95 μs 1 trdrsrc Read Resource execution time — — 40 μs 1 tpgm8 Program Phrase execution time — 90 150 μs tersscr Erase Flash Sector execution time — 15 115 ms Program Section execution time (1KB flash) — 5 — ms trd1allx Read 1s All Blocks execution time — — 1.8 ms trdonce Read Once execution time — — 30 μs Program Once execution time — 90 — μs tersall Erase All Blocks execution time — 870 7400 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tersallu Erase All Blocks Unsecure execution time — 870 7400 ms 2 tpgmsec1k tpgmonce 2 1 1. Assumes 25MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 Flash high voltage current behaviors Table 22. Flash high voltage current behaviors Symbol Description Min. Typ. Max. Unit IDD_PGM Average current adder during high voltage flash programming operation — 3.5 7.5 mA IDD_ERS Average current adder during high voltage flash erase operation — 1.5 4.0 mA 30 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors 3.4.1.4 Symbol Reliability specifications Table 23. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 — years tnvmretp1k Data retention after up to 1 K cycles 20 100 — years nnvmcycp Cycling endurance 10 K 50 K — cycles 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 3.5 Flexbus switching specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 24. Flexbus limited voltage range switching specifications Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation — FB_CLK MHz FB1 Clock period 1/FB_CLK — ns FB2 Address, data, and control output valid — 11.8 ns FB3 Address, data, and control output hold 1.0 — ns FB4 Data and FB_TA input setup 11.9 — ns FB5 Data and FB_TA input hold 0.0 — ns Notes 1 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. Table 25. Flexbus full voltage range switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V Notes Table continues on the next page... KV5x Data Sheet, Rev. 4, 06/2016 31 NXP Semiconductors Peripheral operating requirements and behaviors Table 25. Flexbus full voltage range switching specifications (continued) Num Description Frequency of operation Min. Max. Unit — FB_CLK MHz 1/FB_CLK — ns — 12.6 ns FB1 Clock period FB2 Address, data, and control output valid FB3 Address, data, and control output hold 1.0 — ns FB4 Data and FB_TA input setup 12.5 — ns FB5 Data and FB_TA input hold 0 — ns Notes 1 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. 32 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors Read Timing Parameters S0 S1 S2 S3 S0 FB1 FB_CLK FB5 FB_A[Y] Address FB4 FB2 FB_D[X] FB3 Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn electricals_read.svg FB4 FB_BEn FB5 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ S0 S1 S2 S3 S0 Figure 11. FlexBus read timing diagram KV5x Data Sheet, Rev. 4, 06/2016 33 NXP Semiconductors Peripheral operating requirements and behaviors Write Timing Parameters FB1 FB_CLK FB2 FB3 FB_A[Y] FB_D[X] Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BEn electricals_write.svg FB4 FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 12. FlexBus write timing diagram 3.6 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 3.7 Analog 34 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors 3.7.1 12-bit SAR High Speed Analog-to-Digital Converter (HSADC) parameters Table 26. 12-bit HSADC electrical specifications Characteristic Symbol Min Typ Max Unit Analog supply voltage VDDA 1.71 — 3.6 V Vrefh Supply Voltage • VDDA ≥ 2V Vrefh VDDA VDDA V VSSA 0.1 V Vrefh V Recommended Operating Conditions 2.0 VDDA • VDDA < 2V Vrefl Supply Voltage Vrefl VSSA Analog Input Full-scale input range (single-ended mode) Vrefl Full-scale input range (differential mode) 2*(Vrefh - Vrefl) V Input signal common mode (only for differential mode) (Vrefh + Vrefl)/2 V 5 pF Input sampling capacitance (no parasitic capacitances included) Cs Current Consumption Fs=5MSPS (Conversion in progress, differential mode)1 • IDDA µA — 1150 — — 85 — • IDD Fs=1MSPS (Conversion in progress, differential mode)1 • IDDA µA — 260 — — 19 — • IDD Fs=10kSPS (Conversion in progress, differential mode)1 • IDDA µA — 19 — — 2.9 — • IDD Fs=5MSPS (Conversion in progress, singleended mode)1 • IDDA µA — 1030 — — 85 — • IDD Fs=1MSPS (Conversion in progress, singleended mode)1 • IDDA µA — 230 — — 18 — • IDD Fs=10kSPS (Conversion in progress, singleended mode)1 µA Table continues on the next page... KV5x Data Sheet, Rev. 4, 06/2016 35 NXP Semiconductors Peripheral operating requirements and behaviors Table 26. 12-bit HSADC electrical specifications (continued) Characteristic Symbol • IDDA • IDD Fs=5MSPS (Conversion not in progress) • IDDA Min Typ Max — 19 — — 2.9 — Unit µA • IDD Fs=1MSPS (Conversion not in progress) • IDDA — 38 — — 57 — µA • IDD Fs=10kSPS (Conversion not in progress) • IDDA — 22 — — 14 — µA • IDD — 19 — — 2.7 — Timing Characteristics Input clock frequency fclk 0.14 70 80 MHz Input clock frequency during calibration fclk 0.14 — 60 MHz Sampling rate2 Fs • ADCRES=11 (12 bits conversion result) • ADCRES=10 (10 bits conversion result) • ADCRES=01 (8 bits conversion result) • ADCRES=00 (6 bits conversion result) MSPS 0.01 5 5.71 0.012 5.83 6.66 0.014 7 8 0.0175 8.75 10 Conversion cycle2 (back to back) Clock cycles 14 • ADCRES=11 (12 bits conversion result) 12 • ADCRES=10 (10 bits conversion result) 10 • ADCRES=01 (8 bits conversion result) 8 • ADCRES=00 (6 bits conversion result) Data latency2 Clock cycles 12.5 • ADCRES=11 (12 bits conversion result) 10.5 • ADCRES=10 (10 bits conversion result) 8.5 • ADCRES=01 (8 bits conversion result) 6.5 • ADCRES=00 (6 bits conversion result) Accuracy (DC or Absolute) Integral non-Linearity INL +/- 3.0 LSB Differential non-Linearity DNL +/- 1.0 LSB Table continues on the next page... 36 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors Table 26. 12-bit HSADC electrical specifications (continued) Characteristic Symbol Signal-to-noise and distortion ratio3 Min Typ SINAD Max Unit 65 dBFS Offset error (calibration enabled) +/- 2.0 LSB Offset error (calibration disabled) +/- 64 LSB +/- 5 LSB Total unadjusted error (calibration enabled) TUE 1. Successive conversion mode 2. "ADCRES" refers to the resolution selection control signal 3. Value measured with a –0.5dBFS input signal and then extrapolated to full scale. 3.7.2 ADC electrical specifications The 16-bit accuracy specifications listed in Table 1 and Table 28 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 3.7.2.1 16-bit ADC operating conditions Table 27. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.6 V ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2 ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V VREFL ADC reference voltage low VSSA VSSA VSSA V VADIN Input voltage CADIN Input capacitance RADIN RAS VREFL — VREFH V • 16-bit mode — 8 10 pF • 8-bit / 10-bit / 12-bit modes — 4 5 — 2 5 Input series resistance Analog source resistance (external) kΩ 13-bit / 12-bit modes fADCK < 4 MHz Notes 3 — — 5 kΩ Table continues on the next page... KV5x Data Sheet, Rev. 4, 06/2016 37 NXP Semiconductors Peripheral operating requirements and behaviors Table 27. 16-bit ADC operating conditions (continued) Description Conditions Min. Typ.1 Max. Unit Notes fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 24.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13-bit modes Symbol No ADC hardware averaging 5 20.000 — 818.330 ksps Continuous conversions enabled, subsequent conversion time Crate ADC conversion rate 16-bit mode No ADC hardware averaging 5 37.037 — 461.467 ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. 38 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN VADIN CAS VAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 13. ADC input impedance equivalency diagram 3.7.2.2 16-bit ADC electrical characteristics Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes 0.215 — 1.7 mA 3 • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 IDDA_ADC Supply current ADC asynchronous clock source fADACK Sample Time TUE DNL INL See Reference Manual chapter for sample times Total unadjusted error • 12-bit modes — ±4 ±6.8 • <12-bit modes — ±1.4 ±2.1 Differential nonlinearity • 12-bit modes — ±0.7 –1.1 to +1.9 • <12-bit modes — ±0.2 • 12-bit modes — ±1.0 Integral non-linearity –0.3 to 0.5 –2.7 to +1.9 Table continues on the next page... KV5x Data Sheet, Rev. 4, 06/2016 39 NXP Semiconductors Peripheral operating requirements and behaviors Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description Conditions1 Min. Typ.2 Max. — ±0.5 –0.7 to +0.5 • 12-bit modes — –4 –5.4 • <12-bit modes — –1.4 –1.8 • 16-bit modes — –1 to 0 — • ≤13-bit modes — — ±0.5 • <12-bit modes EFS EQ ENOB Full-scale error Quantization error Effective number of bits Unit Notes LSB4 VADIN = VDDA5 LSB4 16-bit differential mode 6 • Avg = 32 12.8 14.5 • Avg = 4 11.9 13.8 — — bits bits 16-bit single-ended mode • Avg = 32 • Avg = 4 SINAD THD Signal-to-noise plus See ENOB distortion Total harmonic distortion 12.2 13.9 11.4 13.1 — — 6.02 × ENOB + 1.76 16-bit differential mode • Avg = 32 bits bits dB dB — -94 7 — dB 16-bit single-ended mode • Avg = 32 SFDR Spurious free dynamic range — -85 82 95 16-bit differential mode • Avg = 32 16-bit single-ended mode 78 — — dB — dB 7 90 • Avg = 32 EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope VTEMP25 Temp sensor voltage Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 40 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. 8. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input 15.00 14.70 14.40 14.10 ENOB 13.80 13.50 13.20 12.90 12.60 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples 12.30 12.00 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 14. Typical ENOB vs. ADC_CLK for 16-bit differential mode Typical ADC 16-bit Single-Ended ENOB vs ADC Clock 100Hz, 90% FS Sine Input 14.00 13.75 13.50 13.25 13.00 ENOB 12.75 12.50 12.25 12.00 11.75 11.50 11.25 11.00 Averaging of 4 samples Averaging of 32 samples 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 15. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode KV5x Data Sheet, Rev. 4, 06/2016 41 NXP Semiconductors Peripheral operating requirements and behaviors 3.7.3 CMP and 6-bit DAC electrical specifications Table 29. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDHS Supply current, high-speed mode (EN = 1, PMODE = 1) — — 200 μA IDDLS Supply current, low-speed mode (EN = 1, PMODE = 0) — — 20 μA VAIN Analog input voltage VSS — VDD V VAIO Analog input offset voltage — — 20 mV • CR0[HYSTCTR] = 00 — 5 — mV • CR0[HYSTCTR] = 01 — 10 — mV • CR0[HYSTCTR] = 10 — 20 — mV • CR0[HYSTCTR] = 11 — 30 — mV VH Analog comparator hysteresis1 VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN = 1, PMODE = 1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN = 1, PMODE = 0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs 6-bit DAC current adder (enabled) — 7 — μA IDAC6b INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 42 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors CMP Hysteresis vs Vinn 90.00E-03 80.00E-03 CMP Hysteresis (V) 70.00E-03 60.00E-03 HYSTCTR Setting 50.00E-03 0 1 2 3 40.00E-03 30.00E-03 20.00E-03 10.00E-03 000.00E+00 0.1 0.4 0.7 1 1.3 1.6 1.9 Vinn (V) 2.2 2.5 2.8 3.1 Figure 16. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) CMP Hysteresis vs Vinn 180.00E-03 160.00E-03 CMP Hysteresis (V) 140.00E-03 120.00E-03 HYSTCTR Setting 100.00E-03 0 1 2 3 80.00E-03 60.00E-03 40.00E-03 20.00E-03 000.00E+00 -20.00E-03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vinn (V) Figure 17. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 3.7.4 12-bit DAC electrical characteristics KV5x Data Sheet, Rev. 4, 06/2016 43 NXP Semiconductors Peripheral operating requirements and behaviors 3.7.4.1 Symbol 12-bit DAC operating requirements Table 30. 12-bit DAC operating requirements Desciption Min. VDDA Supply voltage VDACR Reference voltage Max. Unit 3.6 V Notes 1.13 3.6 V 1 CL Output load capacitance — 100 pF 2 IL Output load current — 1 mA 1. The DAC reference can be selected to be VDDA or VREFH. 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. 3.7.4.2 Symbol 12-bit DAC operating behaviors Table 31. 12-bit DAC operating behaviors Description IDDA_DACL Supply current — low-power mode Min. Typ. Max. Unit — — 150 μA — — 700 μA Notes P IDDA_DACH Supply current — high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) — low-power mode — 100 200 μs 1 tDACHP Full-scale settling time (0x080 to 0xF7F) — high-power mode — 15 30 μs 1 μs 1 tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) • High-speed mode • Low speed mode — 1 5 Vdacoutl DAC output voltage range low — highspeed mode, no load, DAC set to 0x000 — — 100 mV Vdacouth DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF VDACR −100 — VDACR mV INL Integral non-linearity error — high speed mode — — ±8 LSB 2 DNL Differential non-linearity error — VDACR > 2 V — — ±1 LSB 3 DNL Differential non-linearity error — VDACR = VREF_OUT — — ±1 LSB 4 VOFFSET Offset error — ±0.4 ±0.8 %FSR 5 Gain error — ±0.1 ±0.6 %FSR 5 Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB TCO Temperature coefficient offset voltage — 3.7 — μV/C TGE Temperature coefficient gain error — 0.000421 — %FSR/C Rop Output resistance (load = 3 kΩ) — — 250 Ω SR Slew rate -80h→ F7Fh→ 80h EG PSRR 6 V/μs Table continues on the next page... 44 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors Table 31. 12-bit DAC operating behaviors (continued) Symbol Description BW 1. 2. 3. 4. 5. 6. Min. Typ. Max. • High power (SPHP) 1.2 1.7 — • Low power (SPLP) 0.05 0.12 — 3dB bandwidth Unit Notes kHz • High power (SPHP) 550 — — • Low power (SPLP) 40 — — Settling within ±1 LSB The INL is measured for 0 + 100 mV to VDACR −100 mV The DNL is measured for 0 + 100 mV to VDACR −100 mV The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device 8 6 4 DAC12 INL (LSB) 2 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 18. Typical INL error vs. digital code KV5x Data Sheet, Rev. 4, 06/2016 45 NXP Semiconductors Peripheral operating requirements and behaviors 1.499 DAC12 Mid Level Code Voltage 1.4985 1.498 1.4975 1.497 1.4965 1.496 55 25 -40 85 105 125 Temperature °C Figure 19. Offset at half scale vs. temperature 3.8 Timers See General switching specifications. 3.8.1 Enhanced NanoEdge PWM characteristics Table 32. NanoEdge PWM timing parameters Characteristic Symbol PWM clock frequency NanoEdge Placement (NEP) Step • @ 80 MHz Power-up 46 NXP Semiconductors Typ 80 Size1 Max Unit 120 MHz pwmp • @ 120 MHz Time2 Min tpu ps — 390 — — 260 — 25 µs KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors 1. Temperature and voltage variations do not affect NanoEdge Placement step size. 2. Powerdown to NanoEdge mode transition. 3.9 Communication interfaces 3.9.1 CAN switching specifications See General switching specifications. 3.9.2 Ethernet switching specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 3.9.2.1 MII signal switching specifications The following timing specs meet the requirements for MII style interfaces for a range of transceiver devices. Table 33. MII signal switching specifications Symbol Description Min. Max. — Operating Voltage 1.71 3.6 V — RXCLK frequency — 25 MHz 35% 65% RXCLK MII1 RXCLK pulse width high Unit period MII2 RXCLK pulse width low 35% 65% RXCLK period MII3 RXD[3:0], RXDV, RXER to RXCLK setup 5 — ns MII4 RXCLK to RXD[3:0], RXDV, RXER hold 5 — ns TXCLK frequency — 25 MHz 35% 65% TXCLK — MII5 TXCLK pulse width high period MII6 TXCLK pulse width low 35% 65% TXCLK period MII7 TXCLK to TXD[3:0], TXEN, TXER invalid 2 — ns MII8 TXCLK to TXD[3:0], TXEN, TXER valid — 25 ns KV5x Data Sheet, Rev. 4, 06/2016 47 NXP Semiconductors Peripheral operating requirements and behaviors MII6 MII5 TXCLK (input) MII8 MII7 TXD[n:0] Valid data TXEN Valid data TXER Valid data Figure 20. RMII/MII transmit signal timing diagram MII2 MII1 MII3 MII4 RXCLK (input) RXD[n:0] Valid data RXDV Valid data RXER Valid data Figure 21. RMII/MII receive signal timing diagram 3.9.2.2 RMII signal switching specifications The following timing specs meet the requirements for RMII style interfaces for a range of transceiver devices. Table 34. RMII signal switching specifications Num Description Min. Max. Unit — Operating Voltage 1.71 3.6 — EXTAL frequency (RMII input clock RMII_CLK) — 50 MHz RMII1 RMII_CLK pulse width high 35% 65% RMII_CLK period RMII2 RMII_CLK pulse width low 35% 65% RMII_CLK period RMII3 RXD[1:0], CRS_DV, RXER to RMII_CLK setup 4 — ns RMII4 RMII_CLK to RXD[1:0], CRS_DV, RXER hold 2 — ns Table continues on the next page... 48 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors Table 34. RMII signal switching specifications (continued) Num Description Min. Max. Unit RMII7 RMII_CLK to TXD[1:0], TXEN invalid 4 — ns RMII8 RMII_CLK to TXD[1:0], TXEN valid — 15.4 ns 3.9.3 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 35. Master mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation — 30 MHz 2 x tBUS — ns Notes DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns DS3 DSPI_PCSn to DSPI_SCK output valid (tBUS x 2) − 2 — ns 1 DS4 DSPI_SCK to DSPI_PCSn output hold (tBUS x 2) − 2 — ns 2 DS5 DSPI_SCK to DSPI_SOUT valid — 8.5 ns DS6 DSPI_SCK to DSPI_SOUT invalid −2 — ns DS7 DSPI_SIN to DSPI_SCK input setup 17 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. KV5x Data Sheet, Rev. 4, 06/2016 49 NXP Semiconductors Peripheral operating requirements and behaviors DSPI_PCSn DS3 DS4 DS8 DS7 (CPOL=0) DS1 DS2 DSPI_SCK DSPI_SIN Data First data DSPI_SOUT Last data DS5 DS6 First data Data Last data Figure 22. DSPI classic SPI timing — master mode Table 36. Slave mode DSPI timing (limited voltage range) Num Description Operating voltage Min. Max. Unit 2.7 3.6 V 15 MHz 4 x tBUS — ns (tSCK/2) − 2 (tSCK/2) + 2 ns Frequency of operation DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid — 21 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 15 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 15 ns DSPI_SS DS10 DS9 DSPI_SCK (CPOL=0) DS15 DSPI_SOUT First data DS13 DSPI_SIN DS12 DS16 DS11 Data Last data DS14 First data Data Last data Figure 23. DSPI classic SPI timing — slave mode 50 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Peripheral operating requirements and behaviors 3.9.4 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 37. Master mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit Notes 1.71 3.6 V 1 — 25 MHz 4 x tBUS — ns DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) − 4 — ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) − 4 — ns 3 DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns DS6 DSPI_SCK to DSPI_SOUT invalid -7.8 — ns DS7 DSPI_SIN to DSPI_SCK input setup 24 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DSPI_SCK (CPOL=0) DS7 DSPI_SIN DS4 DS8 First data DSPI_SOUT DS1 DS2 Data Last data DS5 First data DS6 Data Last data Figure 24. DSPI classic SPI timing — master mode Table 38. Slave mode DSPI timing (full voltage range) Num Description Operating voltage Min. Max. Unit 1.71 3.6 V Table continues on the next page... KV5x Data Sheet, Rev. 4, 06/2016 51 NXP Semiconductors Dimensions Table 38. Slave mode DSPI timing (full voltage range) (continued) Num Description Frequency of operation Min. Max. Unit — 12.5 MHz 8 x tBUS — ns (tSCK/2) - 4 (tSCK/2) + 4 ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid — 27.5 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2.5 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 22 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 22 ns DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Data Last data DS14 First data Data Last data Figure 25. DSPI classic SPI timing — slave mode 3.9.5 I2C See General switching specifications. 3.9.6 UART See General switching specifications. 4 Dimensions 52 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Pinouts and Packaging 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to www.nxp.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 144-pin MAPBGA 98ASA00222D 144-pin LQFP 98ASS23177W 100-pin LQFP 98ASS23308W 5 Pinouts and Packaging 5.1 KV5x Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 144 144 100 Pin Name MAP LQFP LQFP BGA Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 D3 1 1 PTE0 HSADC0B _CH16/ HSADC1A _CH0 HSADC0B PTE0 _CH16/ HSADC1A _CH0 SPI1_ PCS1 UART1_ TX XB_ OUT10 XB_IN11 I2C1_SDA TRACE_ CLKOUT D2 2 2 PTE1/ LLWU_P0 HSADC0B _CH17/ HSADC1A _CH1 HSADC0B PTE1/ _CH17/ LLWU_P0 HSADC1A _CH1 SPI1_ SOUT UART1_ RX XB_ OUT11 XB_IN7 I2C1_SCL TRACE_ D3 D1 3 3 PTE2/ LLWU_P1 HSADC0B _CH10/ HSADC1B _CH0 HSADC0B PTE2/ _CH10/ LLWU_P1 HSADC1B _CH0 SPI1_SCK UART1_ CTS_b TRACE_ D2 E4 4 4 PTE3 HSADC0B _CH11/ HSADC1B _CH1 HSADC0B PTE3 _CH11/ HSADC1B _CH1 SPI1_SIN UART1_ RTS_b TRACE_ D1 E5 5 — VDD VDD VDD F6 6 — VSS VSS VSS E3 7 5 PTE4/ LLWU_P2 HSADC1A HSADC1A PTE4/ _CH4/ _CH4/ LLWU_P2 ADC0_ ADC0_ SPI1_ PCS0 UART3_ TX TRACE_ D0 KV5x Data Sheet, Rev. 4, 06/2016 ALT9 53 NXP Semiconductors Pinouts and Packaging 144 144 100 Pin Name MAP LQFP LQFP BGA Default ALT0 SE2/ ADC0_ DP2 SE2/ ADC0_ DP2 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 E2 8 6 PTE5 HSADC1A _CH5/ ADC0_ SE10/ ADC0_ DM2 HSADC1A PTE5 _CH5/ ADC0_ SE10/ ADC0_ DM2 SPI1_ PCS2 UART3_ RX FLEXPWM FTM3_ 1_A0 CH0 E1 9 7 PTE6/ LLWU_ P16 HSADC1B _CH7/ ADC0_ SE4a HSADC1B PTE6/ _CH7/ LLWU_ ADC0_ P16 SE4a SPI1_ PCS3 UART3_ CTS_b FLEXPWM FTM3_ 1_B0 CH1 F4 10 — PTE7 DISABLED PTE7 UART3_ RTS_b FLEXPWM FTM3_ 1_A1 CH2 F3 11 — PTE8 DISABLED PTE8 UART5_ TX FLEXPWM FTM3_ 1_B1 CH3 F2 12 — PTE9/ LLWU_ P17 DISABLED PTE9/ LLWU_ P17 UART5_ RX FLEXPWM FTM3_ 1_A2 CH4 F1 13 — PTE10/ LLWU_ P18 DISABLED PTE10/ LLWU_ P18 UART5_ CTS_b FLEXPWM FTM3_ 1_B2 CH5 G4 14 — PTE11 HSADC1A _CH6/ ADC0_ SE3/ ADC0_ DP3 HSADC1A PTE11 _CH6/ ADC0_ SE3/ ADC0_ DP3 UART5_ RTS_b FLEXPWM FTM3_ 1_A3 CH6 G3 15 — PTE12 HSADC1B _CH6/ ADC0_ SE11/ ADC0_ DM3 HSADC1B PTE12 _CH6/ ADC0_ SE11/ ADC0_ DM3 E6 16 8 VDD VDD VDD F7 17 9 VSS VSS VSS H1 18 10 PTE16 HSADC0A _CH0/ ADC0_ SE1/ ADC0_ DP1 HSADC0A PTE16 _CH0/ ADC0_ SE1/ ADC0_ DP1 SPI0_ PCS0 UART2_ TX FTM_ CLKIN0 FTM0_ FLT3 H2 19 11 PTE17/ LLWU_ P19 HSADC0A _CH1/ ADC0_ SE9/ ADC0_ DM1 HSADC0A PTE17/ _CH1/ LLWU_ ADC0_ P19 SE9/ ADC0_ DM1 SPI0_SCK UART2_ RX FTM_ CLKIN1 LPTMR0_ ALT3 54 NXP Semiconductors ALT7 ALT8 ALT9 FLEXPWM FTM3_ 1_B3 CH7 KV5x Data Sheet, Rev. 4, 06/2016 Pinouts and Packaging 144 144 100 Pin Name MAP LQFP LQFP BGA Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 G1 20 12 PTE18/ LLWU_ P20 HSADC0B _CH0/ ADC0_ SE5a HSADC0B PTE18/ _CH0/ LLWU_ ADC0_ P20 SE5a SPI0_ SOUT UART2_ CTS_b I2C0_SDA G2 21 13 PTE19 HSADC0B _CH1/ ADC0_ SE6a HSADC0B PTE19 _CH1/ ADC0_ SE6a SPI0_SIN UART2_ RTS_b I2C0_SCL H3 22 — VSS VSS VSS J1 23 14 HSADC0A HSADC0A HSADC0A _CH6 _CH6/ _CH6/ ADC0_ ADC0_ SE7a SE7a J2 24 15 HSADC0A _CH7/ ADC0_ SE4b HSADC0A _CH7/ ADC0_ SE4b HSADC0A _CH7/ ADC0_ SE4b K1 25 16 PTE20 HSADC0A _CH8/ ADC0_ SE5b HSADC0A PTE20 _CH8/ ADC0_ SE5b FTM1_ CH0 UART0_ TX FTM1_ QD_PHA K2 26 17 PTE21 HSADC0A _CH9/ HSADC1A _CH7 HSADC0A PTE21 _CH9/ HSADC1A _CH7 FTM1_ CH1 UART0_ RX FTM1_ QD_PHB L1 27 18 HSADC0A _CH2/ HSADC1A _CH2 HSADC0A _CH2/ HSADC1A _CH2 HSADC0A _CH2/ HSADC1A _CH2 L2 28 19 HSADC0A _CH3/ HSADC1A _CH3 HSADC0A _CH3/ HSADC1A _CH3 HSADC0A _CH3/ HSADC1A _CH3 M1 29 20 HSADC0A _CH10/ HSADC1B _CH2 HSADC0A _CH10/ HSADC1B _CH2 HSADC0A _CH10/ HSADC1B _CH2 M2 30 21 HSADC0A _CH11/ HSADC1B _CH3 HSADC0A _CH11/ HSADC1B _CH3 HSADC0A _CH11/ HSADC1B _CH3 H5 31 22 VDDA VDDA VDDA G5 32 23 VREFH VREFH VREFH G6 33 24 VREFL VREFL VREFL H6 34 25 VSSA VSSA VSSA K3 35 — ADC0_ SE0/ ADC0_ ADC0_ SE0/ ADC0_ ADC0_ SE0/ ADC0_ KV5x Data Sheet, Rev. 4, 06/2016 XB_IN9 ALT6 ALT7 ALT8 ALT9 CMP3_ OUT 55 NXP Semiconductors Pinouts and Packaging 144 144 100 Pin Name MAP LQFP LQFP BGA Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 DP0/ DP0/ DP0/ CMP2_IN5 CMP2_IN5 CMP2_IN5 J3 36 — ADC0_ SE8/ ADC0_ DM0/ CMP1_IN2 ADC0_ SE8/ ADC0_ DM0/ CMP1_IN2 ADC0_ SE8/ ADC0_ DM0/ CMP1_IN2 M3 37 26 PTE29 HSADC0A _CH4/ CMP1_ IN5/ CMP0_IN5 HSADC0A PTE29 _CH4/ CMP1_ IN5/ CMP0_IN5 FTM0_ CH2 FTM_ CLKIN0 L3 38 27 PTE30 DAC0_ OUT/ CMP1_ IN3/ HSADC0A _CH5 DAC0_ PTE30 OUT/ CMP1_ IN3/ HSADC0A _CH5 FTM0_ CH3 FTM_ CLKIN1 L4 39 28 HSADC0A _CH12/ CMP0_ IN4/ CMP2_IN3 HSADC0A _CH12/ CMP0_ IN4/ CMP2_IN3 HSADC0A _CH12/ CMP0_ IN4/ CMP2_IN3 L5 40 — PTE13 DISABLED PTE13 M7 41 — PTE22 DISABLED PTE22 FTM2_ CH0 XB_IN2 FTM2_ QD_PHA M6 42 — PTE23 DISABLED PTE23 FTM2_ CH1 XB_IN3 FTM2_ QD_PHB — — 29 VSS VSS VSS L6 43 30 VDD VDD VDD — 44 — VSS VSS VSS M4 45 31 PTE24 HSADC0B _CH4/ HSADC1B _CH4 HSADC0B PTE24 _CH4/ HSADC1B _CH4 CAN1_TX FTM0_ CH0 XB_IN2 I2C0_SCL K5 46 32 PTE25/ LLWU_ P21 HSADC0B _CH5/ HSADC1B _CH5 HSADC0B PTE25/ _CH5/ LLWU_ HSADC1B P21 _CH5 CAN1_RX FTM0_ CH1 XB_IN3 I2C0_SDA EWM_IN K4 47 33 PTE26 DISABLED PTE26 ENET_ 1588_ CLKIN FTM0_ CH4 J4 48 — PTE27 DISABLED PTE27 CAN2_TX H4 49 — PTE28 DISABLED PTE28 CAN2_RX J5 50 34 PTA0 JTAG_ TCLK/ SWD_CLK PTA0 UART0_ CTS_b/ 56 NXP Semiconductors EWM_ OUT_b XB_OUT4 UART4_ TX XB_OUT5 UART4_ RX UART4_ CTS_b UART4_ RTS_b FTM0_ CH5 XB_IN4 EWM_IN JTAG_ TCLK/ SWD_CLK KV5x Data Sheet, Rev. 4, 06/2016 Pinouts and Packaging 144 144 100 Pin Name MAP LQFP LQFP BGA Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 UART0_ COL_b J6 51 35 PTA1 JTAG_TDI PTA1 UART0_ RX FTM0_ CH6 CMP0_ OUT FTM2_ QD_PHA FTM1_ CH1 JTAG_TDI K6 52 36 PTA2 JTAG_ TDO/ TRACE_ SWO PTA2 UART0_ TX FTM0_ CH7 CMP1_ OUT FTM2_ QD_PHB FTM1_ CH0 JTAG_ TDO/ TRACE_ SWO K7 53 37 PTA3 JTAG_ TMS/ SWD_DIO PTA3 UART0_ RTS_b FTM0_ CH0 XB_IN9 EWM_ OUT_b FLEXPWM JTAG_ 0_A0 TMS/ SWD_DIO L7 54 38 PTA4/ LLWU_P3 NMI_b PTA4/ LLWU_P3 FTM0_ CH1 XB_IN10 FTM0_ FLT3 FLEXPWM NMI_b 0_B0 M8 55 39 PTA5 DISABLED PTA5 FTM0_ CH2 RMII0_ RXER/ MII0_ RXER CMP2_ OUT JTAG_ TRST_b E7 56 40 VDD VDD VDD G7 57 41 VSS VSS VSS J7 58 — PTA6 DISABLED PTA6 FTM0_ CH3 CLKOUT TRACE_ CLKOUT J8 59 — PTA7 HSADC1B HSADC1B PTA7 _CH8 _CH8 FTM0_ CH4 RMII0_ MDIO/ MII0_ MDIO TRACE_ D3 K8 60 — PTA8 HSADC1B HSADC1B PTA8 _CH9 _CH9 FTM1_ CH0 RMII0_ MDC/ MII0_MDC TRACE_ D2 L8 61 — PTA9 DISABLED PTA9 FTM1_ CH1 MII0_ RXD3 TRACE_ D1 M9 62 — PTA10/ LLWU_ P22 DISABLED PTA10/ LLWU_ P22 FTM2_ CH0 MII0_ RXD2 FTM2_ QD_PHA L9 63 — PTA11/ LLWU_ P23 DISABLED PTA11/ LLWU_ P23 FTM2_ CH1 MII0_ RXCLK FTM2_ QD_PHB K9 64 42 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_ CH0 RMII0_ RXD1/ MII0_ RXD1 FTM1_ QD_PHA I2C0_SCL J9 65 43 PTA13/ LLWU_P4 CMP2_IN1 CMP2_IN1 PTA13/ LLWU_P4 CAN0_RX FTM1_ CH1 RMII0_ RXD0/ MII0_ RXD0 FTM1_ QD_PHB I2C1_SDA L10 66 44 PTA14 CMP3_IN0 CMP3_IN0 PTA14 SPI0_ PCS0 UART0_ TX KV5x Data Sheet, Rev. 4, 06/2016 CAN2_TX RMII0_ CRS_DV/ MII0_ RXDV TRACE_ D0 I2C0_SDA I2C1_SCL 57 NXP Semiconductors Pinouts and Packaging 144 144 100 Pin Name MAP LQFP LQFP BGA Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT6 ALT7 ALT8 L11 67 45 PTA15 CMP3_IN1 CMP3_IN1 PTA15 SPI0_SCK UART0_ RX K10 68 46 PTA16 CMP3_IN2 CMP3_IN2 PTA16 SPI0_ SOUT UART0_ CTS_b/ UART0_ COL_b RMII0_ TXD0/ MII0_TXD0 K11 69 47 PTA17 HSADC0A HSADC0A PTA17 _CH15 _CH15 SPI0_SIN UART0_ RTS_b RMII0_ TXD1/ MII0_TXD1 E8 70 48 VDD VDD VDD G8 71 49 VSS VSS VSS M12 72 50 PTA18 EXTAL0 EXTAL0 PTA18 XB_IN7 FTM0_ FLT2 FTM_ CLKIN0 XB_OUT8 FTM3_ CH2 M11 73 51 PTA19 XTAL0 XTAL0 PTA19 XB_IN8 FTM1_ FLT0 FTM_ CLKIN1 XB_OUT9 LPTMR0_ ALT1 L12 74 52 RESET_b RESET_b RESET_b K12 75 — PTA24 DISABLED PTA24 XB_IN4 MII0_TXD2 FB_A29 J12 76 — PTA25 DISABLED PTA25 XB_IN5 MII0_ TXCLK FB_A28 J11 77 — PTA26 DISABLED PTA26 MII0_TXD3 FB_A27 J10 78 — PTA27 DISABLED PTA27 MII0_CRS FB_A26 H12 79 — PTA28 DISABLED PTA28 MII0_ TXER FB_A25 H11 80 — PTA29 DISABLED PTA29 MII0_COL FB_A24 H10 81 53 PTB0/ LLWU_P5 HSADC0B HSADC0B PTB0/ _CH2 _CH2 LLWU_P5 I2C0_SCL H9 82 54 PTB1 HSADC0B HSADC0B PTB1 _CH3 _CH3 I2C0_SDA FTM1_ CH1 FTM0_ FLT2 G12 83 55 PTB2 HSADC0A HSADC0A PTB2 _CH14/ _CH14/ CMP2_IN2 CMP2_IN2 I2C0_SCL FTM0_ FLT1 G11 84 56 PTB3 HSADC0B HSADC0B PTB3 _CH15/ _CH15/ CMP3_IN5 CMP3_IN5 I2C0_SDA UART0_ CTS_b/ UART0_ COL_b G10 85 — PTB4 ADC0_ SE6b ADC0_ SE6b G9 86 — PTB5 ADC0_ SE7b ADC0_ SE7b 58 NXP Semiconductors CAN2_RX ALT5 RMII0_ TXEN/ MII0_ TXEN FTM1_ CH0 FTM1_ QD_PHA UART0_ RX RMII0_ MDIO/ MII0_ MDIO EWM_IN FTM1_ QD_PHB UART0_ TX RMII0_ MDC/ MII0_MDC ENET0_ 1588_ TMR0 FTM0_ FLT3 ENET0_ 1588_ TMR1 FTM0_ FLT0 PTB4 FLEXPWM ENET0_ 1_X0 1588_ TMR2 FTM1_ FLT0 PTB5 FLEXPWM ENET0_ 1_X1 1588_ TMR3 FTM2_ FLT0 UART0_ RTS_b ALT9 KV5x Data Sheet, Rev. 4, 06/2016 Pinouts and Packaging 144 144 100 Pin Name MAP LQFP LQFP BGA Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 F12 87 — PTB6 HSADC1A HSADC1A PTB6 _CH12 _CH12 CAN2_TX FLEXPWM 1_X2 FB_AD23 F11 88 — PTB7 HSADC1A HSADC1A PTB7 _CH13 _CH13 CAN2_RX FLEXPWM 1_X3 FB_AD22 F10 89 — PTB8 DISABLED PTB8 F9 90 57 PTB9 DISABLED PTB9 E12 91 58 PTB10 E11 92 59 H7 93 UART3_ RTS_b FB_AD21 SPI1_ PCS1 UART3_ CTS_b ENET0_ 1588_ TMR2 HSADC0B HSADC0B PTB10 _CH6 _CH6 SPI1_ PCS0 UART3_ RX ENET0_ 1588_ TMR3 PTB11 HSADC0B HSADC0B PTB11 _CH7 _CH7 SPI1_SCK UART3_ TX 60 VSS VSS VSS VDD FB_AD20 FTM0_ FLT1 FB_AD19 FTM0_ FLT2 FB_AD18 F5 94 61 VDD VDD E10 95 62 PTB16 DISABLED PTB16 SPI1_ SOUT UART0_ RX FTM_ CLKIN2 CAN0_TX EWM_IN E9 96 63 PTB17 DISABLED PTB17 SPI1_SIN UART0_ TX FTM_ CLKIN1 CAN0_RX EWM_ OUT_b D12 97 64 PTB18 DISABLED PTB18 CAN0_TX FTM2_ CH0 FTM3_ CH2 FLEXPWM FTM2_ 1_A1 QD_PHA FB_AD15 D11 98 65 PTB19 DISABLED PTB19 CAN0_RX FTM2_ CH1 FTM3_ CH3 FLEXPWM FTM2_ 1_B1 QD_PHB FB_OE_b D10 99 66 PTB20 DISABLED PTB20 SPI2_ PCS0 FLEXPWM CMP0_ 0_X0 OUT FB_AD31 D9 100 67 PTB21 DISABLED PTB21 SPI2_SCK FLEXPWM CMP1_ 0_X1 OUT FB_AD30 C12 101 68 PTB22 DISABLED PTB22 SPI2_ SOUT FLEXPWM CMP2_ 0_X2 OUT FB_AD29 C11 102 69 PTB23 DISABLED PTB23 SPI2_SIN SPI0_ PCS5 FLEXPWM CMP3_ 0_X3 OUT FB_AD28 B12 103 70 PTC0 HSADC0B HSADC0B PTC0 _CH8 _CH8 SPI0_ PCS4 PDB0_ EXTRG B11 104 71 PTC1/ LLWU_P6 HSADC0B HSADC0B PTC1/ _CH9 _CH9 LLWU_P6 SPI0_ PCS3 UART1_ RTS_b FTM0_ CH0 FLEXPWM XB_IN11 0_A3 FB_AD13 A12 105 72 PTC2 HSADC1B HSADC1B PTC2 _CH10/ _CH10/ CMP1_IN0 CMP1_IN0 SPI0_ PCS2 UART1_ CTS_b FTM0_ CH1 FLEXPWM XB_IN6 0_B3 FB_AD12 A11 106 73 PTC3/ LLWU_P7 CMP1_IN1 CMP1_IN1 PTC3/ LLWU_P7 SPI0_ PCS1 UART1_ RX FTM0_ CH2 CLKOUT H8 107 74 VSS VSS VSS — 108 75 VDD VDD VDD A9 109 76 PTC4/ LLWU_P8 DISABLED SPI0_ PCS0 UART1_ TX FTM0_ CH3 KV5x Data Sheet, Rev. 4, 06/2016 PTC4/ LLWU_P8 ALT9 FTM0_ FLT1 XB_IN5 FB_AD17 FB_AD16 SPI0_ PCS0 FB_AD14 FTM3_ FLT0 CMP1_ OUT FB_AD11 59 NXP Semiconductors Pinouts and Packaging 144 144 100 Pin Name MAP LQFP LQFP BGA Default D8 110 77 PTC5/ LLWU_P9 DISABLED C8 111 78 PTC6/ LLWU_ P10 B8 112 79 A8 113 D7 ALT0 ALT1 PTC5/ LLWU_P9 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 SPI0_SCK LPTMR0_ ALT2 XB_IN2 CMP2_ CMP2_ PTC6/ IN4/ IN4/ LLWU_ CMP0_IN0 CMP0_IN0 P10 SPI0_ SOUT XB_IN3 PTC7 CMP3_ CMP3_ PTC7 IN4/ IN4/ CMP0_IN1 CMP0_IN1 SPI0_SIN XB_IN4 80 PTC8 HSADC1B HSADC1B PTC8 _CH11/ _CH11/ CMP0_IN2 CMP0_IN2 FTM3_ CH4 FLEXPWM 1_A2 FB_AD7 114 81 PTC9 HSADC1B HSADC1B PTC9 _CH12/ _CH12/ CMP0_IN3 CMP0_IN3 FTM3_ CH5 FLEXPWM 1_B2 FB_AD6 C7 115 82 PTC10 HSADC1B HSADC1B PTC10 _CH13 _CH13 I2C1_SCL FTM3_ CH6 FLEXPWM 1_A3 FB_AD5 B7 116 83 PTC11/ LLWU_ P11 HSADC1B HSADC1B PTC11/ _CH14 _CH14 LLWU_ P11 I2C1_SDA FTM3_ CH7 FLEXPWM 1_B3 FB_RW_b A7 117 84 PTC12 DISABLED PTC12 CAN2_TX FTM_ CLKIN0 FLEXPWM FTM3_ 1_A1 FLT0 D6 118 85 PTC13 DISABLED PTC13 CAN2_RX FTM_ CLKIN1 C6 119 86 PTC14 DISABLED PTC14 I2C1_SCL B6 120 87 PTC15 DISABLED — 121 88 VSS VSS VSS — 122 89 VDD VDD VDD A6 123 90 PTC16 D5 124 91 C5 125 B5 126 PDB0_ EXTRG CMP0_ OUT FTM0_ CH2 FB_AD10 UART0_ RX XB_OUT6 I2C0_SCL FB_AD9 UART0_ TX XB_OUT7 I2C0_SDA FB_AD8 FB_AD27 UART4_ RTS_b FLEXPWM 1_B1 FB_AD26 UART4_ CTS_b I2C0_SCL FLEXPWM 1_A0 FB_AD25 UART4_ RX PTC15 I2C1_SDA I2C0_SDA FLEXPWM 1_B0 FB_AD24 UART4_ TX DISABLED PTC16 CAN1_RX UART3_ RX ENET0_ 1588_ TMR0 FLEXPWM 1_A2 FB_CS5_ b/ FB_TSIZ1/ FB_BE23_ 16_b PTC17 DISABLED PTC17 CAN1_TX UART3_ TX ENET0_ 1588_ TMR1 FLEXPWM 1_B2 FB_CS4_ b/ FB_TSIZ0/ FB_BE31_ 24_b 92 PTC18 DISABLED PTC18 UART3_ RTS_b ENET0_ 1588_ TMR2 FLEXPWM 1_A3 FB_TBST_ b/ FB_CS2_ b/ FB_BE15_ 8_b — PTC19 DISABLED PTC19 UART3_ CTS_b ENET0_ 1588_ TMR3 FLEXPWM 1_B3 FB_CS3_ b/ 60 NXP Semiconductors SPI2_ PCS1 ALT9 FB_TA_b KV5x Data Sheet, Rev. 4, 06/2016 Pinouts and Packaging 144 144 100 Pin Name MAP LQFP LQFP BGA Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 FB_BE7_ 0_b A5 127 93 PTD0/ LLWU_ P12 DISABLED D4 128 94 PTD1 C4 129 95 B4 130 A4 UART2_ RTS_b FTM3_ CH0 FTM0_ CH0 FLEXPWM 0_A0 FB_ALE/ FB_CS1_ b/ FB_TS_b HSADC1A HSADC1A PTD1 _CH11 _CH11 SPI0_SCK UART2_ CTS_b FTM3_ CH1 FTM0_ CH1 FLEXPWM 0_B0 FB_CS0_b FLEXPWM 1_B0 PTD2/ LLWU_ P13 DISABLED PTD2/ LLWU_ P13 SPI0_ SOUT UART2_ RX FTM3_ CH2 FTM0_ CH2 FLEXPWM I2C0_SCL 0_A1 FB_AD4 FLEXPWM 1_A1 96 PTD3 DISABLED PTD3 SPI0_SIN UART2_ TX FTM3_ CH3 FTM0_ CH3 FLEXPWM I2C0_SDA FB_AD3 0_B1 FLEXPWM 1_B1 131 97 PTD4/ LLWU_ P14 DISABLED PTD4/ LLWU_ P14 SPI0_ PCS1 UART0_ RTS_b FTM0_ CH4 FLEXPWM EWM_IN 0_A2 SPI1_ PCS0 A3 132 98 PTD5 HSADC1A HSADC1A PTD5 _CH8 _CH8 SPI0_ PCS2 UART0_ CTS_b/ UART0_ COL_b FTM0_ CH5 FLEXPWM EWM_ 0_B2 OUT_b SPI1_SCK FB_AD1 A2 133 99 PTD6/ LLWU_ P15 HSADC1A HSADC1A PTD6/ _CH9 _CH9 LLWU_ P15 SPI0_ PCS3 UART0_ RX FTM0_ CH6 FTM1_ CH0 FTM0_ FLT0 SPI1_ SOUT M10 134 — VSS VSS VSS F8 135 — VDD VDD VDD A1 136 100 PTD7 DISABLED PTD7 UART0_ TX FTM0_ CH7 FTM1_ CH1 FTM0_ FLT1 SPI1_SIN C9 137 — PTD8/ LLWU_ P24 DISABLED PTD8/ LLWU_ P24 I2C1_SCL UART5_ RX FLEXPWM 0_A3 FB_A16 B9 138 — PTD9 DISABLED PTD9 I2C1_SDA UART5_ TX FLEXPWM 0_B3 FB_A17 B3 139 — PTD10 DISABLED PTD10 UART5_ RTS_b FLEXPWM 0_A2 FB_A18 B2 140 — PTD11/ LLWU_ P25 DISABLED PTD11/ LLWU_ P25 SPI2_ PCS0 UART5_ CTS_b FLEXPWM 0_B2 FB_A19 B1 141 — PTD12 DISABLED PTD12 SPI2_SCK FTM3_ FLT0 XB_IN5 XB_OUT5 FLEXPWM 0_A1 FB_A20 C3 142 — PTD13 DISABLED PTD13 SPI2_ SOUT XB_IN7 XB_OUT7 FLEXPWM 0_B1 FB_A21 C2 143 — PTD14 DISABLED PTD14 SPI2_SIN XB_IN11 XB_ OUT11 FLEXPWM 0_A0 FB_A22 C1 144 — PTD15 DISABLED PTD15 SPI2_ PCS1 FLEXPWM 0_B0 FB_A23 KV5x Data Sheet, Rev. 4, 06/2016 PTD0/ LLWU_ P12 SPI0_ PCS0 FLEXPWM 1_A0 FB_AD2 FB_AD0 61 NXP Semiconductors Pinouts and Packaging 5.2 KV5x Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. 1 2 3 4 5 6 7 8 9 A PTD7 PTD6/ LLWU_P15 PTD5 PTD4/ LLWU_P14 PTD0/ LLWU_P12 PTC16 PTC12 PTC8 B PTD12 PTD11/ LLWU_P25 PTD10 PTD3 PTC19 PTC15 PTC11/ LLWU_P11 C PTD15 PTD14 PTD13 PTD2/ LLWU_P13 PTC18 PTC14 D PTE2/ LLWU_P1 PTE1/ LLWU_P0 PTE0 PTD1 PTC17 E PTE6/ LLWU_P16 PTE5 PTE4/ LLWU_P2 PTE3 F PTE10/ LLWU_P18 PTE9/ LLWU_P17 PTE8 G PTE18/ LLWU_P20 PTE19 H PTE16 J 11 12 PTC4/ LLWU_P8 PTC3/ LLWU_P7 PTC2 A PTC7 PTD9 PTC1/ LLWU_P6 PTC0 B PTC10 PTC6/ LLWU_P10 LLWU_P24 PTB23 PTB22 C PTC13 PTC9 PTC5/ LLWU_P9 PTB21 PTB20 PTB19 PTB18 D VDD VDD VDD VDD PTB17 PTB16 PTB11 PTB10 E PTE7 VDD VSS VSS VDD PTB9 PTB8 PTB7 PTB6 F PTE12 PTE11 VREFH VREFL VSS VSS PTB5 PTB4 PTB3 PTB2 G PTE17/ LLWU_P19 VSS PTE28 VDDA VSSA VSS VSS PTB1 PTB0/ LLWU_P5 PTA29 PTA28 H HSADC0A_ CH6 HSADC0A_ CH7/ ADC0_SE4b ADC0_SE8/ ADC0_DM0/ CMP1_IN2 PTE27 PTA0 PTA1 PTA6 PTA7 PTA13/ LLWU_P4 PTA27 PTA26 PTA25 J K PTE20 PTE21 ADC0_SE0/ ADC0_DP0/ CMP2_IN5 PTE26 PTE25/ LLWU_P21 PTA2 PTA3 PTA8 PTA12 PTA16 PTA17 PTA24 K L HSADC0A_ CH2/ HSADC1A_ CH2 HSADC0A_ CH3/ HSADC1A_ CH3 PTE30 HSADC0A_ CH12/ CMP0_IN4/ CMP2_IN3 PTE13 VDD PTA4/ LLWU_P3 PTA9 PTA11/ LLWU_P23 PTA14 PTA15 RESET_b L M HSADC0A_ CH10/ HSADC1B_ CH2 HSADC0A_ CH11/ HSADC1B_ CH3 PTE29 PTE24 PTE23 PTE22 PTA5 PTA10/ LLWU_P22 VSS PTA19 PTA18 M 1 2 3 4 6 7 8 9 10 11 12 5 10 PTD8/ Figure 26. 144 MAPBGA Pinout Diagram 62 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 111 110 109 PTC13 PTC8 PTC14 118 112 PTC15 119 PTC9 VSS 120 113 VDD 121 PTC10 PTC16 122 115 PTC17 123 114 PTC18 124 PTC12 PTC19 125 PTC11/LLWU_P11 PTD0/LLWU_P12 126 116 PTD1 127 117 PTD2/LLWU_P13 VSS 134 128 VDD 135 PTD3 PTD7 136 129 PTD8/LLWU_P24 137 PTD4/LLWU_P14 PTD9 138 131 PTD10 139 130 PTD11/LLWU_P25 140 PTD6/LLWU_P15 PTD12 141 PTD5 PTD13 142 132 PTD14 143 133 PTD15 144 Pinouts and Packaging PTE0 1 108 VDD PTE1/LLWU_P0 2 107 VSS PTE2/LLWU_P1 3 106 PTC3/LLWU_P7 PTE3 4 105 PTC2 VDD 5 104 PTC1/LLWU_P6 VSS 6 103 PTC0 PTE4/LLWU_P2 7 102 PTB23 PTE5 8 101 PTB22 PTE6/LLWU_P16 9 100 PTB21 PTB20 PTE7 10 99 PTE8 11 98 PTB19 PTE9/LLWU_P17 12 97 PTB18 PTE10/LLWU_P18 13 96 PTB17 PTE11 14 95 PTB16 PTE12 15 94 VDD VDD 16 93 VSS VSS 17 92 PTB11 PTE16 18 91 PTB10 PTE17/LLWU_P19 19 90 PTB9 PTE18/LLWU_P20 20 89 PTB8 PTE19 21 88 PTB7 VSS 22 87 PTB6 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VDD VSS PTA6 PTA7 PTA8 PTA9 PTA10/LLWU_P22 PTA11/LLWU_P23 PTA12 PTA13/LLWU_P4 PTA14 PTA15 PTA16 PTA17 VDD VSS PTA18 PTA19 55 RESET_b 73 PTA5 74 36 54 35 PTA4/LLWU_P3 ADC0_SE0/ADC0_DP0/CMP2_IN5 ADC0_SE8/ADC0_DM0/CMP1_IN2 53 PTA24 PTA3 75 52 34 PTA2 PTA25 VSSA 51 PTA26 76 50 77 33 PTA1 32 VREFL PTA0 VREFH 49 PTA27 PTE28 78 48 31 PTE27 PTA28 VDDA 47 79 PTE26 30 46 PTA29 HSADC0A_CH11/HSADC1B_CH3 PTE25/LLWU_P21 80 45 29 PTE24 PTB0/LLWU_P5 HSADC0A_CH10/HSADC1B_CH2 44 81 VSS 28 43 PTB1 HSADC0A_CH3/HSADC1A_CH3 VDD 82 42 27 PTE23 PTB2 HSADC0A_CH2/HSADC1A_CH2 41 83 PTE22 26 40 PTB3 PTE21 PTE13 84 39 25 HSADC0A_CH12/CMP0_IN4/CMP2_IN3 PTB4 PTE20 38 PTB5 85 37 86 24 PTE30 23 PTE29 HSADC0A_CH6 HSADC0A_CH7/ADC0_SE4b Figure 27. 144 LQFP Pinout Diagram KV5x Data Sheet, Rev. 4, 06/2016 63 NXP Semiconductors PTC16 VDD VSS PTC15 PTC14 PTC13 PTC12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 90 89 88 87 86 85 84 83 82 81 80 PTC4/LLWU_P8 PTC17 91 PTC5/LLWU_P9 PTC18 92 76 PTD0/LLWU_P12 93 77 PTD1 94 PTC7 PTD2/LLWU_P13 95 PTC6/LLWU_P10 PTD3 96 79 PTD4/LLWU_P14 97 78 PTD5 98 PTD7 PTD6/LLWU_P15 100 99 Ordering parts PTE0 1 75 VDD PTE1/LLWU_P0 2 74 VSS PTE2/LLWU_P1 3 73 PTC3/LLWU_P7 PTE3 4 72 PTC2 PTE4/LLWU_P2 5 71 PTC1/LLWU_P6 PTE5 6 70 PTC0 PTE6/LLWU_P16 7 69 PTB23 VDD 8 68 PTB22 9 67 PTB21 PTE16 10 66 PTB20 PTE17/LLWU_P19 11 65 PTB19 PTE18/LLWU_P20 12 64 PTB18 PTE19 13 63 PTB17 VSS 47 48 49 50 VSS PTA18 46 PTA16 VDD 45 PTA15 PTA17 44 PTA14 PTA19 43 51 42 25 PTA12 VSSA PTA13/LLWU_P4 RESET_b VSS VREFL 41 PTB0/LLWU_P5 52 40 53 24 VDD 23 39 VREFH PTA5 PTB1 38 54 PTA4/LLWU_P3 22 37 PTB2 VDDA 36 55 PTA3 21 PTA2 PTB3 HSADC0A_CH11/HSADC1B_CH3 35 56 PTA1 20 34 PTB9 HSADC0A_CH10/HSADC1B_CH2 PTA0 57 33 19 PTE26 HSADC0A_CH3/HSADC1A_CH3 32 PTB10 31 58 PTE24 18 PTE25/LLWU_P21 PTB11 HSADC0A_CH2/HSADC1A_CH2 VDD 59 30 17 29 VSS PTE21 28 60 VSS 16 HSADC0A_CH12/CMP0_IN4/CMP2_IN3 VDD PTE20 27 PTB16 61 26 62 15 PTE30 14 PTE29 HSADC0A_CH6 HSADC0A_CH7/ADC0_SE4b Figure 28. 100 LQFP Pinout Diagram 6 Ordering parts 64 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Part identification 6.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.nxp.com and perform a part number search for the MKV5x device numbers. 7 Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 7.2 Format Part numbers for this device have the following format: Q KV## A FFF T PP CC N 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Prequalification KV## Kinetis family • KV58 • KV56 A Key attribute • F = Cortex-M7 FFF Program flash memory size • 1M0 = 1 MB • 512 = 512 KB T Temperature range (°C) • V = –40 to 105 PP Package identifier • LQ = 144 LQFP (20 mm x 20 mm) • LL = 100 LQFP (14 mm x 14 mm) • MD = 144 MAPBGA (13 mm x 13 mm) CC Maximum CPU frequency (MHz) • 24 = 240 MHz N Packaging type • R = Tape and reel • (Blank) = Trays KV5x Data Sheet, Rev. 4, 06/2016 65 NXP Semiconductors Terminology and guidelines 7.4 Example This is an example part number: MKV58F1M0VLQ24 MKV56F512VLL24 8 Terminology and guidelines 8.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 8.1.1 Example This is an example of an operating requirement: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V 8.2 Definition: Operating behavior Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 8.2.1 Example This is an example of an operating behavior: 66 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Terminology and guidelines Symbol IWP Description Min. Digital I/O weak pullup/ 10 pulldown current Max. 130 Unit µA 8.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 8.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. — Max. 7 Unit pF 8.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 8.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage KV5x Data Sheet, Rev. 4, 06/2016 Min. –0.3 Max. 1.2 Unit V 67 NXP Semiconductors Terminology and guidelines 8.5 Result of exceeding a rating Failures in time (ppm) 40 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic 8.6 Relationship between ratings and operating requirements g( g tin era Op in rat i (m nt me n.) mi g tin era Op n.) e uir req g tin era Op t en em uir q re ax (m .) x ma g( g tin era in rat .) Op Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure –∞ ∞ Operating (power on) dli n Ha ng x.) n.) mi g( in rat li nd Ha ng a (m ing rat Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ ∞ Handling (power off) 8.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 68 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Terminology and guidelines 8.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 8.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol IWP Description Digital I/O weak pullup/pulldown current Min. 10 Typ. 70 Max. 130 Unit µA 8.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: KV5x Data Sheet, Rev. 4, 06/2016 69 NXP Semiconductors Revision History 5000 4500 4000 TJ 3500 150 °C IDD_STOP (μA) 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.95 0.90 1.00 1.05 1.10 VDD (V) 8.9 Typical Value Conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V 9 Revision History The following table provides a revision history for this document. Table 39. Revision History Rev. No. Date 0 02/2015 1 06/2015 Substantial Changes Initial release • Updated the features list to include FlexBus, TRNG, MMCAU, Advanced WatchDog Timer and JTAG modules • Updated the ordering information table to highlight differences in the parts in terms of flash, SRAM, modules or instances. Table continues on the next page... 70 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 Revision History Table 39. Revision History (continued) Rev. No. Date Substantial Changes • Added KV5x block diagram • Editorial changes in the table "Recommended Operating Conditions." • Removed the Typical values column from the table "Recommended Operating Conditions." • Removed the following parameters from the table "Recommended Operating Conditions." • Output Source Current High (IOH) • Output Source Current Low (IOL) • Oscillator Input Voltage High(VIHOSC) • Oscillator Input Voltage Low (VILOSC) • DAC Output Current Drive Strength (Cout) • Added HVD characteristics to the table "LVD, and POR operating requirements" and changed the title to HVD, LVD, and POR operating requirements." • Added the following parameters to the table "Voltage and current operating behaviors" • Output high current total for all ports (IOHT) • Output low current total for all ports (IOHL) • Internal pull-down resistance (RPD) • Removed the footnote "PTC6 and PTC7 are true open drain so have no high drive output transistor so there is no VOH spec for them. These pins must be terminated with a pull-up resistor to VDD" from the table "Voltage and current operating behaviors" • Added a note above the table "Low power mode peripheral adders — typical value" suggesting that the values are preliminary data. • Updated the notes in the table "Power consumption operating behaviors" for run mode currents with all peripherals disabled. • Updated the table "EMC radiated emissions operating behaviors" by splitting description column into Conditions and Clocks columns. • Changed Typ. values to TBDs in the table "EMC radiated emissions operating behaviors." • Updated the table "Typical device clock specifications" • Added a footnote to the ambient temperature entry in the table "Thermal operating requirements" • Updated the table "Thermal attributes" • Changed ADC to HSADC in the title of the section "12-bit SAR High Speed Analog-toDigital Converter (ADC) parameters" • Changed minimum operating voltage value from 2.7 V to 1.71 V in the table "MII signal switching specifications" and RMII signal switching specifications." 2 10/2015 • Updated the part numbers in the table Orderable part numbers summary and the front page • In the features list: • Updated the instances of UART and SPI modules • Added Ether module to the list of communication interfaces • Remove Micro Trace Buffer from the list of System peripherals • In table Operating Requirements, removed rows for NF, TR, and tFLRET • In table PORT Voltage and current operating behaviors, added IICIO, IICcont, and VODPU rows • Updated table Power mode transition operating behaviors • Updated table Power consumption operating behaviors • Updated table EMC radiated emissions operating behaviors • Updated table General switching specifications • In section DSPI switching specifications (limited voltage range) • Removed the notes • Removed table "Master mode DSPI timing for fast pads (limited voltage range)" Table continues on the next page... KV5x Data Sheet, Rev. 4, 06/2016 71 NXP Semiconductors Revision History Table 39. Revision History (continued) Rev. No. Date Substantial Changes • Removed the tbale "Master mode DSPI timing for open drain pads (limited voltage range)" • Removed the table "Slave mode DSPI timing for fast pads (limited voltage range)" • Removed the table "Slave mode DSPI timing for open drain pads (limited voltage range)" • Removed the table "Master mode DSPI timing fast pads (full voltage range)" • Removed the table "Master mode DSPI timing open drain pads (full voltage range)" • Removed the table "Slave mode DSPI timing for fast pads (full voltage range)" • Removed the table "Slave mode DSPI timing for open drain pads (full voltage range)" • Updated the pinouts • Updated table Device clock specifications 3 02/2016 • Added new part numbers for 240 MHz and removed the 220 MHz and 200 MHz part numbers • Updated the document number to reflect change from 220 MHz to 240 MHz • Updated Voltage and current operating ratings • Updated Operating Requirements • Updated VLPS → RUN and STOP → RUN values in Power mode transition operating behaviors • In section Power consumption operating behaviors : • Added a note at the beginning of the table • Updated table to reflect 240 MHz values • Updated Typical device clock specifications • In section MCG specifications, updated the values listed under "PLL" 4 06/2016 • Updated PWM resolution in the introduction to 260 ps • Added table Enhanced NanoEdge PWM characteristics 72 NXP Semiconductors KV5x Data Sheet, Rev. 4, 06/2016 How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/SalesTermsandConditions. NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, Freescale, the Freescale logo, and Kinetis are trademarks of NXP B.V. All other product or service names are the property of their respective owners. ARM, the ARM powered logo, and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. ©2016 NXP B.V. Document Number KV5XP144M240 Revision 4, 06/2016