INTEGRATED CIRCUITS SSTL16857 14-bit SSTL_2 registered driver with differential clock inputs Product specification Supersedes data of 1999 Apr 29 1999 Sep 30 Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16857 FEATURES PIN CONFIGURATION • Stub-series terminated logic for 2.5V VDDQ (SSTL_2) • Optimized for DDR (Double Data Rate) SDRAM applications • Supports SSTL_2 signal inputs and outputs • Flow-through architecture optimizes PCB layout • Meets SSTL_2 class I and class II specifications • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000 V per MIL STD 833 Method 3015 and 200 V per Machine Model • Full DDR solution provided when used with PCK857 and CBT3857 DESCRIPTION The SSTL16857 is a 14-bit SSTL_2 registered driver with differential clock inputs. Both VCC and VDDQ support 2.5V and 3.3V operation however. VDDQ must not exceed VCC. Inputs are SSTL_2 type with VREF normally at 0.5*VDDQ. The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTL16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 100 MHz will have a burst rate of 200 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTL16857 is intended to be used for SSTL_2 input and output signals. The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. Q1 1 48 D1 Q2 2 47 D2 GND 3 46 GND VDDQ 4 45 VCC Q3 5 44 D3 Q4 6 43 D4 Q5 7 42 D5 GND 8 41 D6 VDDQ 9 40 D7 Q6 10 39 CLK– Q7 11 38 CLK+ VDDQ 12 37 VCC GND 13 36 GND Q8 14 35 VREF Q9 15 34 RESET VDDQ 16 33 D8 GND 17 32 D9 Q10 18 31 D10 Q11 19 30 D11 Q12 20 29 D12 VDDQ 21 28 VCC GND 22 27 GND Q13 23 26 D13 Q14 24 25 D14 SW00311 The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf v2.5 ns PARAMETER SYMBOL tPHL/tPLH CI CONDITIONS TYPICAL UNIT Propagation delay; CLK to Qn CL = 30 pF; VDDQ = 2.5 V 1.8 ns Input capacitance VCC = 2.5V 2.9 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi )ȍ (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; ȍ (CL VCC2 fo) = sum of the outputs. ORDERING INFORMATION PACKAGES 48-Pin Plastic TSSOP Type I 1999 Sep 30 TEMPERATURE RANGE ORDER CODE DWG NUMBER 0°C to +70°C SSTL16857 DGG SOT362-1 2 853-2155 22448 Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16857 PIN DESCRIPTION PIN NUMBER LOGIC DIAGRAM SYMBOL NAME AND FUNCTION RESET 34 48, 47, 44, 43, 42, 41, 40, 33, 32, 31, 30, 29, 26, 25 LVCMOS asynchronous master reset (Active LOW) RESET D1 – D14 VREF D1 REGISTER Q1 D2 REGISTER Q2 AD REGISTER Q3 REGISTER Q4 REGISTER Q5 REGISTER Q6 REGISTER Q7 REGISTER Q8 REGISTER Q9 REGISTER Q10 REGISTER Q11 REGISTER Q12 REGISTER Q13 REGISTER Q14 SSTL_2 data inputs 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 Q1 – Q14 35 VREF SSTL_2 input reference level 3, 8, 13, 17, 22, 27, 36, 46 GND Ground (0 V) 28, 37, 45 VCC Positive supply voltage 4, 9, 12, 16, 21 VDDQ Output supply voltage 38 39 CLK+ CLK– Differential clock inputs SSTL_2 data outputs D4 D5 D6 D7 D8 FUNCTION TABLE RESET CLK CLK D Q L X X X L H ↓ ↑ H H H ↓ ↑ L L L or H X Q0 H L or H H = High voltage level L = High voltage level ↓ = High-to-Low transition ↑ = Low-to-High transition X = Don’t care D9 OUTPUT INPUTS D10 D11 D12 D13 D14 CLK+ CLK– SW00312 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL PARAMETER VCC DC supply voltage IIK DC input diode current VI DC input voltage3 IOK DC output diode current VO < 0 VOUT DC output voltage3 Note 3 IOUT O CONDITION LIMITS UNIT MIN MAX –0.5 +4.6 V –50 mA –0.5 VDDQ + 0.5 V –50 mA VDDQ + 0.5 V VI < 0 –0.5 DC output current VO = 0 to VDDQ ±50 Continuous current4 VCC, VDDQ, or GND ±100 mA TSTG Storage temperature range –65 +150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4. The continuous current at VCC, VDDQ, or GND should not exceed ±100 mA. 1999 Sep 30 3 Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16857 RECOMMENDED OPERATING CONDITIONS1 PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VCC Supply voltage VDDQ 3.6 V VDDQ Output supply voltage 2.3 2.7 V VREF Reference voltage (VREF = 0.5 x VDDQ) 1.15 1.25 1.35 VTT Termination voltage VREF – 40mV VREF VREF + 40mV V VI Input voltage 0 VCC V VIH AC HIGH-level input voltage All inputs VIL AC LOW-level input voltage All inputs VIH DC HIGH-level input voltage All inputs All inputs VIL DC LOW-level input voltage IOH HIGH-level output current IOL LOW-level output current V VREF + 350mV V VREF – 350mV V VREF + 180mV VDDQ + 0.5V V VSS – 0.5V VREF – 180mV V –20 mA 20 mA 70 °C Tamb Operating free-air temperature range NOTE: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 0 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL VIK PARAMETER I/O supply voltage TEST CONDITIONS MIN TYP2 VCC – 0.2 2.3 VCC = 2.3V; IOH = –8mA 1.95 2.2 VCC = 2.3V; IOH = –16mA 1.95 2.1 VCC = 2.3V; II = –18mA VOL HIGH level output voltage LOW level output voltage 0.002 0.2 0.14 0.35 VCC = 2.3V; IOL = –16mA 0.30 0.35 CLK, CLK Common mode range for reliable performance 0.97 CLK, CLK Minimum peak-to-peak input to ensure logic state 360 VREF ICC Quiescent supply current CLK and CLK in opposite o osite state1 0.01 ±5 0.01 ±5 VCC = 3.6V ; VI = 2.7V or 0V 0.01 ±5 VCC = 2.7V ; VI = 1.7V or 0.8V 0.05 ±5 VCC = 2.7V ; VI = 2.7V or 0V 0.05 ±5 VCC = 2.7V ; VI = 2.7V or 0V VCC = 3.6V ; VI = 1.7V or 0.8V VREF = 1.15V 1 15V or 1.35V 1 35V VREF = 1.15V 1 15V or 1.35V 1 35V 0.05 ±5 VCC = 3.6V ; VI = 2.7V or 0V 0.05 ±5 VCC = 2.7V 0.05 ±5 0.05 ±5 VCC = 2.7V ; VI = 1.7V or 0.8V 12 25 VCC = 2.7V ; VI = 2.7V or 0V 10 25 VCC = 3.6V ; VI = 1.7V or 0.8V 12 25 VCC = 3.6V ; VI = 2.7V or 0V 10 25 VCC = 3.6V ; VI = 1.7V or 0.8V 1 15V or 1.35V 1 35V VREF = 1.15V VCC = 3.6V 4 V V mV ±5 NOTES: 1. When CLK and CLK are HIGH, typical ICC = 25mA. 2. All typical values are at VCC = 3.3V and Tamb = 25°C (unless otherwise specified). 1999 Sep 30 1.53 0.01 VCC = 2.7V ; VI = 1.7V or 0.8V CLK CLK CLK, V VCC = 2.3V; IOL = –8mA VPP II MAX VCC = 2.3V to 2.7V; IOL = –100µA VCMR Data inputs inputs, RESET UNIT –1.2 VCC = 2.3V to 2.7V; IOH = –100µA VOH Temp = 0°C to +70°C µA µA mA µA mA Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16857 TIMING REQUIREMENTS Over recommended operating conditions; Tamb = 0_C to +70_C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL PARAMETER VCC = 2.5V ±0.2V TEST CONDITIONS MIN fclock Clock frequency MAX VCC = 3.3V ±0.3V MIN 200 tw Pulse duration, CLK, CLK HIGH or LOW tsu Setup time th Hold time MAX 200 1.0 1.0 Data before CLK↑, CLK↓ 0.8 0.9 RESET HIGH before CLK↑, CLK↓ 0.8 1.0 0.5 0.5 UNIT MHz ns ns ns SWITCHING CHARACTERISTICS Over recommended operating conditions; Tamb = 0_C to +70_C; VDDQ = 2.3 – 2.7V and VDDQ does not exceed VCC. Class I, VREF = VTT = VDDQ x 0.5 and CL = 10pF (unless otherwise noted) (see Figure 1) FROM (INPUT) SYMBOL TO (OUTPUT) LIMITS LIMITS VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V MIN fmax tPLH/tPHL tPHL Maximum clock frequency MAX 200 MIN 200 MHz CLK and CLK Q 1.0 3.1 0.7 2.6 ns RESET Q 2.0 5.0 1.4 4.0 ns SDRAM SDRAM SDRAM SDRAM CBT CBT CBT CBT CBT SDRAM SDRAM SDRAM SDRAM CBT SDRAM SDRAM SDRAM SDRAM CBT SDRAM SDRAM CBT SDRAM SDRAM SDRAM CBT SDRAM 184/200-pin DDR SDRAM DIMM BACK SIDE CBT3857 (9) FRONT SIDE SSTL16857 SSTL16857 PCK857 The PLL clock distribution device and SSTL registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation SW00393 1999 Sep 30 UNIT MAX 5 Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16857 PARAMETER MEASUREMENT INFORMATION AC WAVEFORMS VIH CLK VREF tW VIH VREF INPUT VREF VIL tPLH VREF tPHL VIL VOH OUTPUT VREF SW00339 VREF Waveform 3. Pulse duration VOL SW00338 Waveform 1. Propagation delay times inverting and non-inverting outputs VIH TIMING INPUT VREF VIL RESET VIH tsu VREF th VIH VIL DATA INPUT tPHL VREF VREF VOH OUTPUT VIL VREF VOL SW00340 SW00402 Waveform 2. Propagation delay RESET to output. Waveform 4. Setup and hold times TEST CIRCUIT VTT TEST POINT 25Ω 50pF 500 Ω 25Ω = SSTL_2 Class II 50Ω = SSTL_2 Class I SW00336 CL = 10pF or 30pF Figure 2. NOTES: CL includes probe and jig capacitance All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr ≤ 1.25ns/V, tf 1.25ns/V. The outputs are measured one at a time with one transition per measurement. VTT = VREF = VDDQ x 0.5 50pF SW00335 Figure 3. SW00337 Figure 1. Load circuitry 1999 Sep 30 6 Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16857 TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm 1999 Sep 30 7 SOT362-1 Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16857 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 09–99 Document order number: 1999 Sep 30 8 9397–750–06455