Brief CBTV24DD12

CBTV24DD12
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2
applications
Rev. 1 — 28 August 2014
Product brief
1. General description
CBTV24DD12 is designed for 1.8 V/2.5 V/3.3 V supply voltage operation and it supports
Pseudo Open Drain (POD), SSTL_12, SSTL_15 or SSTL_18 signaling and CMOS select
input levels. This device is designed for operation in DDR4, DDR3 or DDR2 memory bus
systems, with speeds up to 3200 MT/s.
The CBTV24DD12 has a 1 : 2 switch or 2 : 1 multiplex topology and offers a 12-bit wide
bus. Each 12-bit wide A-port can be switched to one of two ports B and C, for all bits
simultaneously. Each port is non-directional due to the use of FET switches, allowing a
multitude of applications requiring high-bandwidth switching or multiplexing.
The selection of the port is by a simple CMOS input (SELect). Another CMOS input
(ENable) is available to allow all ports to be disconnected. The SEL0, SEL1 and EN input
signals are designed to operate transparently as CMOS input level signals up to 3.3 V.
CBTV24DD12 uses NXP’s proprietary high-speed switch architecture providing high
bandwidth, very little insertion loss, return loss, and very low propagation delay, allowing
use in many applications requiring switching or multiplexing of high-speed signals. It is
available in a 3.0 mm  8.0 mm TFBGA48 package with 0.65 mm ball pitch, for optimal
size versus board layout density considerations. It is characterized for operation from
10 C to +85 C.
2. Features and benefits
2.1 Topology





12-bit bus width
1 : 2 switch/MUX topology
Bidirectional operation
Simple CMOS select pins (SEL0, SEL1)
Simple CMOS enable pin (EN)
2.2 Performance






3200 MT/s throughput
7.4 GHz bandwidth (for both single-ended and differential signals)
Low ON insertion loss
Low return loss
Low crosstalk
High OFF isolation
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
 POD_12, SSTL_12, SSTL_15 or SSTL_18 signaling
 Low RON (8  typical)
 Low RON (<1 )
2.3 General attributes




1.8 V/2.5 V/3.3 V supply voltage operation
Very low supply current (600 A typical)
ESD robustness exceeds 2.5 kV HBM, 1 kV CDM
Available in TFBGA48 package, 3.0 mm  8.0 mm  1 mm size, 0.65 mm pitch,
Pb-free/Dark Green
3. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
CBTV24DD12ET
V2412
TFBGA48
plastic low profile fine-pitch ball grid array package; 48
balls; body 3  8  1 mm; 0.65 mm pitch
SOT1365-1
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum Temperature
order
quantity
CBTV24DD12ET
CBTV24DD12ETY
TFBGA48
Reel 13” Q1/T1
*Standard mark SMD dry pack
4500
Tamb = 10 C to +85 C
4. Functional diagram
VDD
SEL[0:1]
EN
B[0:11]
host side B
CBTV24DD12
12-bit
2 : 1 MUX/switch
A[0:11]
DRAM side
C[0:11]
host side C
GND
002aah463
Fig 1.
Brief_CBTV24DD12
Product brief
Functional diagram
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 August 2014
© NXP B.V. 2014. All rights reserved.
2 of 3
CBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
5. Package outline
SOT1365-1
TFBGA48: plastic low profile fine-pitch ball grid array package; 48 balls
A
B
D
ball A1
index area
E
A2
A
A1
detail X
e1
C A B
C
Øv
Øw
b
e
C
y
y1 C
1/2 e
M
L
K
J
e
H
G
e2
F
E
1/2 e
D
C
B
A
1 2 3 4
ball A1
index area
X
0
5 mm
scale
Dimensions
Unit
mm
A
A1
A2
b
max 1.05 0.35 0.73 0.45
nom 0.98 0.30 0.68 0.40
min 0.88 0.25 0.63 0.35
D
E
3.1
3.0
2.9
8.1
8.0
7.9
e
e1
e2
v
w
y
0.65 1.95 7.15 0.15 0.05 0.08
y1
0.1
sot1365-1_po
Fig 2.
References
Outline
version
IEC
JEDEC
JEITA
SOT1365-1
---
---
---
European
projection
Issue date
14-01-03
14-08-12
Package outline TFBGA48 (SOT1365-1)
© NXP N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 August 2014
Document identifier: Brief_CBTV24DD12
Brief_CBTV24DD12
Product brief
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 August 2014
© NXP B.V. 2014. All rights reserved.
3 of 3