NXP Fast-mode Plus parallel bus to I2C-bus controller PCA9665 1-MHz I2C-bus control on longer buses This is the first master device to be compatible with Fast-mode Plus, so it offers ten times the speed or ten times the capacitance as standard Fast-mode masters. It can communicate at I2Cbus speeds up to 1 MHz and on buses up to 4,000 pF. Key features 4 Converts parallel-bus to I2C-bus protocol 4 Master and slave functions 4 Multi-master capability 4 Capable of 1 Mbps and 30-mA SCL/ SDA 4 68-byte data buffer option 4 I2C-bus General Call option 4 Software reset capability on parallel bus Applications 4 Adding one or many I2C-bus ports to a microcontroller or a microprocessor 4 Reducing the number of traces on the PCB 4 Increasing I2C-bus throughput 4 Putting more I2C devices on the bus 4 Off-loading I2C-bus processing The NXP PCA9665 allows the 8-bit parallel bus system of a microcontroller or microprocessor to communicate bidirectionally with the I2C-bus. The device has a 68-byte buffer and is an upgraded version of the PCA9564, making it capable of higher speeds and able to drive bigger I2C-buses. There are two operating modes – byte and multiple-byte. In byte mode, the PCA9665 is comparable to the PCA9564 and performs parallel-to-serial and serial-to-parallel conversions one byte at a time. In multiple-byte (buffered) mode, the PCA9665 can send or receive up to 68 bytes at once. This significantly decreases the number of interrupts handled by the processor, so the processor can handle other tasks while the PCA9665 interacts with the I2C-bus. In both operating modes, feedback on the task and operation execution is performed through the active low interrupt output (INT) or by polling the PCA9665 status register. All the tasks related to the I2C-bus, including protocol, arbitration, bus errors, and timing, are handled without requiring an external timing element. The PCA9665 supports I2C General Call capability, and can be configured to respond to the General Call command if the application requires it. A Software Reset scheme on the parallel bus lets resets take place without the use of an additional pin, and an internal oscillator reduces the number of external components. The device can operate in Standard, Fast-mode and Fast-mode Plus, and is compatible with the SMBus protocol. The operating supply voltage is 2.3 to 3.6 V and all the I/O are tolerant to 5 V. The I2C-bus clock frequency is 0 to 1 MHz, and the SDA and SCL outputs are capable of driving 30 mA. The operating temperature is -40 to +85 °C. data D7 SDA PCA9665 D6 D5 D3 D2 D1 D0 SD5 SD4 SD3 SD2 I2CDAT – Data Register – read/write SD1 SD0 – – – IP2 IP1 INDPTR – Indirect Address Pointer – write only BUS BUFFER FILTER 68-BYTE BUFFER SDA CONTROL D4 DIRECT REGISTERS SD7 SD6 – – ST7 ST6 ST5 ST4 ST3 ST2 I2CSTA – Status Register – read only AA ENSIO STA STO SI – I2CCON – Control Register – read/write BIT7 BIT6 A1 A0 0 1 IP0 0 0 ST1 ST0 0 0 – MODE 1 1 1 0 AA ENSIO STA STO SI SCL FILTER SCL CONTROL BIT5 BIT4 BIT3 BIT2 BIT1 INDIRECT – Indirect Register Access – read/write BIT0 ENSIO STA STO SI INDIRECT REGISTERS ESD protection exceeds 2,000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1,000 V CDM per JESD22-C101. Latch-up testing, performed in accordance with JEDEC Standard JESD78, exceeds 100 mA. For more information visit www.nxp.com/i2clogic LB BC6 BC5 BC4 BC3 BC2 I2CCOUNT – Byte Count – read/write BC1 BC0 AD7 AD6 AD5 AD4 AD3 AD2 I2CADR – Own Address – read/write AD1 GC BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 I2CSCLL – SCL LOW Period – read/write BIT1 BIT0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 I2CSCLH – SCL HIGH Period – read/write BIT1 BIT0 TE BIT6 BIT5 BIT4 BIT3 BIT2 I2CTO – TIMEOUT Register – read/write BIT1 BIT0 IR7 IR6 IR5 IR4 IR3 IR2 IR1 I2CPRESET – Software Reset Register – write only IR0 – – – – – SSREN AC1 I2CMODE – I2C Mode Register – read/write AC0 CLOCK SELECTOR 01h 02h 03h CE WR RD INT 04h 05h 06h CONTROL BLOCK INTERRUPT CONTROL OSCILLATOR INDPTR 00h RESET A1 POWER-ON RESET A0 VDD control signals PCA9665 block diagram Comparison of PCF8584, PCA9564, and PCA9665 I2C-bus controllers Characteristics PCF8584 PCA9564 PCA9665 Voltage range 4.5 – 5.5 V 2.3 – 3.6 V I/O tolerant to 5.5 V 2.3 – 3.6 V I/O tolerant to 5.5 V Maximum I2C-bus frequency 90 kHz (1) 360 kHz (2) 1 MHz (2) Maximum capacitive load 400 pF 400 pF 4,000 pF Buffered mode 68 bytes I C General Call Yes 2 Software reset Notes: (1) External clock source Parallel bus (2) Internal clock source requiring no external components Ordering information Package Tube DIP 20 PCA9665N,112 SO 20 PCA9665D,112 PCA9665D,118 TSSOP 20 PCA9665PW,112 PCA9665PW,118 HVQFN 20 Tape and Reel PCA9665BS,118 www.nxp.com © 2006 NXP N.V. All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The Date of release: October 2006 information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and Document order number: 9397 750 15687 may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof Printed in the USA does not convey nor imply any license under patent- or other industrial or intellectual property rights.