Example MPC8540-Based CompactPCI Reference Design

Freescale Semiconductor
MPC8540cPCIWP
Rev. 1, 11/2004
White Paper
An Example MPC8540-Based
CompactPCI Reference Design
by
NCSD Applications
Freescale Semiconductor, Inc.
East Kilbride, Scotland
CompactPCI™ is a very high performance industrial bus based on
the standard PCI electrical specification in a rugged 3U or 6U
Eurocard packaging.Compared to standard desktop PCI,
CompactPCI supports twice as many PCI slots (8 versus 4) and
offers a packaging scheme that is much better suited for use in
industrial applications.Due to its extremely high bandwidth, the
CompactPCI bus is particularly well suited for many high speed
data communication applications such as servers, routers,
converters and switches. Full CompactPCI specifications are
available from the PCI Industrial Computer Manufacturers Group
at www.picmg.org.
This White Paper describes an example design of a compact PCI
reference system based on the latest MPC8540 integrated
PowerPC™ processor.
1
Introduction
The MPC8540 is a member of the latest PowerPC processor based
family of integrated devices. It is based on a 32-bit
implementation of the “new” Book E Embedded PowerPC
processor core. This core is known as the e500 core and supports
the features detailed in the PowerPC Book E architecture
definition.
This core has several features that differ from other PowerPC
cores which are known as “Classic PowerPC.” Details of the
differences are described in a separate Application Note.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
1.
2.
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Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Example Reference CompactPCI Design . . . . . . . . . . 3
Block Diagram of Example Reference Design . . . . . . 4
Example Interface Schematics . . . . . . . . . . . . . . . . . . 6
Document Revision History . . . . . . . . . . . . . . . . . . . 28
Introduction
The key features of the MPC8540 are described in the MPC8540 User’s Manual and therefore will not be repeated
here.
The device consists of the following components in a 783-ball FC-PBGA package
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Embedded e500 Book E-compatible core
256 Kbytes of on-chip memory
DDR memory controller
Local Bus Controller
2 x Three-speed (10/100/1000) Ethernet controllers (TSEC)
RapidIO interface unit
PCI/PCI-X functional unit
Integrated DMA controller
Programmable Interrupt Controller (PIC)
DUART
I2C Controller
Boot sequencer
Address translation and mapping unit (ATMU)
System performance monitor
System access port
Power management
IEEE 1149.1-compliant, JTAG boundary scan
A block diagram of the main functional units within the MPC8540 is shown in Figure 1.
CompactPCI Reference Design, Rev. 1
2
Freescale Semiconductor
Example Reference CompactPCI Design
Figure 1. MPC8540 Functional Block Diagram
2
Example Reference CompactPCI Design
This example reference design utilises the on chip PCI Controller in the MPC8540 to interface to the CompactPCI
bus. It contains a block of DDR SDRAM memory which is controlled directly by the device and a small amount of
Flash memory used to hold power on reset boot code.
One of the TSEC ethernet interfaces is brought out to a standard RJ-45 socket via a Gb Ethernet PHY device and
associated interface logic. Separate debug interface ports are provided via the on-chip DUART interface.
The RapidIO Trade Association have defined a standard interface connector for a parallel RapidIO interface. This
forms part of the specification for a Hardware Implementation Platform (HIP) which allows standard PCI to
RapidIO inter operability. This HIP platform is not defined for CompactPCI systems. For reference purposes the
schematics for this example design show this standard RapidIO connector as an optional extra connector.
Full details are available at www.rapidio.org.
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
3
Block Diagram of Example Reference Design
3
Block Diagram of Example Reference Design
A block diagram of the example system is shown in Figure 2.
Power Supply
DDR SDRAM
128MBytes
Gb Ethernet
PHY etc
DUART
RS232 Interface
MPC8540
Boot FLASH
8MBytes
CompactPCI
Connector
Optional RapidIO
Connector
Clocking,Configuration
and Reset Logic
Figure 2. Block Diagram of Reference Design
3.1
MPC8540
The MPC8540 is the processing element of this design. It contains a 32-bit embedded PowerPC processor core and
interfaces to each of the other blocks of this example reference design.
3.2
DDR SDRAM
The main memory array is built from 5 x MT46V16M16 DDR SDRAM devices. These are configured to provide
128MBytes of 64-bit wide memory along with one parity bit for each memory byte. The control of the DDR memory
system is handled by the DDR memory controller implemented within the MPC8540 device.
3.3
Boot Flash
The boot Flash is implemented by a single 8MByte AMD29L_V641D device configured to be 16-bits wide. Since
the local bus of the MPC8540 is a multiplexed address and data bus, an external latch using 74LVT16373 devices
is implemented and controlled by the Local Address Latch Enable (LALE) signal from the MPC8540.
CompactPCI Reference Design, Rev. 1
4
Freescale Semiconductor
Block Diagram of Example Reference Design
3.4
Compact PCI Connectors
The MPC8540 device contains an on-chip PCI/PCI-X interface which handles all the defined protocol for these
buses. The PCI bus is brought out to two separate edge connectors on the board which conform to the Compact PCI
interface specification. These are the connectors defined as J1 and J2 in the CompactPCI specification. Note the
MPC8540 only supports 3.3V I/O. If a 5V interface is to be supported then level shifting logic will be required
between the MPC8540 and the connectors.
3.5
Gb Ethernet PHY
The MPC8540 contains a two separate triple speed ethernet controllers which support speeds of 10Mbps, 100Mbps
and 1Gbps. One of these controllers is brought out to an RJ45 edge connector via a Marvell 88E1011Gb Ethernet
physical transceiver device
3.6
DUART
The MPC8540 also contains a dual UART interface that supports simple serial interfaces. These channels are
brought out to 9-way D type RS232 connectors. These ports would be typically be used for debug and maintenance
work
3.7
Clocking, Configuration and Reset Logic
The MPC8540 uses the input 66MHz PCI clock as a reference and makes use of on-chip PLLs to multiply this clock
frequency to drive the memory interface bus and processor core. A diagram of the clock structure is shown in
Figure 3.
Figure 3. Clock sub-system Block Diagram
Many of the features of the MPC8540 are configured by sampling a series of pins during reset. In this reference
design the configuration pins are all implemented as a series of small DIP switches that are configured by hand
before the device is reset. For a design where the final configuration is known at the design stage then these DIP
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
5
Example Interface Schematics
switches can be omitted and replaced by pull-up or pull-down resistors to achieve the desired value on the
configuration pins.
3.8
Power Supply
Assuming this board will be supplied with +5V and +3.3V from the CompactPCI backplane then all the other
voltages required on the board are generated by the various power convertor circuits on the card. This includes 2.5V
for the DDR memory and Ethernet PHY. The 1.2V cpu core voltage and the 1.5V for the Ethernet PHY. The 1.25V
reference voltage for the DDR memory is produced by the LP2995 DDR voltage regulator device.
4
Example Interface Schematics
A full set of interface schematics are shown below. These were created using OrCad version 9.2 available from
Cadence Design Systems™. The schematics are laid out in a hierarchical sequence of sheets.
The following pages give a full set of example schematics for an MPC8540 Compact PCI Reference design. They
also include an optional RapidIO connector.
The schematics are laid out in a hierarchical fashion as follows:
Table 1. Top Level System Interconnection
Figure 4
Top Level System Interconnection
Figure 5
Top Level view of MPC8540 and memory systems
Figure 6
DDR SDRAM Memory Array
Figure 7
MPC8540 Top Level
Figure 8
Boot FLASH Memory
Figure 9
MPC8540 CPU and Local Bus Interface
Figure 10
MPC8540 DDR SDRAM Interface
Figure 11
DDR SDRAM Termination
Figure 12
MPC8540 Gb Ethernet Interface
Figure 13
MPC8540 RapidIO Interface
Figure 14
MPC8540 Power on Configuration Logic
Figure 15
MPC8540 PCI/PCI-X Interface
Figure 16
MPC8540 Parallel I/O and DUART Interface
Figure 17
MPC8540 Power Connections
Figure 18
Compact PCI J1 and J2 Connectors
Figure 19
Clock and Reset Logic
Figure 20
Local Power Supply Logic
Figure 21
Gb Ethernet Transceiver
Figure 22
RS232 Interface Logic
Figure 23
Optional RapidIO Connector
Figure 24
MPC8540 COP Debug Connector
CompactPCI Reference Design, Rev. 1
6
Freescale Semiconductor
P17_Power_Supply
P18/19_Ethernet_+_RS232
Ethernet+RS232
SIN1
SOUT1
SIN0
SOUT0
MDC
MDIO
GTX_CLK125
ETHERA[0:24]
P16_Clocks_+_Reset
Clocks+Reset
ETHERA[0:24]
SYSCLKA
P02_Top_Level_View
SIN1
SOUT1
SIN0
SOUT0
MDC
MDIO
GTX_CLK125
ETHERA[0:24]
Top_Level
RIO[0:39]
RIO[0:39]
RIO[0:39]
P20_RapidIO_Connector
P21_Debug_Connector
Debug
PCI[0:86]
DEBUG[0:8]
RapidIO_Connector
DEBUG[0:8]
Freescale Semiconductor
DEBUG[0:8]
Power_Supply
PCI[0:86]
P15_PCI_Connectors
PCI[0:86]
PCI_Connectors
Example Interface Schematics
Figure 4. Top Level System Interconnection
CompactPCI Reference Design, Rev. 1
7
SYSCLK
SYS_HRESET*
SYS_HRESET*
SYS_HRESET*
8
LWR*
LWR*
SCL
SCL
SOUT0
SIN1
SOUT1
SIN1
SOUT1
P04_MPC8540_Top_level
SIN0
PCI[0:86]
PCI[0:86]
SIN0
RIO[0:39]
SOUT0
SYSCLK
SYSCLK
MDC
RIO[0:39]
MDIO
MDC
GTX_CLK125
ETHERA[0:24]
SDA
SDA
LBOE*
LALE
LBOE*
LCS0*
LAD[0:31]
MPC8540
LALE
LAD[0:31]
LCS0*
LAD[0:31]
MDIO
GTX_CLK125
ETHERA[0:24]
P05_Boot_Flash
HRESET*
Boot_Flash
CKSTP_IN*
CKSTP_OUT*
HRESET*
SRESET*
TCK
TDI
TDO
TMS
TRST
MCK*
MCK
MCKE
MWE*
RAS*
CAS*
MCS0*
MA[0:12]
MBA[0:1]
MDQ[0:63]
MDM[0:8]
MDQS[0:8]
MECC[0:7]
DEBUG5
DEBUG6
DEBUG7
DEBUG8
HRESET*
SRESET*
CKSTP_IN*
CKSTP_OUT*
DEBUG0
DEBUG1
DEBUG2
DEBUG3
DEBUG4
TCK
TDI
TDO
TMS
TRST
MA[0:12]
MBA[0:1]
MDQ[0:63]
MDM[0:8]
MDQS[0:8]
MECC[0:7]
SYS_HRESET*
P03_Memory_System
MCK*
MCK
MCKE
MWE*
RAS*
CAS*
MCS0*
MA[0:12]
MBA[0:1]
MDQ[0:63]
MDM[0:8]
MDQS[0:8]
MECC[0:7]
Memory_Block
DEBUG[0:8]
Example Interface Schematics
Figure 5. Top Level view of MPC8540 and memory systems
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
MCKE
MCK*
MCK
MBA[0:1]
MA[0:12]
MDQ[0:63]
Freescale Semiconductor
MCLKS2
MCK*
MCKE
MCS0*
MWE*
CAS*
RAS*
MDQS[0:8]
MDM[0:8]
MCLKS0
MCLKS1
MCK
MCONTROL0
MCONTROL1
MCONTROL2
MCONTROL3
RAS*
CAS*
MWE*
MCS0*
MDQS[0:8]
MDM[0:8]
MCLKS[0:2]
26
27
MBA0
MBA1
MCONTROL[0:3]
+2.5V
+2.5V
MDM1
MDM0
MDQS1
MDQS0
RAS*
CAS*
MWE*
MCS0*
1
18
33
3
9
15
55
61
47
20
51
16
23
22
21
24
MCK 45
MCK* 46
MCKE 44
29
30
31
32
35
36
37
38
39
40
28
41
42
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREF
NC
NC
NC
NC
NC
DNU
DNU
34
48
66
64
58
52
12
6
49
14
17
25
43
53
19
50
2
4
5
7
8
10
11
13
54
56
57
59
60
62
63
65
MT46V16M16_TSOP66
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
UDM
LDM
UDQS
LDQS
RAS
CAS
WE
CS
CLK
CLK
CKE
A0
DQ0
DQ1
A1
DQ2
A2
DQ3
A3
DQ4
A4
DQ5
A5
DQ6
A6
DQ7
A7
DQ8
A8
DQ9
A9
A10/AP DQ10
DQ11
A11
DQ12
A12
DQ13
BA0
DQ14
BA1
DQ15
U1
VREF_+1.25V
MDQ0
MDQ1
MDQ2
MDQ3
MDQ4
MDQ5
MDQ6
MDQ7
MDQ8
MDQ9
MDQ10
MDQ11
MDQ12
MDQ13
MDQ14
MDQ15
26
27
MBA0
MBA1
MDQS8
+2.5V
+2.5V
RAS*
CAS*
MWE*
MCS0*
1
18
33
3
9
15
55
61
47
20
51
16
23
22
21
24
MCK 45
MCK* 46
MCKE 44
29
30
31
32
35
36
37
38
39
40
28
41
42
+2.5V
1
18
33
3
9
15
55
61
47
20
51
16
23
22
21
24
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREF
NC
NC
NC
NC
NC
DNU
DNU
34
48
66
64
58
52
12
6
49
14
17
25
43
53
19
50
2
4
5
7
8
10
11
13
54
56
57
59
60
62
63
65
MT46V16M16_TSOP66
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
UDM
LDM
UDQS
LDQS
RAS
CAS
WE
CS
CLK
CLK
CKE
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREF
NC
NC
NC
NC
NC
DNU
DNU
34
48
66
64
58
52
12
6
49
14
17
25
43
53
19
50
2
4
5
7
8
10
11
13
54
56
57
59
60
62
63
65
VREF_+1.25V
VREF_+1.25V
MDQ16
MDQ17
MDQ18
MDQ19
MDQ20
MDQ21
MDQ22
MDQ23
MDQ24
MDQ25
MDQ26
MDQ27
MDQ28
MDQ29
MDQ30
MDQ31
VREF_+1.25V
MECC0
MECC1
MECC2
MECC3
MECC4
MECC5
MECC6
MECC7
MECC0
MECC1
MECC2
MECC3
MECC4
MECC5
MECC6
MECC7
MT46V16M16_TSOP66
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
UDM
LDM
UDQS
LDQS
RAS
CAS
WE
CS
CLK
CLK
CKE
A0
DQ0
DQ1
A1
DQ2
A2
DQ3
A3
DQ4
A4
DQ5
A5
DQ6
A6
DQ7
A7
DQ8
A8
DQ9
A9
A10/AP DQ10
DQ11
A11
DQ12
A12
DQ13
BA0
DQ14
BA1
DQ15
U2
A0
DQ0
DQ1
A1
DQ2
A2
DQ3
A3
DQ4
A4
DQ5
A5
DQ6
A6
DQ7
A7
DQ8
A8
DQ9
A9
A10/AP DQ10
A11
DQ11
A12
DQ12
DQ13
BA0
DQ14
BA1
DQ15
U5
+2.5V
MDM3
MDM2
MDQS3
MDQS2
RAS*
CAS*
MWE*
MCS0*
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MDM8
26
27
MBA0
MBA1
MCK 45
MCK* 46
MCKE 44
29
30
31
32
35
36
37
38
39
40
28
41
42
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
+
4
3
2
1
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
UDM
LDM
UDQS
LDQS
RAS
CAS
WE
CS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREF
NC
NC
NC
NC
NC
DNU
DNU
34
48
66
64
58
52
12
6
49
14
17
25
43
53
19
50
2
4
5
7
8
10
11
13
54
56
57
59
60
62
63
65
LP2995
VREF
VSENSE
VDDQ
AVIN
PVIN
VTT
LP2995
MECC[0:7]
5
6
7
8
MT46V16M16_TSOP66
GND
NC
U6
1
18
33
3
9
15
55
61
47
20
51
16
23
22
21
24
CLK
CLK
CKE
A0
DQ0
DQ1
A1
DQ2
A2
DQ3
A3
DQ4
A4
DQ5
A5
DQ6
A6
DQ7
A7
DQ8
A8
DQ9
A9
A10/AP DQ10
DQ11
A11
DQ12
A12
DQ13
BA0
DQ14
BA1
DQ15
U3
+
C18
50uF
+2.5V
VREF_+1.25V
MDQ32
MDQ33
MDQ34
MDQ35
MDQ36
MDQ37
MDQ38
MDQ39
MDQ40
MDQ41
MDQ42
MDQ43
MDQ44
MDQ45
MDQ46
MDQ47
DDR Memory Termination Regulator
C17
0.1uF
+2.5V
MDM5
MDM4
MDQS5
MDQS4
RAS*
CAS*
MWE*
MCS0*
+2.5V
26
27
29
30
31
32
35
36
37
38
39
40
28
41
42
MCK 45
MCK* 46
MCKE 44
MBA0
MBA1
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
+2.5V
MDM7
MDM6
MDQS7
MDQS6
RAS*
CAS*
MWE*
MCS0*
+
C16
220uF
VTT_+1.25V
+2.5V
+2.5V
26
27
29
30
31
32
35
36
37
38
39
40
28
41
42
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREF
NC
NC
NC
NC
NC
DNU
DNU
34
48
66
64
58
52
12
6
49
14
17
25
43
53
19
50
2
4
5
7
8
10
11
13
54
56
57
59
60
62
63
65
C7
0.1uF
C12
0.1uF
C6
0.1uF
C11
0.1uF
C2
0.1uF
C13
0.1uF
C8
0.1uF
C14
0.1uF
C9
0.1uF
C4
0.1uF
VREF_+1.25V
MDQ48
MDQ49
MDQ50
MDQ51
MDQ52
MDQ53
MDQ54
MDQ55
MDQ56
MDQ57
MDQ58
MDQ59
MDQ60
MDQ61
MDQ62
MDQ63
C3
0.1uF
MT46V16M16_TSOP66
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
UDM
LDM
UDQS
LDQS
RAS
CAS
WE
CS
CLK
CLK
CKE
A0
DQ0
DQ1
A1
DQ2
A2
DQ3
A3
DQ4
A4
DQ5
A5
DQ6
A6
DQ7
A7
DQ8
A8
DQ9
A9
A10/AP DQ10
DQ11
A11
DQ12
A12
DQ13
BA0
DQ14
BA1
DQ15
U4
C1
0.1uF
1
18
33
3
9
15
55
61
47
20
51
16
23
22
21
24
MCK 45
MCK* 46
MCKE 44
MBA0
MBA1
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
C15
0.1uF
C10
0.1uF
C5
0.1uF
Example Interface Schematics
Figure 6. DDR SDRAM Memory Array
CompactPCI Reference Design, Rev. 1
9
10
SOUT1
SIN1
SOUT0
SIN0
GTX_CLK125
ETHERA[0:24]
RIO[0:39]
CFG[1:32]
P13_MPC8540_CPM_Interface
SOUT1
SIN1
SOUT0
SIN0
MPC8560_CPM_Interface
P09_MPC8540_Comms_Interface
GTX_CLK125
ETHERA[0:24]
MPC8540_Comms_Interface
P10_ MPC8540_RapidIO_Interface
RIO[0:39]
MPC8540_RapidIO_Interface
SCL
MDC
MDIO
SCL
MDC
MDIO
TDO
TDO
CFG[1:32]
CFG[1:32]
P11_MPC8540_Configuration_logic
CFG[1:32]
HRESET
TCK
TDI
TMS
TRST
TCK
TDI
TMS
TRST
CKSTP_OUT*
CKSTP_IN*
LBOE*
CKSTP_IN*
LWR*
LWR*
LALE
LCS0*
LAD[0:31]
P07/08_MPC8540_DDR_Mem_I/F
LBOE*
LALE
LCS0*
LAD[0:31]
CKSTP_OUT*
MPC8540_CONFIG
P06_MPC8540_CPU
SDA
HRESET*
SRESET*
SYSCLK
SDA
HRESET*
SRESET*
SYSCLK
MPC8540_CPU
MPC8540 _Memory Interface
PCI[0:86]
MCKE
P14_MPC8540_Power
MPC8540_Power
P12_MPC8540_PCI_Interface
SYSCLK
CFG[1:32]
MCK*
MCKE
PCI[0:86]
MCK
MCK*
MPC8540_PCI/PCIX_Interface
MCS0*
MCK
MBA[0:1]
MCS0*
MA[0:12]
RAS*
MBA[0:1]
CAS*
MA[0:12]
MWE*
MDM[0:8]
RAS*
MDQS[0:8]
CAS*
MECC[0:7]
MDM[0:8]
MWE*
MDQ[0:63]
MDQ[0:63]
MECC[0:7]
MDQS[0:8]
Example Interface Schematics
Figure 7. MPC8540 Top Level
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
Freescale Semiconductor
LALE
LAD[0:31]
+3.3V
36
35
33
32
30
29
27
26
LAD24
LAD25
LAD26
LAD27
LAD28
LAD29
LAD30
LAD31
7
18
31
42
1
24
48
25
47
46
44
43
41
40
38
37
LAD16
LAD17
LAD18
LAD19
LAD20
LAD21
LAD22
LAD23
+3.3V
7
18
31
42
1
24
48
25
36
35
33
32
30
29
27
26
LAD8
LAD9
LAD10
LAD11
LAD12
LAD13
LAD14
LAD15
4
47
46
44
43
41
40
38
37
C19
0.1uF
8
LAD0
LAD1
LAD2
LAD3
LAD4
LAD5
LAD6
LAD7
+3.3V
+3.3V
A2
A1
A0
SDA
SCL
WP
74LVT16373/SO
VCC
VCC
VCC
VCC
1OE
2OE
1LE
2LE
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
U10
74LVT16373/SO
VCC
VCC
VCC
VCC
1OE
2OE
1LE
2LE
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
U8
EEPROM
GND
VCC
U7
3
2
1
5
6
7
GND
GND
GND
GND
GND
GND
GND
GND
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
GND
GND
GND
GND
GND
GND
GND
GND
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
4
10
15
21
28
34
39
45
13
14
16
17
19
20
22
23
2
3
5
6
8
9
11
12
4
10
15
21
28
34
39
45
13
14
16
17
19
20
22
23
2
3
5
6
8
9
11
12
R1
10K
R3
4K7
+3.3V
R2
10K
R4
4K7
LA24
LA25
LA26
LA27
LA28
LA29
LA30
LA16
LA17
LA18
LA19
LA20
LA21
LA22
LA23
LA9
LA10
LA11
LA12
LA13
LA14
LA15
R5
4K7
SDA
SCL
LA[9:30]
HRESET*
LWR*
LCS0*
LBOE*
R6
10K
+3.3V
R7
10K
LAD15
LAD14
LAD13
LAD12
LAD11
LAD10
LAD9
LAD8
LAD7
LAD6
LAD5
LAD4
LAD3
LAD2
LAD1
LAD0
37
13
14
12
28
26
11
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
U9
AM29LV641D
VCC
ACC
WP
RESET
OE
CE
WE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VIO
VSS
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
47
27
46
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
15
10
9
+3.3V
LA30
LA29
LA28
LA27
LA26
LA25
LA24
LA23
LA22
LA21
LA20
LA19
LA18
LA17
LA16
LA15
LA14
LA13
LA12
LA11
LA10
LA9
Example Interface Schematics
Figure 8. Boot FLASH Memory
CompactPCI Reference Design, Rev. 1
11
4M x 16 FLASH
HRESET*
RED
D2
R36
160R
+3.3V
CKSTP_OUT*
R32
10K
+3.3V
RED
D1
R33
160R
+3.3V
R37
10K
+3.3V
CKSTP_IN*
MDC
MDIO
CFG27
CFG28
CFG15
R35
10K
+3.3V
CPU Boot Configuration
CPU Boot Sequence bit 0
CPU Boot Sequence bit 1
TSEC Width
RIO Tx CLK Source bit 0
RIO Tx CLK Source bit 1
Memory Debug Config
DDR Debug Config
PCI/PCI-X Output Hold bit 0
PCI/PCI-X Output Hold bit 1
CFG12
CFG13
CFG14
CFG15
CFG18
CFG19
CFG27
CFG28
CFG29
CFG30
M11
G1
AF20
AG20
AH16
AG19
AH20
AG18
N12
G2
J9
G3
F3
F5
F2
F4
AG22
AG2
AH3
AF22
AB22
F1
E1
AH1
AG1
AH2
B1
B2
A2
A3
AH25
AH26
AH27
AH28
AG28
AF28
AE28
PIC
JTAG
MPC8540
CKSTP_IN
CKSTP_OUT
SRESET
HRESET_REQ
HRESET
IIC_SCL
IIC_SDA
DFT
PWR Mng.
RTC
SYSCLK
SYS. CNTRL
I2C
LSSD_MODE
TEST_SEL(Draco/Dracom)
ASLEEP
CLOCKING
SPARES
TDO
TRST
TMS
TDI
TCK
SPARE1
SPARE2
SPARE3
SPARE4
ANALOG
DMA_DREQ0
DMA_DREQ1
DMA_DACK0
DMA_DACK1
DMA_DDONE0
DMA_DDONE1
MCP
UDE
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9/DMA_DREQ3
IRQ10/DMA_DACK3
IRQ11/DMA_DDONE3
IRQ_OUT
TRIG_IN
TRIG_OUT/READY/QUIESCE
MSRCID0
MSRCID1
MSRCID2
MSRCID3
MSRCID4
MDVAL
L2_TSTCLK
CLK_OUT
CLKOUT_DIFF
CLKOUT_DIFF
THERM0
THERM1
L1_TSTCLK
EC_MDC
EC_MDIO
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
AUXILIARY FUNCTION
U11D
Eth.MI
Reset Configuration
Sys_PLL Ratio bit 0
Sys_PLL Ratio bit 1
Sys_PLL Ratio bit 2
Sys_PLL Ratio bit 3
Core_PLL Ratio bit 0
Core_PLL Ratio bit 1
Host/Agent Select bit 0
Host/Agent Select bit 1
DMA
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
DEBUG
12
SRESET*
CFG[1:32]
AH23
AH22
AB23
AH21
T11
U11
AF1
C1
AF19
AG23
AF23
AG21
AF21
H5
G4
H6
G5
H7
G6
AG17
AG16
AA18
Y18
AB18
AG24
AA21
Y19
AA19
AG25
AB20
Y20
AF26
AH24
AB21
R20
10K
R8
10K
R21
10K
R9
10K
R22
10K
R10
10K
SCL
SDA
R24
10K
R12
10K
SYSCLK
R23
10K
R11
10K
R25
10K
R13
10K
TDO
TRST
TMS
TDI
TCK
R26
10K
R14
10K
+3.3V
R27
10K
R15
10K
R28
10K
R16
10K
R18
10K
+3.3V
R17
10K
R19
10K
LDP0
LDP1
LDP2
LDP3
MPC8540
LALE
LBCTL
LCKE
LCLK0
LCLK1
LCLK2
LCS0
LCS1
LCS2
LCS3
LCS4
LCS5/DMA_DREQ2
LCS6/DMA_DACK2
LCS7/DMA_DDONE2
LA27
LA28
LA29
LA30
LA31
LWE0/LBS0
LWE1/LBS1
LWE2/LBS2
LWE3/LBS3
LGPL0/LSDA10
LGPL1/LSDWE
LGPL2/LOE/LSDRAS
LGPL3/LSDCAS
LGPL4/LGTA/LUPWAIT/LPBSE
LGPL5
LSYNC_IN
LSYNC_OUT
LOCAL BUS
LAD0
LAD1
LAD2
LAD3
LAD4
LAD5
LAD6
LAD7
LAD8
LAD9
LAD10
LAD11
LAD12
LAD13
LAD14
LAD15
LAD16
LAD17
LAD18
LAD19
LAD20
LAD21
LAD22
LAD23
LAD24
LAD25
LAD26
LAD27
LAD28
LAD29
LAD30
LAD31
U11F
CFG12
CFG1
CFG2
CFG3
CFG4
U18
T18
T19
T20
T21
V21
V20
U23
U27
U28
V18
Y27
Y28
W27
W28
R27
R28
P27
P28
CFG29
CFG30
CFG7
CFG8
CFG13
CFG14
CFG18
CFG19
R34
10K
+3.3V
CFG5
LAD0
LAD1
LAD2
LAD3
LAD4
LAD5
LAD6
LAD7
LAD8
LAD9
LAD10
LAD11
LAD12
LAD13
LAD14
LAD15
LAD16
LAD17
LAD18
LAD19
LAD20
LAD21
LAD22
LAD23
LAD24
LAD25
LAD26
LAD27
LAD28
LAD29
LAD30
LAD31
AB28
AB27
T23
P24
U19
U22
V28
V27
V23
V22
T27
T28
AA27
AA28
T26
P21
AD26
AD27
AD28
AC26
AC27
AC28
AA22
AA23
AA26
Y21
Y22
Y26
W20
W22
W26
V19
T22
R24
R23
R22
R21
R18
P26
P25
P20
P19
P18
N22
N23
N24
N25
N26
R31
10K
+3.3V
LALE
10K
R29
CFG6
+3.3V
R30
10K
+3.3V
LCS0*
LWR*
LBOE*
LAD[0:31]
Example Interface Schematics
Figure 9. MPC8540 CPU and Local Bus Interface
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
Freescale Semiconductor
R38
10K
R39
10K
+2.5V
R40
10K
MCS0*
MCKE
PMWE*
PRAS*
PCAS*
PMBA[0:1]
PMA[0:12]
PMDQS[0:8]
PMDM[0:8]
PMECC[0:7]
MCK*
MCK
PMBA0
PMBA1
VREF_+1.25V
PMA0
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMA12
N27
N20
M20
L19
E19
C21
A21
G19
A19
L24
H28
F24
L21
E18
E16
G14
B13
M19
L26
J25
D25
A22
H18
F16
F14
C13
C20
N19
B21
F21
K21
M21
C23
A23
B24
H23
G24
K19
B25
D27
J14
J13
B18
B19
MWE* D17
RAS* F17
CAS* J16
MCS0*
H16
G16
J15
H15
MCKE
E26
E28
MCK
J20
MCK*
F20
H25
G27
A15
B15
D20
E20
F28
F27
K14
L14
N28
M28
PMECC0
PMECC1
PMECC2
PMECC3
PMECC4
PMECC5
PMECC6
PMECC7
PMDM0
PMDM1
PMDM2
PMDM3
PMDM4
PMDM5
PMDM6
PMDM7
PMDM8
PMDQS0
PMDQS1
PMDQS2
PMDQS3
PMDQS4
PMDQS5
PMDQS6
PMDQS7
PMDQS8
U11B
MPC8540
MVREF(GVdd/2)
MECC0
MECC1
DDR SDRAM
MECC2
MECC3
MECC4
MECC5
MECC6
MECC7
MDM0
MDM1
MDM2
MDM3
MDM4
MDM5
MDM6
MDM7
MDM8
MDQS0
MDQS1
MDQS2
MDQS3
MDQS4
MDQS5
MDQS6
MDQS7
MDQS8
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MBA0
MBA1
MWEMRASMCASMCS0MCS1MCS2MCS3MCKE0
MCKE1
MCK0
MCK0MCK1
MCK1MCK2
MCK2MCK3
MCK3MCK4
MCK4MCK5
MCK5MSYNC_OUT
MSYNC_IN
GVdd1
GVdd2
GVdd3
GVdd4
GVdd5
GVdd6
GVdd7
GVdd8
GVdd9
GVdd10
GVdd11
GVdd12
GVdd13
GVdd14
GVdd15
GVdd16
GVdd17
GVdd18
GVdd19
GVdd20
GVdd21
GVdd22
GVdd23
GVdd24
GVdd25
GVdd26
GVdd27
GVdd28
GVdd29
GVdd30
GVdd31
GVdd32
GVdd33
GVdd34
GVdd35
GVdd36
GVdd37
GVdd38
GVdd39
GVdd40
GVdd41
MDQ0
MDQ1
MDQ2
MDQ3
MDQ4
MDQ5
MDQ6
MDQ7
MDQ8
MDQ9
MDQ10
MDQ11
MDQ12
MDQ13
MDQ14
MDQ15
MDQ16
MDQ17
MDQ18
MDQ19
MDQ20
MDQ21
MDQ22
MDQ23
MDQ24
MDQ25
MDQ26
MDQ27
MDQ28
MDQ29
MDQ30
MDQ31
MDQ32
MDQ33
MDQ34
MDQ35
MDQ36
MDQ37
MDQ38
MDQ39
MDQ40
MDQ41
MDQ42
MDQ43
MDQ44
MDQ45
MDQ46
MDQ47
MDQ48
MDQ49
MDQ50
MDQ51
MDQ52
MDQ53
MDQ54
MDQ55
MDQ56
MDQ57
MDQ58
MDQ59
MDQ60
MDQ61
MDQ62
MDQ63
J12
F12
C12
L13
G13
A14
K15
F15
D16
J17
E17
B17
G18
H19
F19
D19
K20
G20
A20
N21
D21
J22
E22
B22
L23
G23
H24
D24
M25
K25
F25
A25
A26
J27
A27
L28
G28
D28
C28
B28
A28
M26
L27
L22
K24
M24
M23
K27
K26
K22
J28
F26
E27
J26
J23
H26
G26
C26
E25
C24
E23
D26
C25
A24
D23
B23
F22
J21
G21
G22
D22
H21
E21
N18
J18
D18
L17
M18
L18
C18
A18
K17
K16
C16
B16
G17
L16
A16
L15
G15
E15
C14
K13
C15
D15
E14
D14
D13
E13
D12
A11
F13
H13
A13
B12
PMDQ0
PMDQ1
PMDQ2
PMDQ3
PMDQ4
PMDQ5
PMDQ6
PMDQ7
PMDQ8
PMDQ9
PMDQ10
PMDQ11
PMDQ12
PMDQ13
PMDQ14
PMDQ15
PMDQ16
PMDQ17
PMDQ18
PMDQ19
PMDQ20
PMDQ21
PMDQ22
PMDQ23
PMDQ24
PMDQ25
PMDQ26
PMDQ27
PMDQ28
PMDQ29
PMDQ30
PMDQ31
PMDQ32
PMDQ33
PMDQ34
PMDQ35
PMDQ36
PMDQ37
PMDQ38
PMDQ39
PMDQ40
PMDQ41
PMDQ42
PMDQ43
PMDQ44
PMDQ45
PMDQ46
PMDQ47
PMDQ48
PMDQ49
PMDQ50
PMDQ51
PMDQ52
PMDQ53
PMDQ54
PMDQ55
PMDQ56
PMDQ57
PMDQ58
PMDQ59
PMDQ60
PMDQ61
PMDQ62
PMDQ63
+2.5V
C20
0.1uF
C21
0.1uF
C30
10uF
C22
0.1uF
C23
0.1uF
C24
0.1uF
C31
10uF
C25
0.1uF
C26
0.1uF
C32
10uF
C27
0.1uF
PMDQ[0:63]
C28
0.1uF
C29
0.1uF
Example Interface Schematics
Figure 10. MPC8540 DDR SDRAM Interface
CompactPCI Reference Design, Rev. 1
13
PMDQ[0:63]
14
PMDQ31
PMDQ30
PMDQ29
PMDQ28
PMDQ27
PMDQ26
PMDQ25
PMDQ24
PMDQ23
PMDQ22
PMDQ21
PMDQ20
PMDQ19
PMDQ18
PMDQ17
PMDQ16
PMDQ15
PMDQ14
PMDQ13
PMDQ12
PMDQ11
PMDQ10
PMDQ9
PMDQ8
PMDQ7
PMDQ6
PMDQ5
PMDQ4
PMDQ3
PMDQ2
PMDQ1
PMDQ0
R41
22R
R49
22R
R57
22R
R65
22R
R73
22R
R81
22R
R89
22R
R97
22R
R105
22R
R113
22R
R119
22R
R125
22R
R131
22R
R137
22R
R143
22R
R149
22R
R155
22R
R161
22R
R169
22R
R177
22R
R183
22R
R189
22R
R193
22R
R197
22R
R203
22R
R209
22R
R215
22R
R221
22R
R227
22R
R233
22R
R241
22R
R247
22R
MDQ7
MDQ7
MDQ21
MDQ20
MDQ21
MDQ31
MDQ31
MDQ30
MDQ29
MDQ30
MDQ27
MDQ28
MDQ28
MDQ29
MDQ26
MDQ25
MDQ24
MDQ23
MDQ27
MDQ26
MDQ25
MDQ24
MDQ23
MDQ22
MDQ20
MDQ19
MDQ22
MDQ18
MDQ19
MDQ18
MDQ17
MDQ16
MDQ17
MDQ16
MDQ14
MDQ15
MDQ14
MDQ13
MDQ13
MDQ15
MDQ11
MDQ12
MDQ11
MDQ12
MDQ9
MDQ10
MDQ9
MDQ8
MDQ10
MDQ8
MDQ6
MDQ5
MDQ5
MDQ6
MDQ4
MDQ3
MDQ2
MDQ1
MDQ0
MDQ4
MDQ3
MDQ2
MDQ1
MDQ0
VTT_+1.25V
R42
25R
R50
25R
R58
25R
R66
25R
R74
25R
R82
25R
R90
25R
R98
25R
R106
25R
R114
25R
R120
25R
R126
25R
R132
25R
R138
25R
R144
25R
R150
25R
R156
25R
R162
25R
R170
25R
R178
25R
R184
25R
R190
25R
R194
25R
R198
25R
R204
25R
R210
25R
R216
25R
R222
25R
R228
25R
R234
25R
R242
25R
R248
25R
PMDQ32
PMDQ33
PMDQ34
PMDQ35
PMDQ36
PMDQ37
PMDQ38
PMDQ39
PMDQ40
PMDQ41
PMDQ42
PMDQ43
PMDQ44
PMDQ45
PMDQ46
PMDQ47
PMDQ48
PMDQ49
PMDQ50
PMDQ51
PMDQ52
PMDQ53
PMDQ54
PMDQ55
PMDQ56
PMDQ57
PMDQ58
PMDQ59
PMDQ60
PMDQ61
PMDQ62
PMDQ63
R43
22R
R51
22R
R59
22R
R67
22R
R75
22R
R83
22R
R91
22R
R99
22R
R107
22R
R115
22R
R121
22R
R127
22R
R133
22R
R139
22R
R145
22R
R151
22R
R157
22R
R163
22R
R171
22R
R179
22R
R185
22R
R191
22R
R195
22R
R199
22R
R205
22R
R211
22R
R217
22R
R223
22R
R229
22R
R235
22R
R243
22R
R249
22R
MDQ38
MDQ32
MDQ32
MDQ33
MDQ34
MDQ34
MDQ33
MDQ36
MDQ35
MDQ36
MDQ35
MDQ37
MDQ38
MDQ37
MDQ39
MDQ40
MDQ41
MDQ42
MDQ43
MDQ39
MDQ40
MDQ41
MDQ42
MDQ43
MDQ44
MDQ45
MDQ45
MDQ44
MDQ46
MDQ47
MDQ48
MDQ49
MDQ50
MDQ51
MDQ46
MDQ47
MDQ48
MDQ49
MDQ50
MDQ51
MDQ52
MDQ53
MDQ53
MDQ52
MDQ54
MDQ54
MDQ55
MDQ56
MDQ56
MDQ55
MDQ57
MDQ58
MDQ59
MDQ60
MDQ61
MDQ62
MDQ63
MDQ57
MDQ58
MDQ59
MDQ60
MDQ61
MDQ62
MDQ63
R44
25R
R52
25R
R60
25R
R68
25R
R76
25R
R84
25R
R92
25R
R100
25R
R108
25R
R116
25R
R122
25R
R128
25R
R134
25R
R140
25R
R146
25R
R152
25R
R158
25R
R164
25R
R172
25R
R180
25R
R186
25R
R192
25R
R196
25R
R200
25R
R206
25R
R212
25R
R218
25R
R224
25R
R230
25R
R236
25R
R244
25R
R250
25R
PMDQS[0:8]
PMBA[0:1]
PMA[0:12]
VTT_+1.25V
MDQ[0:63]
PMDQS8
PMDQS7
PMDQS6
PMDQS5
PMDQS4
PMDQS3
PMDQS2
PMDQS1
PMDQS0
PMBA1
PMBA0
PMA12
PMA11
PMA10
PMA9
PMA8
PMA7
PMA6
PMA5
PMA4
PMA3
PMA2
PMA1
PMA0
R201
22R
R207
22R
R213
22R
R219
22R
R225
22R
R231
22R
R237
22R
R245
22R
R251
22R
R165
22R
R173
22R
R45
22R
R53
22R
R61
22R
R69
22R
R77
22R
R85
22R
R93
22R
R101
22R
R109
22R
R117
22R
R123
22R
R129
22R
R135
22R
MDQS8
MDQS7
MDQS6
MDQS5
MDQS4
MDQS3
MDQS2
MDQS1
MDQS0
MBA1
MBA0
MA12
MA11
MA10
MA9
MA8
MA7
MA6
MDQS[0:8]
VTT_+1.25V
R166
25R
R174
25R
MBA[0:1]
VTT_+1.25V
R46
25R
R54
25R
R62
25R
R70
25R
R78
25R
R86
25R
R94
25R
R102
25R
R110
25R
R118
25R
R124
25R
R130
25R
R136
25R
VTT_+1.25V
MDQS0 R202
25R
MDQS1 R208
25R
MDQS2 R214
25R
MDQS3 R220
25R
MDQS4 R226
25R
MDQS5 R232
25R
MDQS6 R238
25R
MDQS7 R246
25R
MDQS8 R252
25R
MBA1
MBA0
MA12
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA4
MA5
MA3
MA3
MA2
MA1
MA1
MA2
MA0
MA0
MA[0:12]
MDM[0:8]
MECC[0:7]
VTT_+1.25V
R48
25R
R56
25R
R64
25R
R72
25R
R80
25R
R88
25R
R96
25R
R104
25R
R112
25R
R256
25R
R255
22R
R240
25R
MWE*
CAS*
RAS*
VTT_+1.25V
VTT_+1.25V
VTT_+1.25V
VTT_+1.25V
MECC0 R142
25R
MECC1 R148
25R
MECC2 R154
25R
MECC3 R160
25R
MECC4 R168
25R
MECC5 R176
25R
MECC6 R182
25R
MECC7 R188
25R
MDM8
MDM7
MDM6
MDM5
MDM4
MDM3
MDM2
MDM1
MDM0
PMWE*
MECC7
MECC6
MECC5
MECC4
MECC3
MECC2
MECC1
MECC0
MDM8
MDM7
MDM6
MDM5
MDM4
MDM3
MDM2
MDM1
MDM0
R254
25R
R239
22R
R141
22R
R147
22R
R153
22R
R159
22R
R167
22R
R175
22R
R181
22R
R187
22R
R47
22R
R55
22R
R63
22R
R71
22R
R79
22R
R87
22R
R95
22R
R103
22R
R111
22R
R253
22R
PMECC7
PMECC6
PMECC5
PMECC4
PMECC3
PMECC2
PMECC1
PMECC0
PMDM8
PMDM7
PMDM6
PMDM5
PMDM4
PMDM3
PMDM2
PMDM1
PMDM0
PCAS*
PRAS*
PMECC[0:7]
PMDM[0:8]
Example Interface Schematics
Figure 11. DDR SDRAM Termination
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
CFG[1:32]
Freescale Semiconductor
TSEC1 Protocol
TSEC2 Protocol
RIO Device ID bit 6
RIO Device ID bit 7
Local Bus Output Hold bit 0
Local Bus Output Hold bit 1
CFG16
CFG17
CFG21
CFG22
CFG31
CFG32
+3.3V
Boot ROM Location bit 2
Boot ROM Location bit 1
CFG10
CFG11
Boot ROM Location bit 0
CFG9
Reset Configuration
A4
C5
E7
H10
TSEC2_CRS
TSEC2_COL
TSEC2_RX_CLK
TSEC2_RX_DV
TSEC2_RX_ER
TSEC2_RXD0
TSEC2_RXD1
TSEC2_RXD2
TSEC2_RXD3
TSEC2_RXD4
TSEC2_RXD5
TSEC2_RXD6
TSEC2_RXD7
TSEC2_TX_EN
TSEC2_TX_ER
TSEC2_TX_CLK
TSEC2_GTX_CLK
TSEC2_TXD0
TSEC2_TXD1
TSEC2_TXD2
TSEC2_TXD3
TSEC2_TXD4
TSEC2_TXD5
TSEC2_TXD6
TSEC2_TXD7
TSEC1_CRS
TSEC1_COL
TSEC1_RX_CLK
TSEC1_RX_DV
TSEC1_RX_ER
TSEC1_RXD0
TSEC1_RXD1
TSEC1_RXD2
TSEC1_RXD3
TSEC1_RXD4
TSEC1_RXD5
TSEC1_RXD6
TSEC1_RXD7
TSEC1_TX_EN
TSEC1_TX_ER
TSEC1_TX_CLK
TSEC1_GTX_CLK
TSEC1_TXD0
TSEC1_TXD1
TSEC1_TXD2
TSEC1_TXD3
TSEC1_TXD4
TSEC1_TXD5
TSEC1_TXD6
TSEC1_TXD7
MPC8540
EC_GTX_CLK125
GbE Clocking
LVdd1
LVdd2
LVdd3
LVdd4
TSEC2
TSEC1
U11G
E2
D9
F8
E10
H8
A8
F10
G10
H9
A9
B9
C9
E9
F9
B11
D11
D10
C10
E11
G11
H11
J11
K11
J10
A10
B10
C3
G7
D6
D2
E5
E6
F6
A5
B5
D5
D3
B4
D4
C8
B8
C6
B6
E8
G8
A7
B7
C7
D7
F7
A6
CFG21
CFG22
CFG32
CFG31
CFG17
TXD12
TXD13
TXD15
TXD16
TXD17
CRS0
COL0
RX_CLK0
RX_DV0
RX_ER0
RXD00
RXD01
RXD02
RXD03
RXD04
RXD05
RXD06
RXD07
TX_EN0
TX_ER0
TX_CLK0
GTX_CLK0
TXD00
TXD01
TXD02
TXD03
TXD04
TXD05
TXD06
TXD07
ETHERA12
ETHERA13
ETHERA24
ETHERA22
ETHERA23
ETHERA14
ETHERA15
ETHERA16
ETHERA17
ETHERA18
ETHERA19
ETHERA20
ETHERA21
ETHERA8
ETHERA9
ETHERA10
ETHERA11
ETHERA0
ETHERA1
ETHERA2
ETHERA3
ETHERA4
ETHERA5
ETHERA6
ETHERA7
ETHERA4
ETHERA5
ETHERA6
ETHERA7
GTX_CLK125
CFG11
CFG10
CFG9
CFG16
ETHERA[0:24]
Example Interface Schematics
Figure 12. MPC8540 Gb Ethernet Interface
CompactPCI Reference Design, Rev. 1
15
16
AF25
AF24
MPC8540
RIO_TXCLK_IN-
RIO_TXCLK_IN
U11C
RIO_RD7-
RIO_RD7
RIO_RD6-
RIO_RD6
RIO_RD5-
RIO_RD5
RIO_RD4-
RIO_RD4
RIO_RD3-
RIO_RD3
RIO_RD2-
RIO_RD2
RIO_RD1-
RIO_RD1
RIO_RD0-
RIO_RD0
RIO_RFRAME-
RIO_RFRAME
RIO_RCLK-
RIO_RCLK
RIO_TD4
RIO_TD4RIO_TD5
RIO_TD5RIO_TD6
RIO_TD6RIO_TD7
RIO_TD7-
RIO_TD0
RIO_TD0RIO_TD1
RIO_TD1RIO_TD2
RIO_TD2RIO_TD3
RIO_TD3-
RIO_TCLK
RIO_TCLKRIO_TFRAME
RIO_TFRAME-
RIO23
RIO24
RIO25
RIO26
RIO_RD0
RIO_RD0*
RIO_RD1
T24
RIO27
RIO28
RIO29
RIO_RD2
RIO_RD2*
V25
V24
RIO32
RIO33
RIO34
RIO35
RIO36
RIO_RD4*
RIO_RD5
RIO_RD5*
RIO_RD6
AB25
AB24
AC25
RIO37
RIO38
RIO39
RIO_RD7
RIO_RD7*
AD25
AD24
AC24
RIO_RD6*
AA25
AA24
RIO31
RIO_RD3*
W24
RIO_RD4
RIO30
RIO_RD3
W25
U24
RIO_RD1*
U25
AE27
T25
RIO21
RIO_RCLK*
Y24
RIO22
RIO20
RIO_RCLK
Y25
RIO_RFRAME*
RIO12
RIO13
RIO14
RIO15
RIO16
RIO17
RIO18
RIO19
RIO_TD4
RIO_TD4*
RIO_TD5
RIO_TD5*
RIO_TD6
RIO_TD6*
RIO_TD7
RIO_TD7*
AD21
AC21
AE22
AD22
AC22
AE23
AD23
AC23
AE26
RIO4
RIO5
RIO6
RIO7
RIO8
RIO9
RIO10
RIO11
RIO_TD0
RIO_TD0*
RIO_TD1
RIO_TD1*
RIO_TD2
RIO_TD2*
RIO_TD3
RIO_TD3*
AE18
AD18
AC18
AE19
AD19
AC19
AE20
AD20
RIO_RFRAME
RIO0
RIO1
RIO2
RIO3
RIO_TCLK
RIO_TCLK*
RIO_TFRAME
RIO_TFRAME*
AC20
AE21
AE24
AE25
RIO[0:39]
Example Interface Schematics
Figure 13. MPC8540 RapidIO Interface
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
Boot ROM location bit 0
Boot ROM location bit 1
Boot ROM location bit 2
CPU Boot Configuration
CPU Boot Sequence bit 0
CPU Boot Sequence bit 1
TSEC Width
TSEC1 Protocol
Sys_PLL Ratio bit 0
Sys_PLL Ratio bit 1
Sys_PLL Ratio bit 2
Sys_PLL Ratio bit 3
Core_PLL Ratio bit 0
Core_PLL Ratio bit 1
Host/Agent Select bit 0
Host/Agent Select bit 1
Reset Configuration
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SW DIP-8
SW DIP-8
S3
S1
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
10K,5%
+3.3V
+3.3V
SYSCLK
10K,5%
RN3
1
48
25
24
30
29
27
26
36
35
33
32
41
40
38
37
47
46
44
43
HRESET
GND
GND
GND
GND
GND
GND
GND
GND
4Y1
4Y2
4Y3
4Y4
3Y1
3Y2
3Y3
3Y4
2Y1
2Y2
2Y3
2Y4
1Y1
1Y2
1Y3
1Y4
+3.3V
IDT54FCT162244/FP
1OE
2OE
3OE
4OE
4A1
4A2
4A3
4A4
3A1
3A2
3A3
3A4
2A1
2A2
2A3
2A4
1A1
1A2
1A3
1A4
U12
7
18
31
42
VCC
VCC
VCC
VCC
10
5
9
8
7
6
4
3
2
1
9
8
7
6
4
3
2
1
10
5
45
39
34
28
21
15
10
4
19
20
22
23
13
14
16
17
8
9
11
12
2
3
5
6
R257
10K
+3.3V
CFG13
CFG14
CFG15
CFG16
CFG9
CFG10
CFG11
CFG12
CFG5
CFG6
CFG7
CFG8
CFG1
CFG2
CFG3
CFG4
6
7
1
9
4
5
12
13
74LV175
MRST
CLK
D0
D1
D2
D3
U14
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
3
6
11
14
2
7
10
15
bit
bit
bit
bit
bit 0
bit 1
PCI Debug
PCI Mode Config
Memory Debug Config
DDR Debug Config
PCI/PCI-X Output Hold
PCI/PCI-X Output Hold
Local Bus Output Hold
Local Bus Output Hold
TSEC2 Protocol
RIO Tx CLK Source
RIO Tx CLK Source
PCI Width (32/64)
RIO Device ID bit
RIO Device ID bit
PCI I/O Impedance
PCI Arbiter
Reset Configuration
0
1
0
1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SW DIP-8
SW DIP-8
S4
S2
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
10K,5%
RN2
+3.3V
10
5
9
8
7
6
4
3
2
1
+3.3V
9
8
7
6
4
3
2
1
Freescale Semiconductor
10
5
10K,5%
RN4
1
48
25
24
30
29
27
26
36
35
33
32
41
40
38
37
47
46
44
43
GND
GND
GND
GND
GND
GND
GND
GND
4Y1
4Y2
4Y3
4Y4
3Y1
3Y2
3Y3
3Y4
2Y1
2Y2
2Y3
2Y4
1Y1
1Y2
1Y3
1Y4
+3.3V
IDT54FCT162244/FP
1OE
2OE
3OE
4OE
4A1
4A2
4A3
4A4
3A1
3A2
3A3
3A4
2A1
2A2
2A3
2A4
1A1
1A2
1A3
1A4
U13
7
18
31
42
VCC
VCC
VCC
VCC
RN1
45
39
34
28
21
15
10
4
19
20
22
23
13
14
16
17
8
9
11
12
2
3
5
6
CFG29
CFG30
CFG31
CFG32
CFG25
CFG26
CFG27
CFG28
CFG21
CFG22
CFG23
CFG24
CFG17
CFG18
CFG19
CFG20
CFG[1:32]
Example Interface Schematics
Figure 14. MPC8540 Power on Configuration Logic
CompactPCI Reference Design, Rev. 1
17
CFG[1:32]
18
PCI_GNT1
PCI_GNT2
PCI_GNT3
PCI_GNT4
PCI_REQ64
CFG23
CFG24
CFG25
CFG26
CFG20
SYSCLK
Mode Config
PCI Width (32/64)
PCI
PCI Debug
PCI Arbiter
PCI I/O Impedance
Reset Configuration
PCI_REQ64
PCICLK
PCI80
PCI86
GNT0
PCI_GNT1
PCI_GNT2
PCI_GNT3
PCI_GNT4
PAR
PAR64
FRAME*
TRDY*
IRDY*
STOP*
DEVSEL*
IDSEL*
REQ64*
ACK64*
PERR*
SERR*
REQ0
PCI72
PCI73
PCI74
PCI75
PCI76
PCI77
PCI78
PCI79
PCI80
PCI81
PCI82
PCI83
PCI84
PCI85
C_BE0
C_BE1
C_BE2
C_BE3
C_BE4
C_BE5
C_BE6
C_BE7
PCI64
PCI65
PCI66
PCI67
PCI68
PCI69
PCI70
PCI71
AA11
Y14
AC10
AG10
AD10
V11
AH10
AA9
AE13
AD13
W11
Y11
AF5
AF3
AE4
AG4
AE5
AE6
AG5
AH5
AF6
AG6
AC12
AD11
AB10
AH8
W14
V14
AH13
AG13
MPC8540
PCI_PAR
PCI_PAR64
PCI_FRAME
PCI_TRDY
PCI_IRDY
PCI_STOP
PCI_DEVSEL
PCI_IDSEL
PCI_REQ64
PCI_ACK64
PCI_PERR
PCI_SERR
PCI_REQ0
PCI_REQ1
PCI_REQ2
PCI_REQ3
PCI_REQ4
PCI_GNT0
PCI_GNT1
PCI_GNT2
PCI_GNT3
PCI_GNT4
PCI_C_BE0
PCI_C_BE1
PCI_C_BE2
PCI_C_BE3
PCI_C_BE4
PCI_C_BE5
PCI_C_BE6
PCI_C_BE7
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_AD32
PCI_AD33
PCI_AD34
PCI_AD35
PCI_AD36
PCI_AD37
PCI_AD38
PCI_AD39
PCI_AD40
PCI_AD41
PCI_AD42
PCI_AD43
PCI_AD44
PCI_AD45
PCI_AD46
PCI_AD47
PCI_AD48
PCI_AD49
PCI_AD50
PCI_AD51
PCI_AD52
PCI_AD53
PCI_AD54
PCI_AD55
PCI_AD56
PCI_AD57
PCI_AD58
PCI_AD59
PCI_AD60
PCI_AD61
PCI_AD62
PCI_AD63
PCIX/PCI
U11A
AC13
AB13
Y13
V13
AH12
AG12
AE12
AD12
AB12
Y12
W12
V12
AH11
AG11
AF11
AE11
AA10
Y10
W10
AH9
AG9
AF9
AE9
AD9
AG8
AF8
AC8
AB8
AH7
AE7
AD7
AH6
AF18
AF17
AE17
AB17
AA17
Y17
W17
V17
AF16
AE16
AD16
AC16
AB16
W16
V16
AH15
AG15
AD15
AC15
AB15
AA15
Y15
W15
V15
AH14
AG14
AF14
AE14
AD14
AC14
AB14
AA14
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AD39
AD40
AD41
AD42
AD43
AD44
AD45
AD46
AD47
AD48
AD49
AD50
AD51
AD52
AD53
AD54
AD55
AD56
AD57
AD58
AD59
AD60
AD61
AD62
AD63
PCI0
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6
PCI7
PCI8
PCI9
PCI10
PCI11
PCI12
PCI13
PCI14
PCI15
PCI16
PCI17
PCI18
PCI19
PCI20
PCI21
PCI22
PCI23
PCI24
PCI25
PCI26
PCI27
PCI28
PCI29
PCI30
PCI31
PCI32
PCI33
PCI34
PCI35
PCI36
PCI37
PCI38
PCI39
PCI40
PCI41
PCI42
PCI43
PCI44
PCI45
PCI46
PCI47
PCI48
PCI49
PCI50
PCI51
PCI52
PCI53
PCI54
PCI55
PCI56
PCI57
PCI58
PCI59
PCI60
PCI61
PCI62
PCI63
PCI[0:86]
Example Interface Schematics
Figure 15. MPC8540 PCI/PCI-X Interface
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
M1
N1
N4
N5
N6
N7
N8
N9
N10
N11
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
R1
R2
R3
R4
R5
R6
R7
U11H
Alt. DUART
MPC8540
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26/UART_RTS1
PD27/UART_SOUT1
PD28/UART_SIN1
PD29/UART_RTS0
PD30/UART_SOUT0
PD31/UART_SIN0
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13/UART_CTS1
PC14
PC15/UART_CTS0
PC16
PC17/FEC_RX_CLK
PC18/FEC_TX_CLK
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
CPM
PB4/FEC_TXD3
PB5/FEC_TXD2
PB6/FEC_TXD1
PB7/FEC_TXD0
PB8/FEC_RXD0
PB9/FEC_RXD1
PB10/FEC_RXD2
PB11/FEC_RXD3
PB12/FEC_CRS
PB13/FEC_COL
PB14/FEC_TX_EN
PB15/FEC_TX_ER
PB16/FEC_RX_ER
PB17/FEC_RX_DV
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
Alt. 10/100 Eth. Alt. DUART
Freescale Semiconductor
Alt. 10/100 Eth.
H1
H2
J1
J2
J3
J4
J5
J6
J7
J8
K8
K7
K6
K3
K2
K1
L1
L2
L3
L4
L5
L8
L9
L10
L11
M10
M9
M8
M7
M6
M3
M2
Y1
Y2
Y3
Y4
Y5
Y6
AA8
AA7
AA4
AA3
AA2
AA1
AB1
AB2
AB3
AB5
AB6
AC7
AC4
AC3
AC2
AC1
AD1
AD2
AD5
AD6
AE3
AE2
R8
R9
R10
R11
T9
T6
T5
T4
T1
U1
U2
U3
U4
U7
U8
U9
U10
V9
V6
V5
V4
V3
V2
V1
W1
W2
W3
W6
W7
W8
W9
Y9
SIN0
SOUT0
SIN1
SOUT1
Example Interface Schematics
Figure 16. MPC8540 Parallel I/O and DUART Interface
CompactPCI Reference Design, Rev. 1
19
20
C59
0.1uF
C60
0.1uF
C61
0.1uF
C69
10uF
C62
0.1uF
C63
0.1uF
C64
0.1uF
C70
10uF
C65
0.1uF
0.1uF
C43
0.1uF
C33
C66
0.1uF
0.1uF
C44
0.1uF
C34
C71
10uF
C67
0.1uF
10uF
C53
0.1uF
C45
0.1uF
C35
C68
0.1uF
+1.2V
10uF
C54
0.1uF
C46
0.1uF
C36
10uF
C55
0.1uF
C47
0.1uF
C37
U12
R12
T13
P13
M13
U14
R14
N14
T15
P15
M15
R16
N16
T17
P17
M17
SENSE_VSS
SENSE_VDD
AVdd1
AVdd2
AVdd3
MPC8540
10uF
C58
0.1uF
C50
0.1uF
C40
CORE &PLL
Supply
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
10uF
C57
0.1uF
C49
0.1uF
C39
U11E
10uF
C56
0.1uF
C48
0.1uF
C38
K12
L12
AH19
AH18
AH17
0.1uF
C51
0.1uF
C41
0.1uF
C52
0.1uF
C42
+3.3V
AF2
N2
C2
AG3
AD3
T3
E3
B3
AF4
AB4
M4
H4
C4
W5
K5
AC6
AA6
U6
L6
AG7
V7
AD8
Y8
T8
D8
AC9
K9
G9
AF10
V10
T10
AB11
F11
C11
T12
P12
M12
H12
G12
AE1
D1
T2
N3
H3
AH4
AD4
W4
K4
E4
AC5
AA5
U5
M5
AF7
AB7
Y7
T7
L7
AE8
V8
AB9
AE10
K10
AC11
AF12
AA12
W13
AE15
AA16
AC17
W19
R19
AA20
U20
W21
P22
Y23
R25
AB26
U26
AG27
U11I
MPC8540
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
OVdd1
OVdd2
OVdd3
OVdd4
OVdd5
OVdd6
OVdd7
OVdd8
OVdd9
OVdd10
OVdd11
OVdd12
OVdd13
OVdd14
OVdd15
OVdd16
OVdd17
OVdd18
OVdd19
OVdd20
OVdd21
OVdd22
OVdd23
OVdd24
OVdd25
OVdd26
OVdd27
OVdd28
OVdd29
OVdd30
OVdd31
OVdd32
OVdd33
OVdd34
OVdd35
OVdd36
OVdd37
OVdd38
OVdd39
OVdd40
OVdd41
OVdd42
POWER
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97
GND98
GND99
E12
A12
AF13
AA13
U13
R13
N13
T14
P14
M14
H14
B14
AF15
U15
R15
N15
Y16
U16
T16
P16
M16
AD17
U17
R17
N17
H17
C17
A17
W18
K18
F18
AB19
J19
C19
R20
L20
H20
B20
U21
M22
H22
C22
W23
P23
K23
F23
J24
E24
L25
G25
AG26
V26
R26
B26
AF27
M27
H27
C27
B27
K28
Example Interface Schematics
Figure 17. MPC8540 Power Connections
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
PCI[0:86]
Freescale Semiconductor
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
+5V
PCI84
PCI30
PCI26
PCI67
PCI21
PCI18
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
C_BE5
AD63
AD59
AD56
AD52
AD49
AD45
AD42
AD38
AD35
PCI69
PCI63
PCI59
PCI56
PCI52
PCI49
PCI45
PCI42
PCI38
PCI35
+3.3V
PCI1
+5V
PCI12
PCI7
AD12
AD1
PCI83
SERR*
AD7
PCI78
DEVSEL*
+3.3V
REQ0
AD30
AD26
C_BE3
AD21
AD18
CONN6x22
J2A
CONN6x25
J1A
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
CONN6x22
J2B
PCI29
PCI55
PCI48
PCI41
PCI34
AD55
AD48
AD41
AD34
PCI62
+5V
PCI80
PCI4
PCI9
PCI15
PCI74
PCI17
PCI79
AD62
REQ64*
AD4
AD9
AD15
FRAME*
+5V
B1
B2
B3
B4
B5
B6
B7 AD29
B8
B9 IDSEL*
B10
B11 AD17
CONN6x25
J1B
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
PCI40
PCI33
AD40
AD33
PCI54
PCI47
PCI61
AD47
AD54
PCI71
AD61
C_BE7
+3.3V
PCI3
PCI8
PCI14
PCI76
Connector J2
CONN6x22
J2C
AD3
AD8
AD14
IRDY*
C1
+3.3V
C2
C3
C4
C5
C6
PCI28
C7 AD28
C8
PCI23
C9 AD23
C10
PCI16
C11 AD16
CONN6x25
J1C
Connector J1
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
CONN6x22
J2D
PCI25
PCI86
AD37
AD44
AD51
AD58
C_BE4
+3.3V
AD0
AD6
AD11
PCI37
PCI44
PCI51
PCI58
PCI68
+5V
PCI0
PCI6
PCI11
PCI77
PCI72
PAR
PCI20
STOP*
D1
+5V
D2
D3
D4
D5
D6 PCICLK
D7
D8 AD25
D9
D10 AD20
D11
CONN6x25
J1D
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
CONN6x22
J2E
CONN6x25
J1E
C_BE6
PAR64
AD60
AD57
AD53
AD50
AD46
AD43
AD39
AD36
AD32
+5V
PERR*
C_BE1
AD13
AD10
C_BE0
AD5
AD2
ACK64*
TRDY*
GNT0
AD31
AD27
AD24
AD22
AD19
C_BE2
+5V
PCI70
PCI73
PCI60
PCI57
PCI53
PCI50
PCI46
PCI43
PCI39
PCI36
PCI32
PCI82
PCI65
PCI13
PCI10
PCI64
PCI5
PCI2
PCI81
PCI75
PCI85
PCI31
PCI27
PCI24
PCI22
PCI19
PCI66
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
CONN6x22
J2F
CONN6x25
J1F
Example Interface Schematics
Figure 18. Compact PCI J1 and J2 Connectors
CompactPCI Reference Design, Rev. 1
21
+3.3V
4
8
66MHz
GND
VDD
Y1
OUT
5
S5
Reset Switch
R257
1K
+3.3V
+3.3V
C72
0.1uF
+3.3V
7
10
14
18
22
26
30
6
5
1
2
3
4
PCLK
PCLK
MR
VDD
MAX6314
3
4
U15
RESET
MPC9448
MPC9448
VCC
VCC
VCC
VCC
VCC
VCC
VCC
OE
CLK_STOP
CLK_SEL
CCLK
GND
22
1
U14
2
GND
GND
GND
GND
GND
GND
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
SYS_HRESET_N
R258
1K
+3.3V
8
12
16
20
24
28
32
31
29
27
25
23
21
19
17
15
13
11
9
SYS_HRESET*
SYSCLKA
Example Interface Schematics
Figure 19. Clock and Reset Logic
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
+
+5V
68uF
C73
+
68uF
C74
SW SPDT
SW SPDT
SW4
SW SPDT
SW3
R263
100K
0.1uF
C76
+5V
SW SPDT
SW2
SW1
0.47uF
C75
This sets 1.2V
R268
2K
Note :- Default settings for Switchs
D4
D3
D2
D1
D0
0
0
1
1
1
+3.3V
C89
0.56uF
C88
C81
0.1uF
MAX1627
GND
SHDN
OUT
REF
V+
1.0uF CERAMIC
0.6nF
C90
R267
40.1K
8
3
1
4
5
R047
5
6
7
2
10
13
14
15
8
16
17
+
2
7
6
MAX1624
REF
CC1
CC2
FREQ
LG
D4
D3
D2
D1
D0
PWROK
U18
C79
4.7uF
FB
EXT
CS
100K
R262
R261
10K
1
4
U17
G
D1
D2
D3
D4
5
6
7
8
DL
LX
DH
BST
AGND
FB
PDRV
NDRV
PGND
MAX1624
CSL
CSH
11
12
19
18
22
21
23
24
1
3
4
MMSF3P02HD
N/C
9
VCC
U16
S1
S2
2
3
20
VDD
Freescale Semiconductor
C85
4.7nF
D3
C82
0.1uF
+
R266
39R
R264
39R
C84
4.7nF
0.1uF
C78
R260
9K1
1N5820
1
2
R259
C83
4.7uF
+
Q2
MTB50N06VL
Q1
MTB50N06VL
R265
1.7m
10uH, 2.5A
L1
150uF
C77
C86
0.1uF
1
C80
300uF
79nH
L2
CMPSH-3
D4
+
+5V
+2.5V
2
+
C87
3.6mF
+1.2V
Example Interface Schematics
Figure 20. Local Power Supply Logic
CompactPCI Reference Design, Rev. 1
23
DVDDL_E3A
C94
0.1uF
DVDDL_1_5V
C96
0.1uF
VDDO_3_3V
C95
0.01uF
DVDDL_H3A
+2.5V
0.01uF
0.1uF
AVDDL_2_5V
C110
C109
0.1uF
0.01uF
C112
0.1uF
C113
0.1uF
0.01uF
0.1uF
0.01uF
C111
C105
C104
C103
C102
AVDDL_2_5V
C93
4.7UF
VDDO_3_3V
0.1uF
AVDDL_B1
+
+1.5V
C97
0.01uF
GTX_CLK
TX_CLK
TX_EN
TX_ER
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
TXD0
RX_CLK
RX_DV
RX_ER
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
RXD0
CRS
COL
C101
VDDO_C6
DVDDL_D7A
VDDO_C5
DVDDL_1_5V
VDDO_E7
A8
RXD2
A7
RXD0
B7
C6
VDDO_C6
RXD1
B6
RX_CLK
D5
A6
C5
VDDO_C5
GND_D5
RX_DV
B5
A5
RX_ER
COL
RXD_2
RXD_1
RXD_0
VDDO
RX_CLK
RX_DV
GND
VDDO
RX_ER
COL
GND
GND
TX_CLK
CRS
AVDDL
GTX_CLK
TX_ER
TXD_0
TX_EN
COMA
TXD3
F2
TXD2
F1
GND_E4
DVDDL_E3A
MDIO
LED_LINK100
101
010
CONFIG5
CONFIG6
LED_RX
VDDO_3_3V
111
LED_LINK10
VDDO_3_3V
LED_LINK1000
GND
CONNECTION
CONFIG4
111
110
CONFIG3
100
000
BIT[2:0]
CONFIG2
CONFIG1
CONFIG0
PIN
TXD4
DVDDL_H3A
TXD6
G3
M88E1011
MDC
GND_H5
DISABLE AUTO SELECTION OF FIBER/COPPER INTERFACE
ENABLE ENERGY DETECT
GMII TO COPPER
MDC/MDIO INTERFACE
INT SIGNAL IS ACTIVE HIGH
50 OHM TERMINATION
GMII TO COPPER MODE
ENABLE PAUSE
PHYADR[4] = 0
PHYADR[3] = 0
AUTO-NEGOTIATION
ADVERTISE ALL CAPABILITIES
PREFER SLAVE
ENABLE 125 MHZ CLOCK
ENABLE MDI CROSSOVER
ENABLE AUTO
NEGOTIATION
CLK25
VDDO_J3
NOTE:
SEL_2_5V PIN TIED
TO GND FOR 3.3V
I/O
PHYADR[2] = 0, PHYADR[1] = 0, PHYADR[0] = 0
DESCRIPTION
Pin To Configuration Constant Mapping
MDC
MDIO
GTX_CLK125
+3.3V
B4
D4
A4
GND_D4
C4
B1
AVDDL_B1
TX_CLK
B3
CRS
A3
GND_C4
B2
TXD0
GTX_CLK
A2
A1
TX_ER
TX_EN
U19
TXD5
G2
4.7K
2.49K 1%
MDI0_PA
0.01uF
0.01uF
0.01uF
MDI0_MA
C118
MDI1_PA
MDI0_PA
0.01uF
MDI1_MA
C116
MDI2_PA
MDI2_MA
C114
MDI3_PA
MDI3_MA
C107
MDI3_PA
MDI3_MA
N8
N9
49.9
49.9
49.9
49.9
49.9
49.9
R293
R292
49.9
49.9
AVDDL_2_5V
R290
R289
AVDDL_2_5V
R287
R286
0.1uF
C117
0.1uF
C115
0.1uF
C108
9
8
7
6
5
4
3
2
1
12
11
10
49.9
49.9
0.1uF
C106
MDI2_MA
AVDDL_M8
M8
AVDDL_M7
M7
N7
GND_L7
L7
MDI2_PA
HDAC_NA R279
M6
N6
GND_L6
L6
GND_K6
N5
K6
AVDDH_N5
M5
GND_L5
GND_K5
GND_J5
MDI1_MA
GND_L4
MDI1_PA
AVDDL_2_5V
R284
MDI0_MA
AVDDL_M3
HDAC_PA R277
L5
K5
J5
N4
M4
L4
N3
M3
N2
AVDDL_2_5V
R283
4.7K
R280
MDI3_M
MDI3_P
AVDDL
MDI2_M
AVDDL
GND
MDI2_P
HDAC_N
GND
GND
AVDDH
HDAC_P
GND
GND
GND
MDI1_M
CTRL_25
GND
MDI1_P
AVDDL
MDI0_M
TD4_M
TD4_P
TCT4
TD3_M
TD3_P
TCT3
TD2_M
TD2_P
TCT2
TD1_M
TD1_P
TCT1
U21
D5
332
TX
LED_TXA
LED_RXA
LED_DUPLEXA
LED_LINK_1000A
LED_LINK_100A
LED_LINK_10A
LED_GREEN
D6
332
R270
RX
C92
0.1uF
AVDDH_3_3V
Pulse H5007
1:1
1:1
1:1
1:1
1:1
1:1
1:1
1:1
DPLX
MX4_M
MX4_P
MCT4
MX3_M
MX3_P
MCT3
MX2_M
MX2_P
MCT2
MX1_M
MX1_P
MCT1
D7
332
R271
13
14
15
16
17
18
19
20
21
22
23
24
LED_GREEN
R269
VDDO_3_3V
LNK_1000
R291
R288
R285
R282
+3.3V
C91
0.1uF
75
75
75
75
VDDO_3_3V
7
6
5
8
D8
332
GND
VDD
25MHz
LNK_100
OUT
D9
332
R273
+3.3V
5
+3.3V
VOUT
GND
BYP
SENSE
1000P/3KV
C100
LT1763CS8
GND
GND
SHDN
VIN
LT1763CS8-1.5
U20
4
8
Y2
R272
LED_GREEN
SYS_HRESET*
B8
DVDDL_G7A
AVDDL_L2
A9
ETHERA11
ETHERA10
ETHERA8
ETHERA9
ETHERA7
ETHERA6
ETHERA5
ETHERA4
ETHERA3
ETHERA2
ETHERA1
ETHERA0
ETHERA24
ETHERA22
ETHERA23
ETHERA21
ETHERA20
ETHERA19
ETHERA18
ETHERA17
ETHERA16
ETHERA15
ETHERA14
ETHERA12
ETHERA13
VDDO_J3
AVDDL_M3
VDDO_H7
AVDDL_M7
AVDDL_M8
D1
SIN_P
C1
SIN_M
C2
SOUT_M
B9
RXD4
RXD_3
GND_C7
RXD5
RXD3
RXD_4
TXD1
C7
RXD_5
D2
SOUT_P
C8
GND
E1
TXD_1
D3
SCLK_P
C3
SCLK_M
C9
RXD6
RXD_6
D6
GND_D6
RXD7
RXD_7
D7
DVDDL_D7A
GND
E2
CTRL_15
DVDDL
E4
GND
GND_F4
F4
GND
G1
TXD_4
INT
E3
DVDDL
CLK125
D8
TXD_2
E5
GND
E6
GND_E6
GND_E5
MDIO
D9
TXD_3
GND
VDDO_E7
LED_LINK10
F3
DVDDH
VDDO
E7
TXD_5
F5
GND
F6
GND_F5
GND
GND_F6
SEL_2_5V
F7
MDC
E8
GND_G4
G4
GND
TXD7
G6
LED_LINK100
LED_LINK_100A F9
GND
GND_G6
F8
LED_LINK_10A
E9
10K
R281
DVDDH
GND_G5
G5
GND
H1
TXD_6
GND_H4
H4
GND
H2
TXD_7
H3
DVDDL
DVDDL
G7
DVDDL_G7A
LED_LINK1000
LED_LINK_1000A G8
H5
GND
J1
XTAL2
GND
H6
GND_H6
LED_DPLX
LED_DUPLEXA G9
GND_J4
J4
GND
J3
VDDO
J2
XTAL1
VDDO
H7
LED_RX
H8
LED_RXA
VDDO_H7
LED_TX
H9
LED_TXA
GND_K3
VSSC
K3
GND
K1
TCK
GND
J6
GND_J6
K2
RESET
K4
VSSC
CONFIG_0
J8
CONFIG_5
LED_LINK_100A J7
CONFIG_1
J9
LED_LINK_1000A
AVDDL_L2
L2
AVDDL
CONFIG_2
L1
TMS
CONFIG_6
K7
LED_RXA
K8
CONFIG_2
VDDO_3_3V
GND_L3
K9
M2 R276
RST
N1
MDI0_P
L3
GND
CONFIG_3
LED_LINK_10A
AVDDH_N5
M1 R275
TRST
TDO
L8
TDI
M9
CONFIG_4
L9
CONFIG_4
VDDO_3_3V
LED_GREEN
GND_C4
GND_C7
GND_D4
GND_D5
GND_D6
GND_E4
GND_E5
GND_E6
GND_F4
GND_F5
GND_F6
GND_G4
GND_G5
GND_G6
GND_H4
GND_H5
GND_H6
GND_J4
GND_J5
GND_J6
GND_K3
GND_K4
GND_K5
GND_K6
GND_L3
GND_L4
GND_L5
GND_L6
GND_L7
VSSC
LED_GREEN
24
LNK_10
1
2
3
4
5
6
7
8
C99
0.01uF
CLK25
RJ45
DA_P
DA_M
DB_P
DC_P
DC_M
DB_M
DD_P
DD_M
CON1
Local 1.5V
supply for
PHY
3
4
2
1
AVDDH_3_3V
22R
R278
VDDO_3_3V
D10
332
R274
LED_GREEN
ETHERA[0:24]
+
+1.5V
C98
10uF
Example Interface Schematics
Figure 21. Gb Ethernet Transceiver
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
Freescale Semiconductor
5
9
4
8
3
7
2
6
1
D9 Connector
P2
D9 Connector
5
9
4
8
3
7
2
6
1
+
C122
0.1uF
3
0.1uF
15
2
7
8
14
13
1
+ C119
U22
GND
V+
T2OUT
R2IN
T1OUT
R1IN
C1-
C1+
MAX3232
VCC
V-
T2IN
R2OUT
T1IN
R1OUT
C2-
C2+
16
6
10
9
11
12
5
4
+
C123
0.1uF
+3.3V
0.1uF
+ C120
+
P1
0.1uF
C121
Note Polarity
SOUT1
SIN1
SOUT0
SIN0
Example Interface Schematics
Figure 22. RS232 Interface Logic
CompactPCI Reference Design, Rev. 1
25
RIO[0:39]
RIO_RD5
RIO_RD5*
RIO_RD6
RIO_RD6*
RIO_RD7
RIO_RD7*
RIO35
RIO36
RIO37
RIO38
RIO39
RIO_RD4*
RIO33
RIO34
RIO_RD4
RIO_RD2*
RIO29
RIO32
RIO_RD2
RIO28
RIO_RD3
RIO_RD1*
RIO27
RIO_RD3*
RIO_RD1
RIO31
RIO_RD0*
RIO25
RIO26
RIO30
RIO_RD0
RIO_RFRAME*
RIO24
RIO23
RIO_RCLK*
RIO_RFRAME
RIO21
RIO_RCLK
RIO20
RIO22
RIO_TD4
RIO_TD4*
RIO_TD5
RIO_TD5*
RIO_TD6
RIO_TD6*
RIO_TD7
RIO_TD7*
RIO_TD0
RIO_TD0*
RIO_TD1
RIO_TD1*
RIO_TD2
RIO_TD2*
RIO_TD3
RIO_TD3*
RIO4
RIO5
RIO6
RIO7
RIO8
RIO9
RIO10
RIO11
RIO12
RIO13
RIO14
RIO15
RIO16
RIO17
RIO18
RIO19
RIO_TCLK
RIO_TCLK*
RIO_TFRAME
RIO_TFRAME*
RIO_RFRAME
RIO_RFRAME*
RIO_RD7
RIO_RD7*
RIO_RD6
RIO_RD6*
RIO_RD5
RIO_RD5*
RIO_RD4
RIO_RD4*
RIO_RCLK
RIO_RCLK*
RIO_RD3
RIO_RD3*
RIO_RD2
RIO_RD2*
RIO_RD1
RIO_RD1*
RIO_RD0
RIO_RD0*
A1
B1
BG1
C1
D1
DG1
A2
B2
BG2
C2
D2
DG2
A3
B3
BG3
C3
D3
DG3
A4
B4
BG4
C4
D4
DG4
A5
B5
BG5
C5
D5
DG5
A6
B6
BG6
C6
D6
DG6
A7
B7
BG7
C7
D7
DG7
A8
B8
BG8
C8
D8
DG8
A9
B9
BG9
C9
D9
DG9
A10
B10
BG10
C10
D10
DG10
A B
A1
B1
BG1
C1
D1
DG1
A2
B2
BG2
C2
D2
DG2
A3
B3
BG3
C3
D3
DG3
A4
B4
BG4
C4
D4
DG4
A5
B5
BG5
C5
D5
DG5
A6
B6
BG6
C6
D6
DG6
A7
B7
BG7
C7
D7
DG7
A8
B8
BG8
C8
D8
DG8
A9
B9
BG9
C9
D9
DG9
A10
B10
BG10
C10
D10
DG10
A B
J4
BG
DG FG
E F
E F
1460902-2
C D
C D
HG
G H
H1
G1
HG1
F1
E1
FG1
H2
G2
HG2
F2
E2
FG2
H3
G3
HG3
F3
E3
FG3
H4
G4
HG4
F4
E4
FG4
H5
G5
HG5
F5
E5
FG5
H6
G6
HG6
F6
E6
FG6
H7
G7
HG7
F7
E7
FG7
H8
G8
HG8
F8
E8
FG8
H9
G9
HG9
F9
E9
FG9
H10
G10
HG10
F10
E10
FG10
G H
H1 RIO_TFRAME
G1 RIO_TFRAME*
HG1
F1
E1
FG1
RIO_TD7
H2
RIO_TD7*
G2
HG2
F2
E2
FG2
RIO_TD6
H3
RIO_TD6*
G3
HG3
F3
E3
FG3
RIO_TD5
H4
RIO_TD5*
G4
HG4
F4
E4
FG4
RIO_TD4
H5
RIO_TD4*
G5
HG5
F5
E5
FG5
RIO_TCLK
H6
RIO_TCLK*
G6
HG6
F6
E6
FG6
RIO_TD3
H7
RIO_TD3*
G7
HG7
F7
E7
FG7
RIO_TD2
H8
RIO_TD2*
G8
HG8
F8
E8
FG8
RIO_TD1
H9
RIO_TD1*
G9
HG9
F9
E9
FG9
RIO_TD0
H10
RIO_TD0*
G10
HG10
F10
E10
FG10
+5V
+3.3V
C4
C3
C2
C1
B4
B3
B2
B1
A4
A3
A2
A1
C4
C3
C2
C1
B4
B3
B2
B1
A4
A3
A2
A1
A
B
C
223956-1
223955-2
A
B
C
223955-2
1
J7
223956-1
Guide Pin
J6
J5
J3
Guide Pin
1
26
RIO0
RIO1
RIO2
RIO3
Example Interface Schematics
Figure 23. Optional RapidIO Connector
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
DEBUG[0:8]
Freescale Semiconductor
COP_TCK
COP_TDI
COP_TDO
COP_TMS
COP_TRST
COP_HRESET
COP_SRESET
COP_CKSTP_IN*
COP_CKSTP_OUT*
DEBUG0
DEBUG1
DEBUG2
DEBUG3
DEBUG4
DEBUG5
DEBUG6
DEBUG7
DEBUG8
COP_TCK
COP_TMS
COP_SRESET
COP_HRESET
COP_CKSTP_OUT*
COP_TDO
COP_TDI
R294
10K
R295
10K
+3.3V
R296
10K
R297
10K
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14 KEY
16
COPCONN
J8
R298
10K
R299
2K
+3.3V
R300
10K
COP_CKSTP_IN*
COP_TRST
Example Interface Schematics
Figure 24. MPC8540 COP Debug Connector
CompactPCI Reference Design, Rev. 1
27
Document Revision History
5
Document Revision History
Table 2 provides a revision history for this white paper.
Table 2. Document Revision History
Revision
Date
Change(s)
1
11/2004
Template update. Updated schematics related to DDR hook-up.
0
8/2003
Initial release.
CompactPCI Reference Design, Rev. 1
28
Freescale Semiconductor
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
29
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
CompactPCI Reference Design, Rev. 1
30
Freescale Semiconductor
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor
31
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