Errata sheet LPC5410x

ES_LPC5410x
Errata sheet LPC5410x
Rev. 2.1 — 17 December 2015
Errata sheet
Document information
Info
Content
Keywords
LPC54102J512UK49; LPC54102J256UK49; LPC54101J512UK49;
LPC54101J256UK49; LPC54102J512BD64; LPC54102J256BD64;
LPC54101J512BD64; LPC54101J256BD64
Abstract
LPC5410x errata
ES_LPC5410x
NXP Semiconductors
Errata sheet LPC5410x
Revision history
Rev
Date
2.1
20151217
2.0
1
Description
20150501
20141105
•
•
•
•
•
•
•
Power ROM API.1
Updated Section 1 “Product identification”. Added boot code revision.
Added RTC.1
Added ISP.1
Frequency.1
Updated product identification information
Initial version
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
ES_LPC5410X
Errata sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 17 December 2015
© NXP B.V. 2015. All rights reserved.
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1. Product identification
The ES_LPC5410x LQFP64 package has the following top-side marking:
• First line: LPC5410xJyyy
– x: 2 = dual core (M4, M0+), 1 = single core (M4)
– yyy: flash size
• Second line: BD64
• Third line: xxxxxxxxxxxx
• Fourth line: xxxyywwx[R]z
– yyww: Date code with yy = year and ww = week.
– xR = boot code version and device revision.
The ES_LPC5410x WLCSP49 package has the following top-side marking:
• First line: LPC5410x
– x: 2 = dual core (M4, M0+), 1 = single core (M4)
• Second line: JxxxUK49
– xxx: flash size
• Third line: xxxxxxxx
• Fourth line: xxxyyww
– yyww: Date code with yy = year and ww = week.
• Fifth line: xxxxx
• Sixth line: NXP x[R]z
– xR = boot code version and device revision.
This Errata Sheet covers the following revisions of the LPC5410x:
Table 1.
Device revision table
Revision identifier (R)
Revision description
‘1B’
Initial device revision with boot code version 17.1.
‘1C’
Second device revision with boot code version 17.1.
ES_LPC5410X
Errata sheet
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Rev. 2.1 — 17 December 2015
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2. Errata overview
Table 2.
Functional problems table
Functional
problems
Short description
RTC.1
The PDEN_32K_OSC bit gets cleared when the MCU ‘1B’, ‘1C’
wakes up from Deep power-down mode. This causes
the RTC oscillator to change from bypass mode to
crystal mode.
Section 3.1
ISP.1
ISP (In-System Programming) command for UID
(unique identification number) is not functional.
‘1B’, ‘1C’
Section 3.2
Frequency.1
The maximum operating system clock on the
LPC5410x device is limited to 96 MHz.
‘1B’
Section 3.3
POWER_API.1
The set-voltage ROM API call does not configure the ‘1B’, ‘1C’
internal regulator correctly for the desired operating
frequency.
Table 3.
Revision identifier
Detailed description
Section 3.4
AC/DC deviations table
AC/DC
deviations
Short description
Revision identifier
Detailed description
n/a
n/a
n/a
n/a
Table 4.
Errata notes
Note
Short description
Revision identifier
Detailed description
n/a
n/a
n/a
n/a
ES_LPC5410X
Errata sheet
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Rev. 2.1 — 17 December 2015
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NXP Semiconductors
Errata sheet LPC5410x
3. Functional problems detail
3.1 RTC.1: The RTC oscillator changes from bypass control mode to
crystal mode when waking up from Deep power-down mode.
Introduction:
On the LPC5410x, the low power 32 KHz RTC oscillator can be configured to run in
crystal oscillation mode or bypass control mode. In crystal oscillation mode, the RTC
oscillator is driven by an external 32 KHz crystal and in bypass control mode, the RTC
oscillator is driven by an external 32 KHz clock. Bypass control mode can be entered by
setting the PDEN_32K_OSC bit in the PDRUNCFG register (bit 24).
Problem:
The PDEN_32K_OSC bit gets cleared when the MCU wakes up from Deep power-down
mode. This causes the RTC oscillator to change from bypass mode to crystal mode.
Work-around:
If using deep power-down mode, the crystal oscillation mode should be used instead of
the bypass crystal mode. The bypass crystal mode can be used in active, sleep,
deep-sleep, and power-down modes.
3.2 ISP.1: ISP (In-System Programming) command for UID (unique
identification number) is not functional.
Introduction:
Each LPC5410x device contains a device serial number (four 32-bit words) for unique
identification. The ISP call (ReadUID) can be performed via the USART interface to read
the unique serial number where the word at the lowest address is sent first.
Problem:
On the LPC5410x, the read UID ISP command is not functional.
Work-around:
The unique serial number (four 32-bit words) can be directly read from address locations
0x01800100 to 0x0180010C.
ES_LPC5410X
Errata sheet
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Rev. 2.1 — 17 December 2015
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NXP Semiconductors
Errata sheet LPC5410x
3.3 Frequency.1: The maximum operating system clock on the LPC5410x
device is limited to 96 MHz.
Introduction:
The LPC5410x data sheet specifies that the LPC5410x device can operate at CPU
frequencies up to 100 MHz.
Problem:
To guard band for process, voltage, and temperature, the operating frequency is limited to
96 MHz.
Work-around:
None. Use CPU frequencies 96 MHz.
3.4 POWER_API.1: The set-voltage API ROM call does not configure the
internal regulator correctly for the desired operating frequency.
Introduction:
On the LPC5410x device, the following power API ROM calls are provided to configure
the system clock, and to manage the power consumption::
• set_pll: Configures the system PLL.
• set_voltage: Controls the device power consumption and the internal regulator for
desired operating frequency.
• power_mode_configure: Entry to and wake up from the low power modes.
Problem:
The set-voltage API ROM call does not configure the internal regulator correctly for the
desired operating frequency.
Work-around:
The power API library (power_lib) provided in NXP’s LPC5410x LPCOpen v3.xx software
platform must be used when calling the set_voltage API call. This library correctly
configures the internal regulator for the desired operating frequency.
ES_LPC5410X
Errata sheet
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Rev. 2.1 — 17 December 2015
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Errata sheet LPC5410x
4. AC/DC deviations detail
No known errata.
5. Errata notes
No known errata.
ES_LPC5410X
Errata sheet
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Rev. 2.1 — 17 December 2015
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6. Legal information
6.1
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
6.2
Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
ES_LPC5410X
Errata sheet
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
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customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
6.3
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 17 December 2015
© NXP B.V. 2015. All rights reserved.
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Errata sheet LPC5410x
7. Contents
1
2
3
3.1
3.2
3.3
3.4
4
5
6
6.1
6.2
6.3
7
Product identification . . . . . . . . . . . . . . . . . . . . 3
Errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional problems detail . . . . . . . . . . . . . . . . 5
RTC.1: The RTC oscillator changes from bypass
control mode to crystal mode when waking up
from Deep power-down mode. . . . . . . . . . . . . . 5
ISP.1: ISP (In-System Programming) command
for UID (unique identification number) is not
functional. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Frequency.1: The maximum operating system
clock on the LPC5410x device is limited to 96
MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
POWER_API.1: The set-voltage API ROM call
does not configure the internal regulator correctly
for the desired operating frequency. . . . . . . . . . 6
AC/DC deviations detail . . . . . . . . . . . . . . . . . . 7
Errata notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Legal information. . . . . . . . . . . . . . . . . . . . . . . . 8
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 December 2015
Document identifier: ES_LPC5410X