INTEGRATED CIRCUITS DATA SHEET SAA7706H Car radio Digital Signal Processor (DSP) Product specification File under Integrated Circuits, IC01 2001 Mar 05 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 1 FEATURES 8.13 8.14 8.14.1 1.1 1.2 Hardware Software 8.14.2 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.1.1 8.1.2 Analog front-end The realization of common mode input with AIC Realization of the auxiliary input with volume control Realization of the FM input control Pins VDACN1, VDACN2 and VDACP Pin VREFAD Supply of the analog inputs The signal audio path for input signals CD, TAPE, AUX, PHONE, NAV and AM Signal path for level information Signal path from FM_MPX input to IAC and stereo decoder Noise level Mono or stereo switching The automatic lock system DCS clock The Interference Absorption Circuit (IAC) General description The Filter Stream DAC (FSDAC) Interpolation filter Noise shaper Function of pin POM Power-off plop suppression Pin VREFDA for internal reference Supply of the filter stream DAC Clock circuit and oscillator Supply of the crystal oscillator The phase-locked loop circuit to generate the DSPs and other clocks Supply of the digital part (VDDD3V1 to VDDD3V4) CL_GEN, audio clock recovery block External control pins DSP1 DSP2 CONTENTS 8.1.3 8.1.4 8.1.5 8.1.6 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.5 8.6 8.6.1 8.7 8.7.1 8.7.2 8.7.3 8.7.4 8.7.5 8.7.6 8.8 8.8.1 8.9 8.10 8.11 8.12 8.12.1 8.12.2 2001 Mar 05 8.14.3 8.15 8.15.1 8.15.2 8.15.3 8.15.4 8.16 8.17 I2C-bus control (pins SCL and SDA) Digital serial inputs/outputs and SPDIF inputs General description digital serial audio inputs/outputs General description SPDIF inputs (SPDIF1 and SPDIF2) Digital data stream formats RDS demodulator (pins RDS_CLOCK and RDS_DATA) Clock and data recovery Timing of clock and data signals Buffering of RDS data Buffer interface DSP reset Test mode connections (pins TSCAN, RTCB and SHTCB) 9 I2C-BUS FORMAT 9.1 9.2 9.3 9.4 9.5 9.5.1 9.6 Addressing Slave address (pin A0) Write cycles Read cycles SAA7706H hardware registers SAA7706H DSPs registers I2C-bus memory map specification 10 LIMITING VALUES 11 THERMAL CHARACTERISTICS 12 CHARACTERISTICS 13 RDS AND I2S-BUS TIMING 14 I2C-BUS TIMING 15 SOFTWARE DESCRIPTION 16 APPLICATION DIAGRAM 17 PACKAGE OUTLINE 18 SOLDERING 18.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 18.2 18.3 18.4 18.5 2 SAA7706H 19 DATA SHEET STATUS 20 DEFINITIONS 21 DISCLAIMERS 22 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 1 SAA7706H FEATURES 1.1 Hardware • 5-bitstream 3rd-order sigma-delta Analog-to-Digital Converters (ADCs) with anti-aliasing broadband input filter • 1-bitstream 1st-order sigma-delta ADC with anti-aliasing broadband input filter • Easy applicable. • 4-bitstream Digital-to-Analog Converters (DACs) with 128-fold oversampling and noise shaping 1.2 • Integrated semi-digital filter; no external post filter required for DAC • Integrated 19 kHz MPX filter; de-emphasis and stereo detection • Dual media support: allowing separate front-seat and rear-seat signal sources and separate control • Electronic adjustments: FM or AM level, FM channel separation, Dolby®(1) level • Simultaneous radio and audio processing • Digital FM stereo decoder • Baseband audio processing (treble, bass, balance, fader and volume) • Digital FM interference suppression • Four channel 5-band parametric equalizer • RDS demodulation via separate ADC; with buffered output option • 9-bands mono audio spectrum analyzer Software • Improved FM weak signal processing • Extended beep functions with tone sequencer for phone rings • Two mono Common-Mode Rejection Ratio (CMRR) input stages for voice signals from phone and navigation inputs • Large volume jumps e-power interpolated to prevent zipper noise • Phone and navigation mixing at DAC front outputs • Dual media support; allowing separate front-seat and rear-seat signal sources and separate control • Two stereo CMRR input stages (CD-walkman and CD-changer etc.) • Dynamic loudness or bass boost • Analog single-ended TAPE and AUX input • Audio level monitor • Separate AM-left and AM-right inputs in the event of use of external AM stereo decoder • Tape equalization and Music Search System (MSS) detection for tape • One digital input: I2S-bus or LSB-justified format • Dolby-B tape noise reduction (at 44.1 kHz only) • Two digital inputs: SPDIF format • Dynamics compression available in all modes • Co-DSP support via I2S-bus or LSB-justified format • CD de-emphasis processing • Audio output short-circuit protected • Voice-over possibility for phone and navigation signals • • Improved AM signal processing I2C-bus controlled (including fast mode) • MOST bus interfacing (details in separate manual) • Digital AM CQUAM stereo decoder (not in all rom_codes available) • Phase-locked loop derives the internal clocks from one common fundamental crystal oscillator • Digital AM interference suppression • Combined AM/FM level input • Soft audio mute • Pin compatible with SAA7705 and SAA7708 • All digital inputs are tolerant of 5 V input levels • RDS update processing: pause detection, mute and signal-quality sensor-freeze • All analog inputs have high GSM immunity • General purpose tone generator • Low number of external components required (1) Dolby — Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111, USA, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby Laboratories Licensing Corporation. • −40 to +85 °C operating temperature range 2001 Mar 05 3 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) • Noise generator allows for frequency response measurements SAA7706H • RDS-demodulation • FM and AM weak signal processing (soft mute, sliding stereo and high cut) • Boot-up ROM for fast start-up • Signal level, noise and multipath detection for AM or FM signal quality information • Dolby-B tape noise reduction • AM co-channel and adjacent channel detection (not in all rom_codes available). • Audio controls for volume, balance, fader, tone and dynamics compression. 2 • CD de-emphasis function Some functions have been implemented in hardware (FM stereo decoder, RDS-demodulator and FM Interference Absorption Circuit (IAC) and are not freely programmable. APPLICATIONS • High-end car radio systems. 3 Digital audio signals from external sources with the Philips I2S-bus and the LSB-justified 16, 18, 20 and 24 bits format or SPDIF format are accepted. GENERAL DESCRIPTION The SAA7706H performs all the signal functions in front of the power amplifiers and behind the car radio tuner AM and FM outputs and the CD, tape and phone inputs. These functions are: The big advantage of this SAA7706H device is the ‘dual media support’; this enables independent front seat and rear seat audio sources and control. • Interference absorption • Stereo decoding for FM and AM (stereo) 4 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD operating supply voltage all VDD pins with respect to VSS 3 3.3 3.6 V IDDD supply current of the digital part DSP1 at 50 MHz; DSP2 at 62.9 MHz − 110 150 mA IDDA supply current of the analog part zero input and output signal − 40 60 mA Ptot total power dissipation DSP1 at 50 MHz; DSP2 at 62.9 MHz − 540 750 mW Vi(con)(max)(rms) maximum conversion input level (RMS value) THD < 1%; VOLFM = 00H 0.33 0.368 − V THD total harmonic distortion input signal 0.368 V (RMS) at 1 kHz; bandwidth = 19 kHz; VOLFM = 00H − −70 −65 dB − 0.03 0.056 % input signal at 1 kHz; 75 bandwidth = 40 kHz; 0 dB reference = 0.368 V (RMS); VOLFM = 00H 81 − dB THD < 1% 0.66 − V FM_MPX input S/N signal-to-noise ratio input stereo CD, TAPE, AUX and AM inputs Vi(con)(max)(rms) 2001 Mar 05 maximum conversion input level (RMS value) 4 0.6 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SYMBOL PARAMETER CONDITIONS SAA7706H MIN. TYP. MAX. UNIT THD total harmonic distortion input signal 0.55 V (RMS) at 1 kHz; bandwidth = 20 kHz − −85 −75 dB S/N signal-to-noise ratio input signal at 1 kHz; bandwidth = 20 kHz; 0 dB reference = 0.55 V (RMS) 85 90 − dB total harmonic distortion-plus-noise to at 0 dB signal ratio (measured with system at −60 dB; A-weighted one) − −90 −85 dB − −37 − dB signal-to-noise ratio (measured with system one) − 105 − dB − 11.2896 − FSDAC (THD + N)/S S/N code = 0; A-weighted Crystal oscillator fxtal 5 crystal frequency MHz ORDERING INFORMATION TYPE NUMBER SAA7706H 2001 Mar 05 PACKAGE NAME QFP80 DESCRIPTION plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm 5 VERSION SOT318-2 73 4 3 LEVELADC STEREO CMRR INPUTS 77 14 STEREO DECODER DSP2_INOUT1 DSP2_INOUT2 DSP2_INOUT3 DSP2_INOUT4 DSP1_IN1 DSP1_IN2 DSP1_OUT1 DSP1_OUT2 VDDD3V4 DIGITAL SOURCE SELECTOR 13 12 8 ANALOG SOURCE SELECTOR 69 68 35 A DIGITAL SOURCE SELECTORS MONO ADC3 30 DIGITAL I/O DSP2 B 33 31 32 80 RDS DEMODULATOR 79 XTAL OSCILLATOR POM FLV I2S-BUS SPDIF FRV RLV RRV VREFDA IIS_OUT1 IIS_OUT2 IIS_CLK IIS_WS IIS_IN1 IIS_IN2 I2C-BUS 20 LOOPO 61 43 44 45 21 60 59 62 65 63 64 26 29 27 28 24 25 57 58 56 42 DSP_RESET CD_WS CD_DATA CD_CLK SYSFS Product specification Fig.1 Block diagram. SAA7706H OSC_OUT MGT457 OSC_IN SEL_FR + 6 STEREO ADC2 VSS(OSC) FM_RDS 16 9 VDD(OSC) FM_MPX 66 7 RDS_CLOCK TAPE_R + 34 RDS_DATA TAPE_L QUAD FSDAC DSP1 67 TP1 AUX_R VDDD3V3 SIGNAL QUALITY SAA7706H STEREO ADC1 TSCAN AUX_L VDDD3V2 SIGNAL LEVEL 78 RTCB AM_R/AM VSSA2 72 70 SHTCB 6 AM_L/NAV VDDA2 PHONE VOLUME IAC VREFAD VDDD3V1 VSSD3V7 VSSD3V6 VSSD3V5 VSSD3V4 VSSD3V3 VSSD3V2 VSSD3V1 VDDD3V7 VDDD3V6 VDDD3V5 5 MONO CMRR INPUTS A0 CD_R_GND 10 SDA CD_(L)_GND 71 SCL CD_R 41 40 39 38 19 18 15 17 11 SPDIF1 CD_L 48 51 52 55 SPDIF2 LEVEL VSSA1 VDDA1 NAV_GND 49 50 53 54 47 37 23 Philips Semiconductors PHONE_GND 46 36 22 Car radio Digital Signal Processor (DSP) PHONE 76 75 2 BLOCK DIAGRAM VDACN1 74 1 6 VDACP ook, full pagewidth 2001 Mar 05 VDACN2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 7 SAA7706H PINNING SYMBOL PIN PIN TYPE DESCRIPTION VDACP 1 apio positive reference voltage ADC1, ADC2, ADC3 and level-ADC VDACN1 2 apio ground reference voltage ADC1 LEVEL 3 apio gsmcap LEVEL input pin; via this pin the level of the FM signal or level of the AM signal is fed to the DSP1; the level information is used in the DSP1 for dynamic signal processing NAV_GND 4 apio gsmcap common mode reference input pin of the navigation signal (pin AM_L/NAV) POM 5 apio power-on mute of the QFSDAC; timing is determined by an external capacitor RRV 6 apio rear; right audio output of the QFSDAC AUX_L 7 apio left channel of analog AUX input AUX_R 8 apio right channel of analog AUX input RLV 9 apio rear; left audio output of the QFSDAC VSSA2 10 vssco ground supply analog part of the QFSDAC and SPDIF bitslicer VDDA2 11 vddco positive supply analog part of the QFSDAC and SPDIF bitslicer VREFDA 12 apio voltage reference of the analog part of QFSDAC FRV 13 apio front; right audio output of the QFSDAC CD_R_GND 14 apio common-mode reference input pin for analog CD_R or TAPE_R in the event of separated ground reference pins for left and right are used DSP2_INOUT2 15 bpts5thdt5v flag input/output 2 of the DSP2-core (DSP2-flag) I2C-bus configurable FLV 16 apio front; left audio voltage output of the QFSDAC DSP2_INOUT1 17 bpts5thdt5v flag input/output 1 of the DSP2-core (DSP2-flag) I2C-bus configurable DSP2_INOUT3 18 bpts5thdt5v flag input/output 3 of the DSP2-core (DSP2-flag) I2C-bus configurable DSP2_INOUT4 19 bpts5thdt5v flag input/output 4 of the DSP2-core (DSP2-flag) I2C-bus configurable LOOPO 20 bpts5tht5v SYSCLK output (256fs) TP1 21 ipthdt5v for test purpose only; this pin may be left open or connected to ground VDDD3V7 22 vdde positive supply (peripheral cells only) VSSD3V7 23 vsse ground supply (peripheral cells only) SPDIF2 24 apio SPDIF input 2; can be selected instead of SPDIF1 via I2C-bus bit SPDIF1 25 apio SPDIF input 1; can be selected instead of SPDIF2 via I2C-bus bit SYSFS 26 ipthdt5v system fs clock input CD_WS 27 ipthdt5v digital CD-source word select input; I2S-bus or LSB-justified format CD_DATA 28 bpts10thdt5v digital CD-source left-right data input; I2S-bus or LSB-justified format CD_CLK 29 ipthdt5v digital CD-source clock input I2S-bus or LSB-justified format IIS_CLK 30 ots10ct5v clock output for external I2S-bus receiver; for example headphone or subwoofer IIS_IN1 31 ipthdt5v data 1 input for external I2S-bus transmitter; e.g. audio co-processor IIS_IN2 32 ipthdt5v data 2 input for external I2S-bus transmitter; e.g. audio co-processor IIS_WS 33 ots10ct5v word select output for external I2S-bus receiver; for example headphone or subwoofer IIS_OUT1 34 ots10ct5v data 1 output for external I2S-bus receiver or co-processor IIS_OUT2 35 ots10ct5v data 2 output for external I2S-bus receiver or co-processor 2001 Mar 05 7 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SYMBOL VDDD3V6 PIN 36 PIN TYPE SAA7706H DESCRIPTION vdde positive supply (peripheral cells only) VSSD3V6 37 vsse ground supply (peripheral cells only) DSP1_IN1 38 bpts10thdt5v flag input 1 of the DSP1-core DSP1_IN2 39 bpts10thdt5v flag input 2 of the DSP1-core DSP1_OUT1 40 op4mc flag output 1 of the DSP1-core DSP1_OUT2 41 op4mc flag output 2 of the DSP1-core DSP_RESET 42 iptut5v general reset of chip (active LOW) RTCB 43 ipthdt5v asynchronous reset test control block; connect to ground (internal pull-down) SHTCB 44 ipthdt5v shift clock test control block (internal pull-down) TSCAN 45 ipthdt5v scan control active high (internal pull-down) VDDD3V5 46 vdde positive supply (peripheral cells only) VSSD3V5 47 vsse ground supply (peripheral cells only) VDDD3V1 48 vddi positive supply (core only) VSSD3V1 49 vssis ground supply (core only) VSSD3V2 50 vssco ground supply (core only) VDDD3V2 51 vddco positive supply (core only) VDDD3V3 52 vddco positive supply (core only) VSSD3V3 53 vssco ground supply (core only) VSSD3V4 54 vssis ground supply (core only) VDDD3V4 55 vddi positive supply (core only) A0 56 ipthdt5v slave sub-address I2C-bus selection or serial data input test control block SCL 57 iptht5v serial clock input I2C-bus SDA 58 iic400kt5v serial data input/output I2C-bus RDS_CLOCK 59 bpts10tht5v radio data system bit clock output or RDS external clock input I2C-bus bit controlled RDS_DATA 60 ops10c radio data system data output SEL_FR 61 iptht5v AD input selection switch to enable high ohmic FM_MPX input at fast tuner search on FM_RDS input VSS(OSC) 62 vssco ground supply (crystal oscillator only) OSC_IN 63 apio crystal oscillator input OSC_OUT 64 apio crystal oscillator output VDD(OSC) 65 vddco positive supply (crystal oscillator only) AM_R/AM 66 apio gsmcap right channel AM audio frequency or AM input in the event of mono; analog input pin AM_L/NAV 67 apio gsmcap left channel AM audio frequency or input of common mode navigation signal; analog input pin TAPE_R 68 apio gsmcap right channel of analog TAPE input TAPE_L 69 apio gsmcap left channel of analog TAPE input CD_R 70 apio gsmcap right channel of analog CD input PHONE 71 apio gsmcap common mode PHONE signal, analog input pin CD_L 72 apio gsmcap left channel of analog CD input 2001 Mar 05 8 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SYMBOL SAA7706H PIN PIN TYPE DESCRIPTION PHONE_GND 73 apio gsmcap common mode reference input pin of the PHONE signal VDDA1 74 vddco positive supply analog (ADC1, ADC2, ADC3 and level-ADC only) VSSA1 75 vssco ground supply analog (ADC3 and level-ADC only) VDACN2 76 apio ground reference voltage (ADC2) CD_(L)_GND 77 apio gsmcap common mode reference input pin for analog CD or TAPE or in the event of separated ground reference pins used for CD_L or TAPE_L VREFAD 78 apio common mode reference voltage ADC1, ADC2, ADC3 and level-ADC FM_RDS 79 apio gsmcap FM RDS signal; analog input pin FM_MPX 80 apio gsmcap FM multiplex signal; analog input pin Table 1 Brief explanation of used pin types PIN TYPE EXPLANATION apio 3-state I/O analog; I/O pad cell; actually pin type vddco apio gsmcap 3-state I/O analog; I/O pad cell; actually pin type vddco with high GSM immunity bpts5thdt5v 43 MHz bidirectional pad; push-pull input; 3-state output; 5 ns slew rate control; TTL; hysteresis; pull-down; 5 V tolerant bpts10tht5v 21 MHz bidirectional pad; push-pull input; 3-state output; 10 ns slew rate control; TTL; hysteresis; 5 V tolerant bpts10thdt5v 21 MHz bidirectional pad; push-pull input; 3-state output; 10 ns slew rate control; TTL; hysteresis; pull-down; 5 V tolerant iic400kt5v I2C-bus pad; 400 kHz I2C-bus specification; TTL; 5 V tolerant iptht5v input pad buffer; TTL; hysteresis; 5 V tolerant ipthdt5v input pad buffer; TTL; hysteresis; pull-down; 5 V tolerant iptut5v input pad buffer; TTL; pull-up; 5 V tolerant op4mc output pad buffer; 4 mA output drive; CMOS; slew rate control; 50 MHz ots10ct5v output pad buffer; 3-state, 10 ns slew rate control; CMOS; 5 V tolerant ops10c output pad buffer; 4 mA output drive; CMOS; slew rate control; 21 MHz vdde VDD supply peripheral only vsse VSS supply peripheral only vddco VDD supply to core only vssco VSS supply to core only (vssco does not connect the substrate) vddi VDD supply to core and peripheral vssis VSS supply to core and peripheral; with substrate connection 2001 Mar 05 9 Philips Semiconductors Product specification 65 VDD(OSC) 66 AM_R/AM 67 AM_L/NAV 68 TAPE_R 69 TAPE_L 70 CD_R SAA7706H 71 PHONE 72 CD_L 73 PHONE_GND 74 VDDA1 75 VSSA1 76 VDACN2 78 VREFAD 79 FM_RDS 80 FM_MPX handbook, full pagewidth 77 CD_(L)_GND Car radio Digital Signal Processor (DSP) VDACP 1 64 OSC_OUT VDACN1 2 63 OSC_IN LEVEL 3 62 VSS(OSC) NAV_GND 4 61 SEL_FR POM 5 60 RDS_DATA RRV 6 59 RDS_CLOCK AUX_L 7 58 SDA AUX_R 8 57 SCL RLV 9 56 A0 VSSA2 10 55 VDDD3V4 VDDA2 11 54 VSSD3V4 53 VSSD3V3 VREFDA 12 SAA7706H FRV 13 52 VDDD3V3 CD_R_GND 14 51 VDDD3V2 DSP2_INOUT2 15 50 VSSD3V2 FLV 16 49 VSSD3V1 DSP2_INOUT1 17 48 VDDD3V1 DSP2_INOUT3 18 47 VSSD3V5 DSP2_INOUT4 19 46 VDDD3V5 LOOPO 20 45 TSCAN TP1 21 44 SHTCB Fig.2 Pinning diagram. 2001 Mar 05 10 DSP1_OUT1 40 DSP1_IN2 39 DSP1_IN1 38 VSSD3V6 37 VDDD3V6 36 IIS_OUT2 35 IIS_OUT1 34 IIS_WS 33 IIS_IN2 32 IIS_IN1 31 IIS_CLK 30 41 DSP1_OUT2 CD_CLK 29 SPDIF2 24 CD_DATA 28 42 DSP_RESET CD_WS 27 VSSD3V7 23 SYSFS 26 43 RTCB SPDIF1 25 VDDD3V7 22 MGT458 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 8 8.1 FUNCTIONAL DESCRIPTION The PHONE and NAV inputs have their own CMRR input stage and can be redirected to ADC1/2 via the Audio Input Control (AIC). For pin compatibility with SAA7704, SAA7705 and SAA7708 the AM is combined with the NAV input. It is also possible to directly mix PHONE or NAV (controlled with MIXC) with the front FSDAC channels after volume control. The FM inputs (FM_MPX/FM_RDS) can be selected with external pin SEL_FR. The FM and RDS input sensitivity can be adjusted with VOLFM and VOLRDS via I2C-bus. Analog front-end The analog front-end consists of two identical sigma-delta stereo ADCs (ADC1 and ADC2) with several input control blocks for handling common mode signals and acting as input selector. A mono version (ADC3) is added for handling RDS signals. Also a first-order sigma-delta ADC for tuner level information is incorporated. The switches S1 and S2 select (see Fig.3) between the FM_MPX/FM_RDS and the CD, TAPE, AUX, AM, PHONE and NAV connection to ADC1 and ADC2. The inputs CD, TAPE, AUX, AM, PHONE and NAV can be selected with the audio input controls (AIC1/2). The ground reference (G0 and G1) can be selected to be able to handle common mode signals for CD or TAPE. The ground reference G0 is connected to an external pin and G1 is internally referenced (see Fig.4). 2001 Mar 05 SAA7706H 11 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SAA7706H handbook, full pagewidth CLKLEVEL LEVEL 3 LEVEL-ADC LEVELO VOLRDS(5:0) SEL_FR FM_RDS FM_MPX CD_L TAPE_L S3 61 79 80 1 0 MUX 72 69 GNDC1 AUX_L CD_R TAPE_R AM_R/AM AUX_R CD_(L)_GND VREFAD CD_R_GND 7 VOLFM(5:0) x00 AIC1(2:0) GNDRC1 x01 x10 MUX 011 1 111 0 MUX 0 1 MUX x00 x01 x10 MUX 011 111 70 68 66 8 77 78 14 GNDC2 0 1 MUX PHONE PHONE_GND AM_L/NAV NAV_GND 71 73 CMRR 67 4 CMRR ADF3 S1 0 1 MUX 0 1 MUX LEFT1 STEREO ADC1 ADF1_a RIGHT1 fmhsnr_adc1 x00 AIC2(2:0) GNDRC2 x01 x10 MUX 1 011 0 111 MUX x00 x01 x10 MUX 011 111 RDS MONO (RDS) ADC3 CLKADC2 0 1 MUX MIDREF 0 1 MUX CLKADC2 0 1 MUX charge_pump S2 0 1 MUX 0 1 MUX LEFT2 STEREO ADC2 ADF1_b RIGHT2 CLKADC2 fmhsnr_adc2 MIXC VOLMIX(5:2) 1 0 MUX MIX VOLMIX(4:0) located in FIRDAC MGT459 Fig.3 Analog front-end switch diagram. 2001 Mar 05 12 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 8.1.1 THE REALIZATION OF COMMON MODE INPUT WITH AIC SAA7706H In Fig.4 the CD input is selected. In this situation both signal lines going to S1/2 in front of the ADC will contain the common mode signal. The ADC itself will suppress this common mode signal with a high rejection ratio. The inputs CD_L and CD_R in this example are connected via an external resistor tap of 82 kΩ and 100 kΩ to be able to handle larger input signals. The 100 kΩ resistors are needed to provide a DC biasing of the operational amplifiers OA1 and OA2. The 1 MΩ resistor provides DC biasing of OA3 and OA4. If no external resistor tap is needed the resistors of 100 kΩ and 1 MΩ still have to provide DC biasing. Only the 82 kΩ resistor can be removed. The impedance level in combination with parasitic capacitance at input CD_L or CD_R determines for a great deal the achievable common rejection ratio. A high common mode rejection ratio can be created by the use of the ground return pin. Pin CD_(L)_GND can be used in the case that the left and right channel have one ground return line. CD_(L)_GND and CD_R_GND can be used for separated left and right ground return lines. The ground return lines can be connected via the switch GNDC1/2 and GNDRC1/2 (see Fig.4) to the plus input of the second operational amplifier in the signal path. The signal of which a high common mode rejection ratio is required has a signal and a common signal as input. The common signal is connected to the CD_(L)_GND and/or CD_R_GND input. The actual input can be selected with audio input control AIC1/2(1:0). handbook, full pagewidth 10 kΩ 82 kΩ CD_L LEFT 72 00 01 10 MUX 11 10 kΩ to MUX S1/2 10 kΩ OA1 OA3 100 kΩ AIC1/2(1:0) G1 CD_(L)_GND GROUND LEFT from CD-player analog 77 G0 1 MΩ GNDC1/2 VREFAD 78 GNDRC1/2 MIDREF 1 MΩ CD_R_GND 14 GROUND RIGHT 82 kΩ RIGHT 10 kΩ 10 kΩ 100 kΩ CD_R 70 to MUX S1/2 00 01 10 MUX 11 10 kΩ OA2 OA4 MGT460 off-chip on-chip Fig.4 Example of the use of common mode analog input in combination with input resistor tap. 2001 Mar 05 13 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SAA7706H handbook, full pagewidth 0 dB (full-scale) 660 mV (RMS) Audio ADC GAIN AUDIO DIGITAL FILTER 5 dB GAIN DSP2 STEREO DECODER 3 dB GAIN DSP1 −2 dB (full-scale) MGT461 Fig.5 Audio gain through ADC and digital filter path to DSP. 8.1.2 REALIZATION OF THE AUXILIARY INPUT WITH VOLUME 8.1.3 CONTROL The gain of the circuit has a maximum of 2.26 (7.08 dB). This results in an input level of 368 mV for full-scale, which means 0 dB (full-scale) at the DSP1 input via the stereo decoder (see Fig.6). The gain can be reduced in steps of 1.5 dB. When the gain is set to −3.4 dB the input level becomes 1229 mV for full-scale. This setting accounts for the 200 mV (RMS) input sensitivity at 22.5 kHz sweep and a saturation of the input at 138 kHz sweep. A differential input with volume control for mixing to the front left or front right of both DAC outputs is provided. The inputs consist of a PHONE and NAV input. Both are accompanied with their ground return lines. After selection of PHONE or NAV the volume can be changed from about +18 to −22.5 dB in 27 steps and mute (MIX output). This signal can be added to the left and/or right front DAC channels. RDS update: for RDS update the fast access pin SEL_FR must be made HIGH. In that case the FM_RDS signal also goes through the path that was set for FM_MPX. In this situation the signal must be obtained via the FM_RDS input and a noise sample can be retrieved. The input FM_MPX gets high-ohmic. Charging of the coupling capacitor connected to pin FM_MPX is no longer possible. The output signals of both input circuits can also be switched to ADC1 and/or ADC2, depending on the settings of audio input control 1 (AIC1) and audio input control 2 (AIC2), without volume control (see Fig.3). handbook, full pagewidth REALIZATION OF THE FM INPUT CONTROL 831 mV (RMS) FM GAIN AUDIO DIGITAL FILTER 5 dB GAIN ADC DSP2 0 dB (full-scale) STEREO DECODER 3 dB GAIN DSP1 MGT462 Fig.6 FM gain path through stereo decoder to DSP1. 2001 Mar 05 14 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 8.1.4 PINS VDACN1, VDACN2 AND VDACP 8.1.6 SAA7706H SUPPLY OF THE ANALOG INPUTS These pins are used as negative and positive reference for the ADC1, 2, 3 and the level-ADC. They have to be directly connected to the VSSA1 and filtered VDDA1 for optimal performance (see Figs 25 and 26). The analog input circuit has separate power supply connections to allow maximum filtering. These pins are VSSA1 for the analog ground and VDDA1 for the analog power supply. 8.1.5 8.2 PIN VREFAD Via this pin the midref voltage of the ADCs is filtered. This midref voltage is used as half supply voltage reference of the ADCs. External capacitors (connected to VSSA1) prevent crosstalk between switch cap DACs of the ADCs and buffers and improves the power supply rejection ratio of all components. This pin is also used in the application as reference for the inputs TAPE and CD (see Fig.4). The voltage on pin VREFAD is determent by the voltage on pins VDACP and VDACN1 or VDACN2 and is found as: V VDACP – V VDACN1,2 V VREFAD = --------------------------------------------------2 The signal audio path for input signals CD, TAPE, AUX, PHONE, NAV and AM The left and right channels are converted and down-sampled by the ADF1_a, ADF1_b. This data stream is converted into a serial format and fed to the DSP1 and DSP2 source selectors. In Figs 7 and 8 the overall and detailed frequency response curves of the analog-to-digital audio decimation path based on a 44.1 kHz sample frequency are shown. MGT463 0 handbook, full pagewidth α (dB) −50 −100 −150 −200 −250 Fig.7 0 100 200 300 400 f (kHz) 500 Overall frequency response curve analog-to-digital audio path decimation based on a 44.1 kHz sample frequency. 2001 Mar 05 15 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) α SAA7706H MGT464 20 handbook, full pagewidth (dB) 0 −20 −40 −60 −80 −100 −120 −140 Fig.8 0 10 20 30 40 f (kHz) 50 Detailed frequency response curve analog-to-digital audio path decimation based on a 44.1 kHz sample frequency. 2001 Mar 05 16 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 8.3 Signal path for level information SAA7706H The tolerance on the gain is less than 2%. The MSB is always logic 0 to represent a positive level. Input level span can be increased by an external resistor tap. The high input impedance of the level-ADC makes this possible. For FM weak signal processing, for AM and FM purposes (absolute level and multipath) a level input is implemented (pin LEVEL). In the event of radio reception the clocking of the filters and the level-ADC is based on a 38 kHz sampling frequency. A DC input signal is converted by a bitstream sigma-delta ADC followed by a decimation filter. The decimation filter reduces in the event of an 38 kHz based clocking regime the bandwidth of the incoming signal to a frequency range of 0 to 29 kHz with a resulting fs = 76 kHz. The response curve is given in Fig.9. The input signal has to be obtained from a radio part. The tuner must deliver the level information of either AM or FM to pin LEVEL. The level information is sub-sampled by the DSP1 to obtain a field strength and a multipath indication. These values are stored in the coefficient or data RAM. Via the I2C-bus they can be read and used in other microcontroller programs. The input signal for level must be in the range 0 to 3.3 V (VVDACP − VVDACN). The 9-bit level-ADC converts this input voltage in steps with a resolution better than at least 14 mV over the 3.3 V range. MGT465 10 handbook, full pagewidth α (dB) 0 −10 −20 −30 −40 −50 −60 0 10 20 30 40 50 60 Fig.9 Frequency response level-ADC and decimal filter. 2001 Mar 05 17 70 f (kHz) 80 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 8.4 Signal path from FM_MPX input to IAC and stereo decoder SAA7706H After selection of one of the ADCs, the FM_MPX path it is followed by the IAC and the FM stereo decoder. One of the two MPX filter outputs contains the multiplex signal with a frequency range of 0 to 60 kHz. The overall low-pass frequency response of the decimation filters is shown in Fig.10. The FM_MPX signal is after selection available at one of three ADCs (ADC1, 2 and 3). The multiplex FM signal is converted to the digital domain in ADC1, 2 and 3 through a bitstream ADC. Improved performance for FM stereo can be achieved by means of adapting the noise shaper curve of the ADC to a higher bandwidth. The first decimation takes place in two down-sample filters. These decimation filters are switched by means of the I2C-bus bit wide_narrow in the wide or narrow band position. In the event of FM reception it must be in the narrow position. MGT466 0 handbook,αfull pagewidth (dB) −20 −40 −60 −80 −100 −120 −140 0 100 200 300 400 Fig.10 Overall frequency response of ADC1, ADC2 and decimation filters. 2001 Mar 05 18 f (kHz) 500 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) The outputs of the stereo decoder to the DSP1, which are all running on a sample frequency of 38 kHz are: SAA7706H Normally the FM_MPX input and the FM_RDS input have the same source. If the FM input contains a stereo radio channel, the pilot information is switched to the Digitally Controlled Sampling (DCS) clock generation and the DCS clock is locked to the 256 × 38 kHz of the pilot. In this case this locked frequency is also used for the RDS path ensuring the best possible performance. • Pilot presence indication: pilot-I. This 1-bit signal is LOW for a pilot frequency deviation <4 kHz and HIGH for a pilot frequency deviation >4 kHz and locked on a pilot tone. • ‘Left’ and ‘right’ FM reception stereo signal: this is the 18-bit output of the stereo decoder after the matrix decoding. Except from the above mentioned theoretical response also the non-flat frequency response of the ADC has to be compensated in the DSP1 program. • Noise level (see also Section 8.4.1): which is retrieved from the high-pass output of the MPX filter. The noise level is detected and filtered in the DSP1 and is used to optimize the FM weak signal processing. MGT467 handbook, full pagewidth 0 α (dB) −20 −40 −60 −80 −100 0 10 20 30 40 50 60 f (kHz) Fig.11 Transfer of MPX signal at the output of the stereo decoder. 2001 Mar 05 19 70 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 8.4.1 NOISE LEVEL SAA7706H The resulting noise information is rectified and has a word length of 10 bits. This means that the lowest and/or the highest possible level is not used. The noise level can be detected and filtered in the DSP1-core and be used to optimize the FM weak signal processing. The transfer curves of both filters before decimation are shown in Fig.12. The high-pass 1 (HP1 or narrow band noise level filter) output of the second MPX decimation filter in a band from 60 kHz to 120 kHz is detected with an envelope detector and decimated to a frequency of 38 kHz. The response time of the detector is 100 µs. Another option is the high-pass 2 (HP2 or wide band noise level filter). This output of the first MPX decimation filter is in a band from 60 to 240 kHz. It has the same properties and is also decimated to the same 38 kHz. Which of the signals is used (HP1 or HP2) is determined by the I2C-bus bit sel_nsdec. MGT468 handbook, full pagewidth 0 α (dB) (1) −20 (2) −40 −60 −80 −100 −120 −140 0 50 100 150 200 250 f (kHz) 300 (1) Noise with wide band digital filter. (2) Noise with small band digital filter. Fig.12 Frequency response of noise level before decimation. 8.4.2 MONO OR STEREO SWITCHING 8.4.3 The VCO of the DCS block will be at 19 kHz ±2 Hz exact based in the event of no-pilot FM_MPX reception or in the event of only RDS reception. In the event of stereo reception the phase error is zero for a pilot tone with a frequency of exactly 19 kHz. The DCS block uses a sample rate converter to derive from the XTAL clock, via a PLL, a 512 multiple of 19 kHz (9.728 MHz). In the event of mono reception the DCS circuit generates a preset frequency of n × 19 kHz ±2 Hz. In the event of stereo reception the frequency is exactly n × 19 kHz (DCS locked to N × pilot tone). The detection of the pilot and the stereo indication is done in the DSP program. 2001 Mar 05 THE AUTOMATIC LOCK SYSTEM 20 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 8.5 The characteristics of both IAC detectors can be adapted to the properties of different FM front-ends by means of the predefined coefficients in the IAC control registers. The values can be changed via the I2C-bus. Both IAC detectors can be switched on or off independently of each other. Both IAC detectors can mute the MPX signal independently of each other. DCS clock In radio mode the stereo decoder, the ADC3 and RDS demodulator, the ADC1 or ADC2 and the level decimation filters have to run synchronously to the 19 kHz pilot. Therefore a clock signal with a controlled frequency of a multiple of 19 kHz (9.728 MHz = 512 × 19 kHz) is needed. In the SAA7706H the patented method of non-equidistant digitally controlled sampling DCS clock has been implemented. By a special dividing mechanism a frequency of 9.728 MHz from the PLL2 clock frequency of >40 MHz is generated. The dividing can be changed by means of I2C-bus bits to cope with the different input frequencies of the DCS block. A third IAC function is the dynamic IAC circuit. This block is intended to switch off the IAC completely the moment the MPX signal has a too high frequency deviation which in the event of small IF filters can result in AM modulation. This AM modulation could be interpreted by the IAC circuitry as interference caused by the car’s engine. The DCS system is controlled by up or down information from the stereo decoder. In the event of mono transmissions or 44.1 kHz ADC1 or ADC2 usage the DCS clock is still controlled by the stereo decoder loop. The output keeps the DCS free running on a multiple frequency of 19 kHz ±2 Hz if the correct clock setting is applied. In 8.7 8.6.1 The Interference Absorption Circuit (IAC) GENERAL DESCRIPTION The output voltage of the FSDAC scales proportionally with the power supply voltage. The IAC detects and suppresses ignition interference. This hardware IAC is a modified, digitized and extended version of the analog circuit which is in use for many years already. 8.7.1 INTERPOLATION FILTER The digital filter interpolates from 1 to 64fs by means of a cascade of a recursive filter and an FIR filter. The IAC consists of an MPX mute function switched by mute pulses from ignition interference pulse detectors. The input signal of a second IAC detection circuit is the FM level signal (the output of the level-ADC). This detector performs optimally in lower antenna voltage circumstances. It is therefore complementary to the first detector. Table 2 Digital interpolation filter characteristics ITEM The input signal of a first IAC detection circuit is the output signal of one of the down-sample paths coming from ADC1 or ADC2. This interference detector analyses the high-frequency contents of the MPX signal. The discrimination between interference pulses and other signals is performed by a special Philips patented fuzzy logic such as algorithm and is based on probability calculations. This detector performs optimally in higher antenna voltage circumstances. On detection of ignition interference, this logic will send appropriate pulses to the MPX mute switch. 2001 Mar 05 The Filter Stream DAC (FSDAC) The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. tape/cd of either 38 or 44.1 kHz and AM mode the DCS clock always has to be put in preset mode with a bit in the I2C-bus memory map definitions. 8.6 SAA7706H CONDITIONS VALUE (dB) Pass band ripple 0 − 0.45fs ±0.03 Stop band >0.55fs −50 Dynamic range 0 − 0.45fs 116.5 Gain DC −3.5 8.7.2 NOISE SHAPER The 5th-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. 21 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 8.7.3 In order to obtain the lowest noise and to have the best ripple rejection, a filter capacitor has to be added between this pin and ground, preferably close to the analog pin VSSA2. FUNCTION OF PIN POM With pin POM it is possible to switch off the reference current of the DAC. The capacitor on pin POM determines the time after which this current has a soft switch-on. So at power-on the current audio signal outputs are always muted. The loading of the external capacitor is done in two stages via two different current sources. The loading starts at a current level that is lower than the current loading after the voltage on pin POM has past a particular level. This results in an almost dB-linear behaviour. This must prevent ‘plop’ effects during power on or off. 8.7.4 8.7.6 SUPPLY OF THE FILTER STREAM DAC The entire analog circuitry of the DACs and the operational amplifiers are supplied by 2 supply pins: VDDA2 and VSSA2. VDDA2 must have sufficient decoupling to prevent total harmonic distortion degradation and to ensure a good power supply rejection ratio. The digital part of the DAC is fully supplied from the chip core supply. POWER-OFF PLOP SUPPRESSION 8.8 To avoid plops in a power amplifier, the supply voltage of the analog part of the DAC and the rest of the chip can be fed from a separate power supply of 3.3 V. A capacitor connected to this power supply enables to provide power to the analog part at the moment the digital voltage is switching off fast. In this event the output voltage will decrease gradually allowing the power amplifier some extra time to switch off without audible plops. 8.7.5 SAA7706H Clock circuit and oscillator The chip has an on-chip crystal clock oscillator. The block diagram of this Pierce oscillator is shown in Fig.13. The active element needed to compensate for the loss resistance of the crystal is the block Gm. This block is placed between the external pins OSC_IN and OSC_OUT. The gain of the oscillator is internally controlled by the AGC block. A sine wave with a peak-to-peak voltage close to the oscillator power supply voltage is generated. The AGC block prevents clipping of the sine wave and therefore the higher harmonics are as low as possible. At the same time the voltage of the sine wave is as high as possible which reduces the jitter going from sine wave to the clock signal. PIN VREFDA FOR INTERNAL REFERENCE With two internal resistors half the supply voltage VDDA2 is obtained and used as an internal reference. This reference voltage is used as DC voltage for the output operational amplifiers and as reference for the DAC. handbook, full pagewidth 0.5VDD(OSC) Gm AGC clock to circuit Rbias on-chip 63 64 65 62 OSC_IN OSC_OUT VDD(OSC) VSS(OSC) off-chip C2 C1 MGT469 Fig.13 Block diagram oscillator circuit. 2001 Mar 05 22 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) handbook, full pagewidth SAA7706H 0.5VDD(OSC) Gm AGC clock to circuit Rbias on-chip 63 64 65 62 OSC_IN OSC_OUT VDD(OSC) VSS(OSC) off-chip C3 C2 C1 MGT470 slave input 3.3 V(p-p) Fig.14 Block diagram of the oscillator in slave mode. 8.8.1 • Although a multiple of the frequency of the used crystal of 11.2896 MHz falls within the FM reception band, this will not disturb the reception because the relatively low frequency crystal is driven in a controlled way and the sine wave of the crystal has in the FM reception band only very minor harmonics. SUPPLY OF THE CRYSTAL OSCILLATOR The power supply connections of the oscillator are separated from the other supply lines. This is done to minimize the feedback from the ground bounce of the chip to the oscillator circuit. Pin VSS(OSC) is used as ground supply and pin VDD(OSC) as positive supply. A series resistor plus capacitance is required for proper operating on pin VDD(OSC), see Figs 25 and 26. See also important remark in Section 8.10. 8.9 8.10 The supply voltage on pins VDDD3V1 to VDDD3V4 must be for at least 10 ms earlier active than the supply voltage applied to pin VDD(OSC). The phase-locked loop circuit to generate the DSPs and other clocks 8.11 There are several reasons why a PLL circuit is used to generate the clock for the DSPs: CL_GEN, audio clock recovery block When an external I2S-bus or SPDIF source is connected, the FSDAC circuitry needs an 256fs related clock. This clock is recovered from either the incoming WS of the digital serial input or the WS derived from the SPDIF1/SPDIF2 input. There is also a possibility to provide the chip with an external clock, in that case it must be a 256fs clock with a fixed phase relation to the source. • The PLL makes it possible to switch in the rare cases that tuning on a multiple of the DSP clock frequency occurs to a slightly higher frequency for the clock of the DSP. In this way an undisturbed reception with respect to the DSP clock frequency is possible. • Crystals for the crystal oscillator in the range of twice the required DSP clock frequency, so approximately 100 MHz, are always third overtone crystals and must also be manufactured on customer demand. This makes these crystals expensive. The PLL1 enables the use of a crystal running in the fundamental mode and also a general available crystal can be chosen. For this circuit a 256 × 44.1 kHz = 11.2896 MHz crystal is chosen. This type of crystal is widely used. 2001 Mar 05 Supply of the digital part (VDDD3V1 to VDDD3V4) 23 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 8.12 8.12.1 External control pins 8.13 DSP1 SAA7706H I2C-bus control (pins SCL and SDA) General information about the I2C-bus can be found in “The I2C-bus and how to use it”. This document can be ordered using the code 9398 393 40011. For the external control of the SAA7706H device a fast I2C-bus is implemented. This is a 400 kHz bus which is downward-compatible with the standard 100 kHz bus. There are two different types of control instructions: For external control two input pins have been implemented. The status of these pins can be changed by applying a logic level. The status is saved in the DSP1 status register. The function of each pin depends on the DSP1 program. To control external devices two output pins are implemented. The status of these pins is controlled by the DSP program. • Instructions to control the DSP program, programming the coefficient RAM and reading the values of parameters (level, multipath etc.) Function of these ‘control pins’ can be found in a separate manual and is rom_code dependent. • Instructions controlling the data flow; such as source selection, IAC control and clock speed. 8.12.2 The detailed description of the I2C-bus and the description of the different bits in the memory map is given in Chapter 9. DSP2 For external control four configurable I/O pins have been implemented. Via the I2C-bus these four pins can be independently configured as input or output. The status of these pins can be changed by applying a logic level (input mode). The status is saved in the DSP2 status register. The function of each pin depends on the I2C-bus setting and DSP2 program. Function of these ‘control pins’ can be found in a separate manual and is rom_code dependent. 2001 Mar 05 24 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 8.14 8.14.1 This chip does not handle the user data bits, channel status bits and validity bits of the SPDIF stream, but only the audio is given at its outputs. Some rom_codes do take care of the pre-emphasis bit of the SPDIF stream. Digital serial inputs/outputs and SPDIF inputs GENERAL DESCRIPTION DIGITAL SERIAL AUDIO INPUTS/OUTPUTS For communication with external digital sources a digital serial bus is implemented. It is a serial 3-line bus, having one line for data, one line for clock and one line for the word select. For external digital sources the SAA7706H acts as a slave, so the external source is master and supplies the clock. The bits in the audio space are always decoded regardless of any status bits e.g. ‘copy protected’, ‘professional mode’ or ‘data mode’. The DAC is not muted in the event of a non-linear PCM audio, however the bit is observable via the I2C-bus. A few other channel status bits are available. There are 5 control signals available from the SPDIF input stage. These are connected to flags of DSP2. For more details see separate manual. The digital serial input is capable of handling multiple input formats. The input is capable of handling Philips I2S-bus and LSB-justified formats of 16, 18, 20 and 24 bits word sizes. The sampling frequency can be either 44.1 or 48 kHz. See Fig.15 for the general waveform formats of all possible formats. These 5 control signals are: • Signals to indicate the sample frequency of the SPDIF signal: 44.1 and 48 kHz (32 kHz is not supported) • A lock signal indicating if the SPDIF input is in lock The number of bit clock (BCK) pulses may vary in the application. When the applied word length is smaller than 24 bits (internal resolution of DSP2), the LSB bits will get internally a zero value; when the applied word length exceeds 24 bits then the LSBs are skipped. • The pre-emphasis bit of the SPDIF audio stream • The pcm_audio/non-pcm_audio bit indicating if an audio or data stream is detected. The FSDAC output will not be muted in the event of a non-audio PCM stream. This status bit can be read via the I2C-bus, the microcontroller can decide to mute the DAC (via pin POM). It should be noted that: • Two digital sources can not be used at the same time • Maximum number of bit clocks per word select (WS) is limited to 64 The design fulfils the digital audio interface specification “IEC 60958-1 Ed2, part 1, general part IEC 60958-3 Ed2, part 3, consumer applications”. • The word select (WS) must have a duty cycle of 50%. 8.14.2 It should be noted that: GENERAL DESCRIPTION SPDIF INPUTS (SPDIF1 AND SPDIF2) • The SPDIF input may only be used in the ‘consumer mode’ specified in the digital audio interface specification For communication with external digital sources also an SPDIF input can be used. The two SPDIF input pins can be connected via an analog multiplexer to the SPDIF receiver. It is a receiver without an analog PLL that samples the incoming SPDIF with a high frequency. In this way the data is recovered synchronously on the applied system clock. • Only one of the two SPDIF sources can be used (selected) at the same time • The FSDAC will not (automatically) be muted in the event of a non-audio stream • Two digital sources can not be used at the same time From the SPDIF signal a three wire serial bus (e.g. I2S-bus) is made, consisting of a word select, data and bit clock line. The sample frequency fs depends solely on the SPDIF signal input accuracy and both 44.1 and 48 kHz are supported. 2001 Mar 05 SAA7706H • Supported sample frequencies are 44.1 and 48 kHz. 25 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 3 DATA MSB B2 MSB B2 >=8 MSB INPUT FORMAT I2S-BUS WS LEFT RIGHT 16 15 1 16 B15 LSB MSB 2 15 2 1 BCK DATA MSB B2 B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS WS LEFT RIGHT 18 17 16 15 1 18 B17 LSB MSB 2 17 16 15 2 1 BCK 26 DATA MSB B2 B3 B4 B2 B3 B4 B17 LSB Philips Semiconductors 2 1 Car radio Digital Signal Processor (DSP) >=8 3 DIGITAL DATA STREAM FORMATS 2 8.14.3 1 BCK handbook, full pagewidth 2001 Mar 05 RIGHT LEFT WS LSB-JUSTIFIED FORMAT 18 BITS WS LEFT 20 RIGHT 19 18 17 16 15 1 20 B19 LSB MSB 2 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS WS LEFT 24 23 22 21 20 RIGHT 19 18 17 16 15 2 24 B23 LSB MSB 23 22 21 20 19 18 17 16 15 2 1 BCK MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB MGR751 LSB-JUSTIFIED FORMAT 24 BITS Fig.15 All serial data input/output formats. SAA7706H DATA Product specification 1 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 8.15 RDS demodulator (pins RDS_CLOCK and RDS_DATA) 8.15.1 SAA7706H CLOCK AND DATA RECOVERY The RDS-chain has a separate input. This enables RDS updates during tape play and also the use of a second receiver for monitoring the RDS information of signals from an other transmitter (double tuner concept). It can as such be done without interruption of the audio program. The MPX signal from the main tuner of the car radio can be connected to this RDS input via the built-in source selector. The input selection is controlled by an I2C-bus bit. The RDS demodulator recovers the additional inaudible RDS information which is transmitted by FM radio broadcasting. The (buffered) data is provided as output for further processing by a suitable decoder. The operational functions of the decoder are in accordance with the EBU specification ”EN 50067”. The RDS demodulator has three different functions: The RDS chain contains a sigma-delta ADC (ADC3), followed by two decimation filters. The first filter passes the multiplex band including the signals around 57 kHz and reduces the sigma-delta noise. The second filter reduces the RDS bandwidth around 57 kHz. The overall filter curve is shown in Fig.16 and a more detailed curve of the RDS 57 kHz band in Fig.17. • Clock and data recovery from the MPX signal • Buffering of 16 bits, if selected • Interfacing with the microcontroller. MGT471 0 handbook, full pagewidth α (dB) −20 −40 −60 −80 −100 0 19 38 57 76 95 114 Fig.16 Overall frequency response curve decimation filters. 2001 Mar 05 27 133 f (kHz) 152 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) α SAA7706H MGT472 10 handbook, full pagewidth (dB) 0 −10 −20 −30 −40 −50 −60 −70 50 52 54 56 58 60 62 f (kHz) 64 Fig.17 Detailed frequency response curve RDS channel. The quadrature mixer converts the RDS band to the frequency spectrum around 0 Hz and contains the appropriate Q/I signal filters. The final decoder with CORDIC recovers the clock and data signals. These signals are output on pins RDS_CLOCK and RDS_DATA. In the event of FM-stereo reception the clock of the total chip is locked to the stereo pilot (19 kHz multiple). In the event of FM-mono the DCS loop keeps the DCS clock around the same 19 kHz multiple. In all other cases like AM reception or tape, the DCS circuit has to be set in a preset position by means of an I2C-bus bit. Under these conditions the RDS system is always clocked by the DCS clock in a 38 kHz (4 × 9.5 kHz) based sequence. 2001 Mar 05 8.15.2 TIMING OF CLOCK AND DATA SIGNALS The timing of the clock and data output is derived from the incoming data signal. Under stable conditions the data will remain valid for 400 µs after the clock transition. The timing of the data change is 100 µs before a positive clock change. This timing is suited for positive as well as negative triggered interrupts on a microcontroller. The RDS timing is shown in Fig.18. During poor reception it is possible that faults in phase occur, then the duty cycle of the clock and data signals will vary from minimum 0.5 times to a maximum of 1.5 times the standard clock periods. Normally, faults in phase do not occur on a cyclic basis. 28 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SAA7706H handbook, full pagewidth RDS_DATA RDS_CLOCK tsu tHC Tcy tLC th MGU270 Fig.18 RDS timing in the direct output mode. 8.15.3 BUFFERING OF RDS DATA In Fig.19 the interface signals from the RDS decoder and the microcontroller in buffer mode are shown. When the buffer is filled with 16 bits the data line is pulled down. The data line will remain LOW until reading of the buffer is started by pulling down the clock line. The first bit is clocked out. After 16 clock pulses the reading of the buffer is ready and the data line is set HIGH until the buffer is filled again. The microcontroller stops communication by pulling the line HIGH. The data is written out just after the clock HIGH-to-LOW transition. The data is valid when the clock is HIGH. When a new 16-bit buffer is filled before the other buffer is read, that buffer will be overwritten and the old data is lost. The repetition of the RDS data is around the 1187 Hz. This results in an interrupt on the microcontroller for every 842 µs. In a second mode, the RDS interface has a double 16-bit buffer. 8.15.4 BUFFER INTERFACE The RDS interface buffers 16 data bits. Every time 16 bits are received, the data line is pulled down and the buffer is overwritten. The microcontroller has to monitor the data line in at most every 13.5 ms. This mode can be selected via an I2C-bus. 2001 Mar 05 29 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SAA7706H handbook, full pagewidth RDS_DATA D0 D1 D2 D13 D14 D15 tLC RDS_CLOCK tHC tw block ready MGU271 Tcy start reading data Fig.19 Interface signals RDS decoder and microcontroller (buffer mode). 8.16 • The program counter of both DSPs are set to address 0000H DSP reset Pin DSP_RESET is active LOW and requires an external pull-up resistor. Between this pin and the VSSD ground a capacitor should be connected to allow a proper switch-on of the supply voltage. The capacitor value is such that the chip is in reset as long as the power supply is not stabilized. A more or less fixed relationship between the DSP_RESET (pin) and the POM (pin) time constant is mandatory. • The two output flags of DSP1 (DSP1_OUT1 and DSP1_OUT2) are reset to logic 0. All the configurable flags of DSP2 are reset to logic 0, however the four flags available at the output of the chip are default configured as input flags (DSP2_INOUT1, DSP2_INOUT2, DSP2_INOUT3 and DSP2_INOUT4). When the level on pin DSP_RESET is at HIGH, the DSP program (DSP1 and DSP2) starts to run. The voltage on pin POM determines the current flowing in the DACs. At 0 V on pin POM the DAC currents are zero and so are the DAC output voltages. 8.17 At the VDDA2 voltage the DAC currents are at their nominal (maximal) value. Long before the DAC outputs get to their nominal output voltages, the DSP must be in working mode to reset the output register: therefore the DSP time constant must be shorter than the POM time constant. For recommended capacitors see Figs 25 and 26. Pins TSCAN, RTCB and SHTCB are used to put the chip in test mode and to test the internal connections. Each pin has an internal pull-down resistor to ground. In the application these pins can be left open or connected to ground. The reset has the following function: • All I2C-bus bits are set to their default value • The DSP status registers (DSP1 and DSP2) are reset 2001 Mar 05 Test mode connections (pins TSCAN, RTCB and SHTCB) 30 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) Then the master writes the high memory address and low memory address where the reading of the memory content of the SAA7706H must start. The SAA7706H acknowledges these addresses both. Then the master generates a repeated START (Sr) and again the SAA7706H address ‘0011100’ but this time followed by a logic 1 (read) of the R/W bit. I2C-BUS FORMAT 9 For more general information on the I2C-bus protocol, see the Philips I2C-bus specification. 9.1 Addressing Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure. 9.2 From this moment on the SAA7706H will send the memory content in groups of 2 (Y-memory DSP1) or 3 (X-memory DSP1, X/Y-memory DSP2 or registers) bytes to the I2C-bus each time acknowledged by the master. The master stops this cycle by generating a negative acknowledge, then the SAA7706H frees the I2C-bus and the master can generate a STOP condition. The data is transferred from the DSP register to the I2C-bus register at execution of the MPI instruction in the DSP2 program. Therefore at least once every DSP routine an MPI instruction should be added. The data length of 4 bytes is not used in the SAA7706H. Slave address (pin A0) The SAA7706H acts as slave receiver or a slave transmitter. Therefore the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The SAA7706H slave address is shown in Table 3. Table 3 Slave address MSB 0 LSB 0 1 1 1 0 A0 9.5 R/W Write cycles The I2C-bus configuration for a write cycle is shown in Fig.20. The write cycle is used to write the bytes to both DSP1 and DSP2 for manipulating the data and coefficients. Depending on which DSP is accessed the data protocol exists out of 2, 3 or 4 bytes. More details can be found in the I2C-bus memory map (see Table 5). 9.5.1 The second block has an address space of 16 addresses and are all X-memory mapped on DSP2. While this space is 24 bits wide 3 bytes should be sent to or read from. These addresses are DSP2 mapped which means an MPI instruction is needed for accessing those locations and there is no verifying mechanism if all addresses are really mapped to physical registers. Therefore, all those locations will be acknowledged even if the data is not valid. For the SAA7706H several registers are located in this section. A few registers are predefined for DSP2 purposes (see Table 5). Read cycles I2C-bus The configuration for a READ cycle is shown in Fig.21. The read cycle is used to read the data values from XRAM or YRAM of both DSPs. The master starts with a START condition S, the SAA7706H address ‘0011100’ and a logic 0 (write) for the R/W bit. This is followed by an acknowledge of the SAA7706H. 2001 Mar 05 SAA7706H DSPS REGISTERS The hardware registers have two different address blocks. One block exists out of hardware register locations which control both DSPs and some major settings such as the PLL division. These locations have a maximum of 16 bits, which means 2 bytes need to be sent to or read from. For the SAA7706H one register is located at the DSPs and general control register (0FFFH). The data length is 2, 3 or 4 bytes depending on the accessed memory. If the Y-memory of DSP1 is addressed the data length is 2 bytes, in the event of the X-memory of DSP1 or X/Y-memory of DSP2 the length is 3 bytes. The slave receiver detects the address and adjusts the number of bytes accordingly. The data length of 4 bytes is not used in the SAA7706H. 9.4 SAA7706H hardware registers The write cycle can be used to write the bytes to the hardware registers to control the DCS block, the PLL for the DSP clock generation, the IAC settings, the AD volume control settings, the analog input selection, the format of the I2S-bus and some other settings. It is also possible to read these locations for chip status information. More detail can be found in the I2C-bus memory map, Tables 4 and 5. The sub-address bit A0 corresponds to the hardware address pin A0 which allows the device to have 2 different addresses. The A0 input is also used in test mode as a serial input of the test control block. 9.3 SAA7706H 31 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... K ADDR L A C K DATA H A C K DATA M A C K DATA L A C P K auto increment if repeated n-groups of 3 (2) bytes address MGD568 R/W S = START condition P = STOP condition ACK = acknowledge from SAA7706H ADDR H and ADDR L = address DSP register DATA 1, DATA 2, DATA3 and DATA 4 = 2, 3 or 4 bytes data word. Fig.20 Master transmitter writes to the SAA7706H registers. 32 A S 0 0 1 1 1 0 0 0 C K ADDR H A C K ADDR L A A C S 0 0 1 1 1 0 0 1 C K K DATA H A C K DATA M A C K DATA L Philips Semiconductors ADDR H Car radio Digital Signal Processor (DSP) 2001 Mar 05 A C K A S 0 0 1 1 1 0 0 0 C A C P K auto increment if repeated n-groups of 3 (2) bytes address R/W R/W Product specification Fig.21 Master transmitter reads from the SAA7706H registers. SAA7706H S = START condition Sr = repeated START condition P = STOP condition ACK = acknowledge from SAA7706H (SDA LOW) R = repeat n-times the 2, 3 or 4 bytes data group NA = negative acknowledge master (SDA HIGH) ADDR H and ADDR L = address DSP register DATA 1, DATA 2, DATA 3 and DATA 4 = 2, 3 or 4 bytes data word. MGA808 - 1 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 9.6 SAA7706H I2C-bus memory map specification The I2C-bus memory map contains all defined I2C-bus bits. The map is split up in two different sections, the hardware memory registers and the RAM definitions. In Table 5 the preliminary memory map is depicted. The hardware registers are memory map on the XRAM of DSP2. Table 5 shows the detailed memory map of those locations. All locations are acknowledged by the SAA7706H even if the user tries to write to a reserved space. The data in these sections will be lost. Reading from this locations will result in undefined data words. Table 4 I2C-bus memory map ADDRESS FUNCTION SIZE 512 × 12 bits 2000H to 21FFH YRAM (DSP2) 1FF0H to 1FFFH hardware registers 16 × 24 bits 1000H to 127FH XRAM (DSP2) 640 × 24 bits 0FFFH DSP CONTROL 1 × 16 bits 0800H to 097FH YRAM (DSP1) 384 × 12 bits 0000H to 017FH XRAM (DSP1) 384 × 18 bits Table 5 I2C-bus memory map overview of hardware registers DESCRIPTION REGISTER Hardware registers Program counter register DSP2 1FFFH Status register DSP2 1FFEH I/O configuration register DSP2 1FFDH Phone, navigation and audio register 1FFCH FM and RDS sensitivity register 1FFBH Clock coefficient register 1FFAH Clock settings register 1FF9H IAC settings register 1FF8H Selector register 1FF7H CL_GEN register 4 1FF6H CL_GEN register 3 1FF5H CL_GEN register 2 1FF4H CL_GEN register 1 1FF3H Evaluation register 1FF0H DSP control DSPs and general control register 2001 Mar 05 0FFFH 33 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SAA7706H 10 LIMITING VALUES In accordance with the Absolute Maximum Ratings System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage −0.5 +3.6 V Vn input voltage on any pin −0.5 +5.5 V IIK DC input clamping diode current VI < −0.5 V or VI > VDD + 0.5 V − ±10 mA IOK DC output clamping diode current VO < −0.5 V or VO > VDD + 0.5 V − ±20 mA IO(sink/source) DC output source or sink current −0.5 V < VO < VDD + 0.5 V − ±20 mA IDD,ISS supply current per supply pin − ±50 mA Tamb ambient operating temperature −40 +85 °C Tstg storage temperature range −65 +125 °C VESD ESD voltage human body model 100 pF; 1500 Ω 2000 − V machine model 200 pF; 0.5 µH; 10 Ω 200 − V CIC spec/test method 100 − mA − 890 mW Ilu(prot) latch-up protection current Ptot total power dissipation 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS VALUE UNIT thermal resistance from junction to ambient mounted on printed-circuit board 45 K/W MAX. UNIT 12 CHARACTERISTICS VDD = 3 to 3.6 V; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. Supplies; Tamb = −40 to +85 °C VDD operating supply voltage all VDD pins with respect to VSS 3.0 3.3 3.6 V IDDD supply current of the digital part DSP1 at 50 MHz; DSP2 at 62.9 MHz − 110 150 mA IDDD(core) supply current of the digital core part DSP1 at 50 MHz; DSP2 at 62.9 MHz − 105 140 mA IDDD(peri) supply current of the digital periphery part without external load to ground − 5 10 mA IDDA supply current of the analog part zero input and output signal − 40 60 mA IDDA(ADC) supply current of the ADCs zero input and output signal − 15 26 mA IDDA(DAC) supply current of the DACs zero input and output signal − 19 30 mA IDDA(osc) supply current XTAL oscillator functional mode − 2 4 mA 2001 Mar 05 34 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SYMBOL Ptot PARAMETER total power dissipation SAA7706H CONDITIONS DSP1 at 50 MHz, DSP2 at 62.9 MHz MIN. TYP. MAX. UNIT − 540 750 mW Digital I/O; Tamb = −40 to +85 °C; VDD = 3 to 3.6 V VIH HIGH-level input voltage for all digital inputs and I/Os 2.0 − − V VIL LOW-level input voltage for all digital inputs and I/Os − − 0.8 V Vhys Schmitt trigger hysteresis voltage 0.4 − − V VOH HIGH-level output voltage standard output; IO = −4 mA VDD − 0.4 − − V 5 ns slew rate output; IO = −4 mA VDD − 0.4 − − V 10 ns slew rate output; IO = −2 mA VDD − 0.4 − − V 20 ns slew rate output; IO = −1 mA VDD − 0.4 − − V standard output; IO = 4 mA − − 0.4 V 5 ns slew rate output; IO = 4mA − − 0.4 V 10 ns slew rate output; IO = 2 mA − − 0.4 V 20 ns slew rate output; IO = 1 mA − − 0.4 V I2C-bus output; IO = 4 mA − − 0.4 V VO = 0 V or VDD − − ±5 µA VOL LOW-level output voltage ILO output leakage current 3-state outputs Rpd internal pull-down resistor to VSS 24 50 140 kΩ Rpu internal pull-up resistor to VDD 30 50 100 kΩ Ci input capacitance − − 3.5 pF ti(r),ti(f) input rise and fall times VDD = 3.6 V − 6 200 ns to(t) output transition time standard output; CL = 30 pF − 3.5 − ns 5 ns slew rate output; CL = 30 pF − 5 − ns 10 ns slew rate output; CL = 30 pF − 10 − ns 20 ns slew rate output; CL = 30 pF − 20 − ns I2C-bus output; Cb = 400 pF 60 − 300 ns 2001 Mar 05 35 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SYMBOL PARAMETER SAA7706H CONDITIONS MIN. TYP. MAX. UNIT Analog inputs; Tamb = 25 °C; VDDA1 = 3.3 V DC CHARACTERISTICS V VREFAD ---------------------V VDDA1 common mode reference voltage ADC1, ADC2 and level-ADC Zo(VREFAD) with reference to VSSA1 0.47 0.50 0.53 output impedance at pin VREFAD − 10 − Ω VVDACP positive reference voltage ADC1, 2, 3 and level-ADC 3 3.3 3.6 V IVDACP positive reference current ADC1, 2, 3 and level-ADC − −200 − µA VVDACN1, VVDACN2 negative reference voltage ADC1, 2, 3 and level-ADC −0.3 0 +0.3 V IVDACN1, IVDACN2 negative reference current ADC1, 2 and 3 − 200 − µA VIO(ADC) input offset voltage ADC1, 2 and 3 − 140 − mV AC CHARACTERISTICS Vi(con)(max)(rms) Ri THD 2001 Mar 05 maximum conversion input level (RMS value) CD, TAPE, AM and AUX input signals THD <1% 0.6 0.66 − V FM_MPX input signal THD <1%; VOLFM = 00H 0.33 0.368 − V CD, TAPE, AM and AUX input signals 1 − − MΩ FM_MPX input signal 48 60 72 kΩ input impedance total harmonic distortion CD, TAPE, AM and AUX input signals input signal 0.55 V (RMS) at 1 kHz; bandwidth = 20 kHz; fs = 44.1 kHz − −85 −75 dB FM_MPX input signal input signal 368 mV (RMS) at − 1 kHz; bandwidth = 19 kHz; − VOLFM = 00H −70 −65 dB 0.03 0.056 % 36 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SYMBOL S/N α19 α38 PARAMETER SAA7706H CONDITIONS MIN. TYP. MAX. UNIT signal-to-noise ratio CD, TAPE, AM and AUX input signals input signal at 1 kHz; bandwidth = 20 kHz; 0 dB reference = 0.55 V (RMS); fs = 44.1 kHz 85 90 − dB FM_MPX input signal mono input signal at 1 kHz; bandwidth = 19 kHz; 0 dB reference = 0.368 V (RMS); VOLFM = 00H 80 83 − dB FM_MPX input signal stereo input signal at 1 kHz; bandwidth = 40 kHz; 0 dB reference = 0.368 V (RMS); VOLFM = 00H 75 81 − dB pilot signal frequency = 19 kHz − 81 − dB unmodulated − 98 − dB subcarrier frequency = 38 kHz − 83 − dB unmodulated − 91 − dB carrier and harmonic suppression at the output carrier and harmonic suppression at the output α57 carrier and harmonic suppression for 19 kHz, including notch subcarrier frequency = 57 kHz − 83 − dB unmodulated − 96 − dB α76 carrier and harmonic suppression for 19 kHz, including notch subcarrier frequency = 76 kHz − 84 − dB unmodulated − 94 − dB IMα10 intermodulation fmod = 10 kHz; fspur = 1 kHz 77 − − dB IMα13 intermodulation fmod = 13 kHz; fspur = 1 kHz 76 − − dB α57(VF) traffic radio suppression f = 57 kHz − 110 − dB α67(SCA) Subsidiary Communication Authority (SCA) suppression f = 67 kHz − 110 − dB α114 adjacent channel suppression f = 114 kHz − 110 − dB α190 adjacent channel suppression f = 190 kHz − 110 − dB Vth(pilot)(rms) pilot threshold voltage (RMS value) at pin DSP1_OUT1 stereo on; VOLFM = 07H − 35.5 − mV stereo off; VOLFM = 07H − 35.4 − mV − 0 − dB fi = 1 kHz 40 45 − dB fi = 10 kHz 25 30 − dB 60 70 − dB hys hysteresis of Vth(pilot)(rms) αcs1 channel separation FM-stereo input αcs2 2001 Mar 05 channel separation CD, TAPE, AM and AUX input signals 37 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SYMBOL fres PARAMETER SAA7706H CONDITIONS MIN. TYP. MAX. UNIT audio frequency response CD, TAPE, AM and AUX input signals fs = 44.1 kHz; at −3 dB 20 − − kHz FM_MPX input signal at −3 dB via DSP at DAC output 17 − − kHz − − 0.5 dB fi = 1 kHz 65 − − dB fi = 15 kHz 50 − − dB ∆GL-R overall left/right gain unbalance (TAPE, CD, AUX and AM input signals) αct crosstalk between inputs PSRRMPX/RDS power supply ripple rejection MPX and RDS ADCs output via ADC input 35 short-circuited; fripple = 1 kHz; Vripple = 100 mV (peak); CVREFAD = 22 µF; CVDACP = 10 µF 45 − dB PSRRLAD power supply ripple rejection level-ADC output via DAC; ADC input 29 short-circuited; fripple = 1 kHz; Vripple = 100 mV (peak); CVREFAD = 22 µF 39 − dB CMRRCD common-mode rejection ratio for CD input mode RCD_(L)_GND = 1 MΩ; resistance of CD player ground cable < 1 kΩ; fi = 1 kHz 60 − − dB I2S-bus; AC characteristics PHONE and NAV inputs; Tamb = 25 °C; VDDA1 = 3.3 V THD total harmonic distortion of PHONE and NAV input signals at maximum input voltage Vi = 0.75 V (RMS); fi = 1 kHz; 40 VOLMIX = 30H; measured at FLV and FRV outputs − − dB CMRR common mode rejection ratio of PHONE and NAV input signals Vi = 0.75 V(RMS); fi = 1 kHz; 25 VOLMIX = 30H 50 − dB Ri input impedance of PHONE, NAV/AM_L and AM_R input signals 90 120 150 kΩ Vi(max)(rms) maximum input level of PHONE and NAV input signals (RMS value) 0.75 1 − V fi = 1 kHz; VOLMIX = 30H AC characteristics FM_RDS input; Tamb = 25 °C; VDDA1 = 3.3 V Vi(con)(max)(rms) maximum conversion level THD < 1%; VOLRDS = 00H of FM_RDS input (RMS value) 0.33 0.368 − V Ri(FM_RDS) input resistance FM_RDS input 40 60 72 kΩ THDFM_RDS total harmonic distortion RDS ADC −60 −67 − dB 2001 Mar 05 fc = 57 kHz 38 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SYMBOL PARAMETER S/NFMRDS signal-to-noise ratio RDS ADC αpilot pilot attenuation RDS α nearby selectivity RDS αn(ADC) RDS ADC noise attenuation Vripple(RDS) ripple voltage RDS pass band αmux(RDS) ∆fosc SAA7706H CONDITIONS MIN. TYP. MAX. UNIT 6 kHz bandwidth; fc = 57 kHz; 54 0 dB reference = 0.55 V (RMS); VOLRDS = 00H − − dB 50 − − dB 61 − − dB 70 − − dB − − 0.5 dB multiplex attenuation RDS mono 70 − − dB stereo 40 − − dB maximum crystal resonance frequency deviation of 100 ppm − − 6 Hz 0.2 0.5 3.3 V − 6 − kΩ − 40 − mV 48 54 − dB allowable frequency deviation of the 57 kHz RDS neighbouring channel at 200 kHz distance 2.4 kHz bandwidth AC characteristics SPDIF1 and SPDIF2 inputs; Tamb = 25 °C; VDDA2 = 3.3 V Vi(p-p) AC input level (peak-to-peak level) Ri input impedance Vhys hysteresis of input voltage at 1 kHz AC characteristics analog LEVEL input; Tamb = 25 °C; VDDA1 = 3.3 V S/NLAD signal-to-noise ratio of level-ADC 0 to 29 kHz bandwidth; maximum input level; unweighted Ri input resistance 1.0 − 2.2 MΩ Vi(fs)(LAD) full-scale level-ADC input voltage 0 − VDDA1 V VIO DC offset voltage − − 120 mV α decimation filter attenuation 20 − − fco(PB) pass band cut-off frequency at −3 dB and DCS clock = 9.728 MHz − 29 − kHz fsr sample rate frequency after decimation DCS clock = 9.728 MHz − 38 − kHz dB ------------------decade Analog DAC outputs on pins FLV, FRV, RLV and RRV; Tamb = 25 °C; VDDA2 = 3.3 V; fs = 44.1 kHz; RL = 5 kΩ; fi = 1 kHz DC CHARACTERISTICS Ro(ref) reference output resistance pin VREFDA − 14 − kΩ Ro DAC output resistance pins FLV, FRV, RLV and RRV − 0.13 3.0 Ω Io(max) maximum output current (THD + N)/S < 0.1%; RL = 5 kΩ − 0.22 − mA RL load resistance 3 − − kΩ 2001 Mar 05 39 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SYMBOL CL PARAMETER SAA7706H CONDITIONS load capacitance MIN. TYP. MAX. UNIT − − 200 pF AC CHARACTERISTICS Vo(RMS) output voltage (RMS value) − 1000 − mV ∆Vo unbalance between channels − 0.1 − dB (THD + N)/S total harmonic distortion-plus-noise to signal ratio (measured with system one) at 0 dB − −90 −85 dB at −60 dB; A-weighted − −37 − dB S/N signal-to-noise ratio (measured with system one) code = 0; A-weighted − 105 − dB αcs channel separation PSRR power supply rejection ratio − 80 − dB fripple = 1 kHz; Vripple(p-p) = 1% − 50 − dB Oscillator; Tamb = 25 °C; VDD(OSC) = 3.3 V − 11.2896 − MHz 1.6 2.6 V fxtal crystal frequency Vxtal voltage across the crystal crystal series resistance Rs < 100 Ω; crystal shunt capacitance Cp < 7 pF; crystal load capacitance CL = 12 pF; C1 = C2 = 22 pF (see Fig.13) IDD(OSC) supply current crystal oscillator at start-up 1.7 3.4 6.4 mA at oscillation − 0.32 − mA 3.6 13 RDS AND I2S-BUS TIMING Tamb = 25 °C; VDDD = 3.3 V; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT RDS timing (see Figs 18 and 19) fRDSCLK nominal RDS clock frequency tsu clock set-up time Tcy cycle time tHC clock HIGH time tLC clock LOW time th data hold time tw wait time 2001 Mar 05 − 1187.5 − Hz direct output mode 100 − − µs direct output mode − 842 − µs buffer mode 2 − − µs direct output mode 220 − 640 µs buffer mode 1 − − µs direct output mode 220 − 640 µs buffer mode 1 − − µs 100 − − µs 1 − − µs buffer mode 40 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SYMBOL PARAMETER SAA7706H CONDITIONS MIN. TYP. MAX. UNIT I2S-bus timing (see Fig.23) tr rise time Tcy = 325 ns − − 0.15Tcy ns tf fall time Tcy = 325 ns − − 0.15Tcy ns Tcy bit clock cycle time 325 − − ns tBCK(H) bit clock time HIGH Tcy = 325 ns 0.35Tcy − − ns tBCK(L) bit clock time LOW Tcy = 325 ns 0.35Tcy − − ns tsu(D) data set-up time Tcy = 325 ns 0.2Tcy − − ns th(D) data hold time Tcy = 325 ns 0.2Tcy − − ns td(D) data delay time Tcy = 325 ns − − 0.15Tcy ns tsu(WS) word select set-up time Tcy = 325 ns 0.2Tcy − − ns th(WS) word select hold time Tcy = 325 ns 0.2Tcy − − ns LEFT handbook, full pagewidth WS RIGHT tBCK(H) tr tsu(WS) tf th(WS) td(D) BCK tBCK(L) tsu(D) th(D) Tcy DATA IN DATA OUT LSB MSB LSB MSB MGM129 Fig.23 Input timing digital audio data inputs. 2001 Mar 05 41 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SAA7706H 14 I2C-BUS TIMING Tamb = 25 °C; VDDD = 3.3 V; unless otherwise specified. SYMBOL PARAMETER STANDARD MODE I2C-BUS CONDITIONS MIN. FAST MODE I2C-BUS UNIT MAX. MIN. MAX. fSCL SCL clock frequency 0 100 0 400 kHz tBUF bus free time between a STOP and START condition 4.7 − 1.3 − µs tHD;STA hold time (repeated) START condition. After this period, the first clock pulse is generated 4.0 − 0.6 − µs tLOW LOW period of the SCL clock 4.7 − 1.3 − µs tHIGH HIGH period of the SCL clock 4.0 − 0.6 − µs tSU;STA set-up time for a repeated START condition 4.7 − 0.6 − µs tHD;DAT data hold time 0 − 0 0.9 µs tSU;DAT data set-up time 250 − 100 − ns tr rise time of both SDA and SCL signals Cb in pF − 1000 20 + 0.1Cb 300 ns tf fall time of both SDA and Cb in pF SCL signals − 300 20 + 0.1Cb 300 ns tSU;STO set-up time for STOP condition 4.0 − 0.6 − µs Cb capacitive load for each bus line − 400 − 400 pF tSP pulse width of spikes to be suppressed by input filter − − 0 50 ns 2001 Mar 05 42 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SAA7706H handbook, full pagewidth SDA tLOW tf tSU;DAT tr tf tHD;STA tSP tr tBUF SCL S tHD;STA tHD;DAT tHIGH tSU;STA Sr tSU;STO P S MSC610 Fig.24 Definition of timing on the I2C-bus. 15 SOFTWARE DESCRIPTION The use and description of the software features of the SAA7706H will be described in the separate application manual. 16 APPLICATION DIAGRAM The application diagram shown in Figs 25 and 26 must be considered as one of the examples of a (limited) application of the chip e.g. in this case the I2S-bus inputs of the CD-input are not used. For the real application set-up the information of the application report is necessary. 2001 Mar 05 43 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) handbook, full pagewidth SAA7706H VDDD VDDA R35 10 Ω L2 R34 R1 C1 PHONE C3 220 pF R3 100 kΩ C5 LEVEL 27 kΩ C4 220 pF 46 36 22 VSSD3V7 VSSD3V6 VSSD3V5 VSSD3V4 VSSD3V3 VSSD3V2 VSSD3V1 VDDD3V7 VDDD3V6 VDDD3V5 76 75 VSSA1 VDACN2 74 49 50 53 54 47 37 23 NAV_GND 220 nF LEVEL MONO CMRR INPUTS 73 A 4 3 LEVEL ADC B CD_L 72 8.2 kΩ C7 47 µF CD-GND R5 100 kΩ R6 1 µF 2 PHONE_GND 470 nF 15 kΩ R4 CD-L 1 PHONE 71 470 nF 15 kΩ C2 R2 C6 VDACP VDACN1 VDDA1 10 Ω C43 100 µF C45 22 nF C8 R7 1 µF 8.2 kΩ R8 10 kΩ C9 100 pF R9 10 kΩ C10 100 pF CD-R CD_(L)_GND 77 CD_R 70 CD_R_GND 14 VREFAD 78 AM_L/NAV 67 AM_R/AM 66 TAPE_L 69 TAPE_R 68 STEREO CMRR INPUTS SAA7706H R10 1 MΩ C12 22 µF R11 100 pF R13 AM-R/AM R17 TAPE-L C18 100 pF 220 nF 56 kΩ C20 100 pF R37 220 nF 82 kΩ C47 100 pF R39 220 nF 82 kΩ C48 100 pF C21 27 pF C22 R19 FM 22 kΩ AUX_L MONO ADC3 7 R39 100 kΩ AUX-R ANALOG SOURCE SELECTOR R38 100 kΩ AUX-L E R18 100 kΩ TAPE-R STEREO ADC2 1 µF AUX_R 8 FM_RDS 79 FM_MPX 80 SEL_FR 61 RDS DEMODULATOR XTAL OSCILLATOR 43 44 45 21 60 59 62 65 C23 100 nF RDS RDS DATA CLOCK L1 R36 10 Ω VDDA Fig.25 Application diagram (continued in Fig.26). 2001 Mar 05 44 63 64 OSC_OUT 56 kΩ C19 R16 100 kΩ OSC_IN 220 nF 100 pF VSS(OSC) R15 RDS_CLOCK 100 kΩ C16 C17 D RDS_DATA 220 nF STEREO ADC1 TP1 100 kΩ C14 TSCAN C15 RTCB 220 nF C SHTCB C13 AM-L/NAV VDD(OSC) C11 47 nF C24 18 pF X1 11.2896 MHz C25 18 pF C48 47 µF MGT473 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SAA7706H handbook, full pagewidth VDDD VDDD 48 51 52 55 +5 V DSP2_INOUT1 DSP2_INOUT2 R37 4.7 kΩ DSP2_INOUT3 DSP2_INOUT4 DSP1_IN1 DSP1_IN2 DSP1_OUT1 DSP1_OUT2 VDDD3V4 VDDD3V3 VDDD3V2 VDDD3V1 DSP-FLAGS R24 910 Ω T1 R25 4.7 kΩ 41 40 39 38 19 18 15 17 11 VDDA2 10 VSSA2 C31 22 µF C32 100 nF 5 POM microcontroller C33 22 µF PHONE VOLUME A + SIGNAL LEVEL B 16 FLV C34 10 µF + SAA7706H 13 FRV C36 10 µF FRONT-LEFT C35 10 nF R29 R28 100 Ω FRONT-RIGHT C37 10 nF 10 kΩ QUAD FSDAC DSP1 9 RLV C38 10 µF R31 R30 100 Ω REAR-LEFT C39 10 nF 10 kΩ STEREO DECODER IAC R26 10 kΩ SIGNAL QUALITY C R27 100 Ω 6 RRV DIGITAL SOURCE SELECTOR D C40 10 µF R33 R32 100 Ω REAR-RIGHT C41 10 nF 10 kΩ E 12 VREFDA C42 4.7 µF 34 IIS_OUT1 A DIGITAL SOURCE B SELECTORS 35 IIS_OUT2 DSP2 30 IIS_CLK DIGITAL I/O 33 IIS_WS 31 IIS_IN1 32 IIS_IN2 I2S-BUS I2C-BUS SPDIF SDA 56 42 DSP_RESET 58 A0 57 SCL SPDIF1 24 25 SPDIF2 CD_CLK CD_WS 29 27 28 CD_DATA 26 SYSFS 20 LOOPO C27 SPDIF2 C26 100 pF R20 100 nF 75 Ω C29 R22 10 kΩ R23 10 kΩ +5 V microcontroller C30 1 µF +5 V SPDIF1 C28 100 pF R21 100 nF 75 Ω SCL SDA MGT474 Fig.26 Application diagram (continued from Fig.25). 2001 Mar 05 45 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SAA7706H 17 PACKAGE OUTLINE QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT318-2 c y X 64 A 41 40 65 ZE e E HE A A2 (A 3) A1 θ wM pin 1 index Lp bp 80 L 25 detail X 24 1 wM bp e ZD v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 3.2 0.25 0.05 2.90 2.65 0.25 0.45 0.30 0.25 0.14 20.1 19.9 14.1 13.9 0.8 24.2 23.6 18.2 17.6 1.95 1.0 0.6 0.2 0.2 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT318-2 2001 Mar 05 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-08-01 99-12-27 MO-112 46 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) If wave soldering is used the following conditions must be observed for optimal results: 18 SOLDERING 18.1 Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 18.2 SAA7706H – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. 18.3 18.4 Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. 2001 Mar 05 Manual soldering 47 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) 18.5 SAA7706H Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2001 Mar 05 48 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) SAA7706H 19 DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 20 DEFINITIONS 21 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 22 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2001 Mar 05 49 Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) NOTES 2001 Mar 05 50 SAA7706H Philips Semiconductors Product specification Car radio Digital Signal Processor (DSP) NOTES 2001 Mar 05 51 SAA7706H Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/25/01/pp52 Date of release: 2001 Mar 05 Document order number: 9397 750 07096