8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-powe ...

P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAM
Rev. 08 — 15 December 2004
Product data
1. General description
The P89LPC920/921/922/9221 are single-chip microcontrollers designed for
applications demanding high-integration, low cost solutions over a wide range of
performance requirements. The P89LPC920/921/922/9221 is based on a high
performance processor architecture that executes instructions in two to four clocks,
six times the rate of standard 80C51 devices. Many system-level functions have been
incorporated into the P89LPC920/921/922/9221 in order to reduce component count,
board space, and system cost.
2. Features
2.1 Principal features
■ 2 kB/4 kB/8 kB Flash code memory with 1 kB erasable sectors, 64-byte erasable
page size, and single byte erase.
■ 256-byte RAM data memory.
■ Two 16-bit counter/timers. Each timer may be configured to toggle a port output
upon timer overflow or to become a PWM output.
■ Real-Time clock that can also be used as a system timer.
■ Two analog comparators with selectable inputs and reference source.
■ Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities.
■ 400 kHz byte-wide I2C-bus communication port.
■ Configurable on-chip oscillator with frequency range and RC oscillator options
(selected by user programmed Flash configuration bits). The RC oscillator (factory
calibrated to ±1 %) option allows operation without external oscillator
components. Oscillator options support frequencies from 20 kHz to the maximum
operating frequency of 18 MHz. The RC oscillator option is selectable and fine
tunable.
■ 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
■ High drive current (20 mA) on eight I/O pins on the P89LPC9221 (P0.3 to P0.7,
P1.4, P1.6, P1.7).
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
2.2 Additional features
■ 15 I/O pins minimum. Up to 18 I/O pins while using on-chip oscillator and reset
options.
■ 20-pin TSSOP and DIP packages.
■ A high performance 80C51 CPU provides instruction cycle times of 111 ns to
222 ns for all instructions except multiply and divide when executing at 18 MHz.
This is six times the performance of the standard 80C51 running at the same
clock frequency. A lower clock frequency for the same performance results in
power savings and reduced EMI.
■ In-Application Programming of the Flash code memory. This allows changing the
code in a running application.
■ Serial Flash programming allows simple in-circuit production coding. Flash
security bits prevent reading of sensitive application programs.
■ Watchdog timer with separate on-chip oscillator, requiring no external
components. The watchdog prescaler is selectable from eight values.
■ Low voltage reset (Brownout detect) allows a graceful system shutdown when
power fails. May optionally be configured as an interrupt.
■ Idle and two different Power-down reduced power modes. Improved wake-up from
Power-down mode (a low interrupt input starts execution). Typical Power-down
current is 1 µA (total Power-down with voltage comparators disabled).
■ Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.
■ Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
■ Programmable port output configuration options:
◆ quasi-bidirectional,
◆ open drain,
◆ push-pull,
◆ input-only.
■ Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value
of the pins match or do not match a programmable pattern.
■ LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip (160 mA for the P89LPC9221; 80 mA for the P89LPC920/921/922).
■ Controlled slew rate port outputs to reduce EMI. Outputs have approximately
10 ns minimum ramp times.
■ Only power and ground connections are required to operate the
P89LPC920/921/922/9221 when internal reset option is selected.
■ Four interrupt priority levels.
■ Eight keypad interrupt inputs, plus two additional external interrupt inputs.
■ Second data pointer.
■ Schmitt trigger port inputs.
■ Emulation support.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
2 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
3. Ordering information
Table 1:
Ordering information
Type number
Package
Name
Description
Version
P89LPC920FDH
TSSOP20
plastic thin shrink small outline package;
20 leads; body width 4.4 mm
SOT360-1
P89LPC921FDH
TSSOP20
plastic thin shrink small outline package;
20 leads; body width 4.4 mm
SOT360-1
P89LPC922FDH
TSSOP20
plastic thin shrink small outline package;
20 leads; body width 4.4 mm
SOT360-1
P89LPC922FN
DIP20
plastic dual in-line package; 20 leads (300 mil) SOT146-1
P89LPC9221FN
DIP20
plastic dual in-line package; 20 leads (300 mil) SOT146-1
P89LPC9221FDH TSSOP20
plastic thin shrink small outline package;
20 leads; body width 4.4 mm
SOT360-1
3.1 Ordering options
Table 2:
Part options
Type number
Flash memory
Temperature range
Frequency
P89LPC920FDH
2 kB
−40 °C to +85 °C
0 MHz to 18 MHz
P89LPC921FDH
4 kB
−40 °C to +85 °C
0 MHz to 18 MHz
P89LPC922FDH
8 kB
−40 °C to +85 °C
0 MHz to 18 MHz
P89LPC922FN
8 kB
−40 °C to +85 °C
0 MHz to 18 MHz
P89LPC9221FN
8 kB
−40 °C to +85 °C
0 MHz to 18 MHz
P89LPC9221FDH
8 kB
−40 °C to +85 °C
0 MHz to 18 MHz
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
3 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
4. Block diagram
P89LPC920/921/922/9221
HIGH PERFORMANCE
ACCELERATED 2-CLOCK 80C51 CPU
2 kB/4 kB/8 kB
CODE FLASH
UART
internal bus
256-BYTE
DATA RAM
REAL-TIME CLOCK/
SYSTEM TIMER
PORT 3
CONFIGURABLE I/Os
I2C
PORT 1
CONFIGURABLE I/Os
TIMER 0
TIMER 1
PORT 0
CONFIGURABLE I/Os
WATCHDOG TIMER
AND OSCILLATOR
KEYPAD
INTERRUPT
ANALOG
COMPARATORS
PROGRAMMABLE
OSCILLATOR DIVIDER
CRYSTAL
OR
RESONATOR
CONFIGURABLE
OSCILLATOR
CPU
clock
ON-CHIP
RC
OSCILLATOR
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
002aaa410
Fig 1. Block diagram.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
4 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
5. Pinning information
5.1 Pinning
handbook, halfpage
20 P0.1/CIN2B/KBI1
P1.7 2
19 P0.2/CIN2A/KBI2
P1.6 3
18 P0.3/CIN1B/KBI3
RST/P1.5 4
VSS 5
XTAL1/P3.1 6
CLKOUT/XTAL2/P3.0 7
P89LPC920FDH
P89LPC921FDH
P89LPC922FDH
P89LPC9221FDH
KBI0/CMP2/P0.0 1
17 P0.4/CIN1A/KBI4
16 P0.5/CMPREF/KBI5
15 VDD
14 P0.6/CMP1/KBI6
13 P0.7/T1/KBI7
INT1/P1.4 8
SDA/INT0/P1.3 9
12 P1.0/TXD
SCL/T0/P1.2 10
11 P1.1/RXD
002aaa408
Fig 2. TSSOP20 pin configuration.
handbook, halfpage
20 P0.1/CIN2B/KBI1
P1.7 2
19 P0.2/CIN2A/KBI2
P1.6 3
18 P0.3/CIN1B/KBI3
RST/P1.5 4
17 P0.4/CIN1A/KBI4
VSS 5
XTAL1/P3.1 6
CLKOUT/XTAL2/P3.0 7
P89LPC922FN
P89LPC9221FN
KBI0/CMP2/P0.0 1
16 P0.5/CMPREF/KBI5
15 VDD
14 P0.6/CMP1/KBI6
13 P0.7/T1/KBI7
INT1/P1.4 8
SDA/INT0/P1.3 9
12 P1.0/TXD
SCL/T0/P1.2 10
11 P1.1/RXD
002aaa407
Fig 3. DIP20 pin configuration.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
5 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
5.2 Pin description
Table 3:
Pin description
Symbol
Pin
P0.0 to P0.7
Type
Description
I/O
Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 8.12.1 “Port
configurations” and Table 8 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
1
20
19
18
17
16
14
13
I/O
P0.0 — Port 0 bit 0.
O
CMP2 — Comparator 2 output.
I
KBI0 — Keyboard input 0.
I/O
P0.1 — Port 0 bit 1.
I
CIN2B — Comparator 2 positive input B.
I
KBI1 — Keyboard input 1.
I/O
P0.2 — Port 0 bit 2.
I
CIN2A — Comparator 2 positive input A.
I
KBI2 — Keyboard input 2.
I/O
P0.3 — Port 0 bit 3. High current source (P89LPC9221).
I
CIN1B — Comparator 1 positive input B.
I
KBI3 — Keyboard input 3.
I/O
P0.4 — Port 0 bit 4. High current source (P89LPC9221).
I
CIN1A — Comparator 1 positive input A.
I
KBI4 — Keyboard input 4.
I/O
P0.5 — Port 0 bit 5. High current source (P89LPC9221).
I
CMPREF — Comparator reference (negative) input.
I
KBI5 — Keyboard input 5.
I/O
P0.6 — Port 0 bit 6. High current source (P89LPC9221).
O
CMP1 — Comparator 1 output.
I
KBI6 — Keyboard input 6.
I/O
P0.7 — Port 0 bit 7. High current source (P89LPC9221).
I/O
T1 — Timer/counter 1 external count input or overflow output.
I
KBI7 — Keyboard input 7.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
6 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
Table 3:
Pin description…continued
Symbol
Pin
P1.0 to P1.7
Type
I/O, I
Description
[1]
Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three
pins as noted below. During reset Port 1 latches are configured in the input only mode
with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs
and outputs depends upon the port configuration selected. Each of the configurable
port pins are programmed independently. Refer to Section 8.12.1 “Port configurations”
and Table 8 “DC electrical characteristics” for details. P1.2 - P1.3 are open drain when
used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
12
11
10
9
8
4
I/O
P1.0 — Port 1 bit 0.
O
TXD — Transmitter output for the serial port.
I/O
P1.1 — Port 1 bit 1.
I
RXD — Receiver input for the serial port.
I/O
P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O
T0 — Timer/counter 0 external count input or overflow output (open-drain when used as
output).
I/O
SCL — I2C serial clock input/output.
I/O
P1.3 — Port 1 bit 3 (open-drain when used as output).
I
INT0 — External interrupt 0 input.
I/O
SDA — I2C serial data input/output.
I/O
P1.4 — Port 1 bit 4. High current source (P89LPC9221).
I
INT1 — External interrupt 1 input.
I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input (if selected via FLASH configuration). A LOW on this pin
resets the microcontroller, causing I/O ports and peripherals to take on their default
states, and the processor begins execution at address 0. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until VDD has
reached its specified level. When system power is removed VDD will fall below the
minimum specified operating voltage. When using an oscillator frequency above
12 MHz, in some applications, an external brownout detect circuit may be
required to hold the device in reset when VDD falls below the minimum specified
operating voltage.
3
I/O
P1.6 — Port 1 bit 6. High current source (P89LPC9221).
2
I/O
P1.7 — Port 1 bit 7. High current source (P89LPC9221).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
7 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
Table 3:
Pin description…continued
Symbol
Pin
P3.0 to P3.1
Type
Description
I/O
Port 3: Port 3 is an 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 3 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 8.12.1 “Port
configurations” and Table 8 “DC electrical characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below:
7
6
I/O
P3.0 — Port 3 bit 0.
O
XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the FLASH configuration.
O
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It
can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source for
the real time clock/system timer.
I/O
P3.1 — Port 3 bit 1.
I
XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selected via the FLASH configuration). It can be a port pin if internal RC oscillator or
watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used
to generate the clock for the real time clock/system timer.
VSS
5
I
Ground: 0 V reference.
VDD
15
I
Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power down modes.
[1]
Input/Output for P1.0-P1.4, P1.6, P1.7. Input for P1.5.
6. Logic symbol
XTAL2
XTAL1
PORT 1
CLKOUT
VSS
P89LPC920/921/922/9221
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
PORT 3
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
PORT 0
VDD
TxD
RxD
T0
INT0
INT1
RST
SCL
SDA
002aaa409
Fig 4. Logic symbol.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
8 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
7. Special function registers
Remark: Special Function Registers (SFRs) accesses are restricted in the following
ways:
• User must not attempt to access any SFR locations not defined.
• Accesses to any defined SFR locations must be strictly for the functions for the
SFRs.
• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:
– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value
when read (even if it was written with ‘0’). It is a reserved bit and may be used in
future derivatives.
– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.
– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
9 of 46
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors
9397 750 14469
Product data
Table 4:
Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
addr.
MSB
Hex
Binary
E0H
00
00000000
A2H
00[1]
000000x0
Bit address
ACC*
Accumulator
Reset value
E7
E6
E5
LSB
E4
E3
E2
E1
E0
AUXR1
Auxiliary function register
B*
B register
F0H
00
00000000
BRGR0[2]
Baud rate generator rate
LOW
BEH
00
00000000
BRGR1[2]
Baud rate generator rate
HIGH
BFH
00
00000000
BRGCON
Baud rate generator control
BDH
00
xxxxxx00
CMF1
00[1]
xx000000
CMF2
00[1]
xx000000
Bit address
Comparator 1 control register
ACH
EBRR
ENT1
ENT0
SRST
0
-
DPS
F7
F6
F5
F4
F3
F2
F1
F0
-
-
CE1
CP1
CP2
CN1
CN2
OE1
OE2
SBRGS
CO1
CO2
BRGEN
DIVM
CPU clock divide-by-M
control
95H
00
00000000
DPTR
Data pointer (2 bytes)
83H
00
00000000
10 of 46
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Data pointer LOW
82H
00
00000000
FMADRH
Program Flash address HIGH
E7H
00
00000000
FMADRL
Program Flash address LOW
E6H
00
00000000
FMCON
Program Flash control (Read)
E4H
BUSY
-
-
-
HVA
HVE
SV
OI
70
01110000
Program Flash control (Write)
E4H
FMCMD.
7
FMCMD.
6
FMCMD.
5
FMCMD.
4
FMCMD.
3
FMCMD.
2
FMCMD.
1
FMCMD.
0
FMDATA
Program Flash data
E5H
00
00000000
I2ADR
I2C
DBH
00
00000000
I2CON*
I2C
00
x00000x0
I2DAT
I2C data register
DAH
I2SCLH
Serial clock generator/SCL
duty cycle register HIGH
DDH
00
00000000
slave address register
Bit address
control register
D8H
I2ADR.6
I2ADR.5
I2ADR.4
I2ADR.3
I2ADR.2
I2ADR.1
I2ADR.0
GC
DF
DE
DD
DC
DB
DA
D9
D8
-
I2EN
STA
STO
SI
AA
-
CRSEL
P89LPC920/921/922/9221
ADH
DPL
CE2
-
Comparator 2 control register
Data pointer HIGH
-
-
CMP2
DPH
-
-
8-bit microcontrollers with two-clock 80C51 core
Rev. 08 — 15 December 2004
CMP1
CLKLP
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR Bit functions and addresses
addr.
MSB
I2SCLL
Serial clock generator/SCL
duty cycle register LOW
DCH
I2STAT
I2C status register
D9H
Bit address
IEN0*
Interrupt enable 0
IEN1*
Interrupt enable 1
A8H
Bit address
E8H
Bit address
IP0*
Interrupt priority 0 HIGH
B8H
B7H
Bit address
IP1*
IP1H
Interrupt priority 1
Interrupt priority 1 HIGH
F8H
F7H
Keypad control register
94H
KBMASK
Keypad interrupt mask
register
86H
KBPATN
Keypad pattern register
Port 0
80H
11 of 46
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Bit address
P1*
Port 1
90H
Bit address
Hex
Binary
00
00000000
F8
11111000
00[1]
00000000
00[1]
00x00000
STA.4
STA.3
STA.2
STA.1
STA.0
0
0
0
AF
AE
AD
AC
AB
AA
A9
A8
EA
EWDRT
EBO
ES/ESR
ET1
EX1
ET0
EX0
EF
EE
ED
EC
EB
EA
E9
E8
-
EST
-
-
-
EC
EKBI
EI2C
BF
BE
BD
BC
BB
BA
B9
B8
-
PWDRT
PBO
PS/PSR
PT1
PX1
PT0
PX0
00[1]
x0000000
00[1]
x0000000
-
PWDRT
H
PBOH
PSH/
PSRH
PT1H
PX1H
PT0H
PX0H
FF
FE
FD
FC
FB
FA
F9
F8
-
PST
-
-
-
PC
PKBI
PI2C
00[1]
00x00000
PI2CH
00[1]
00x00000
KBIF
00[1]
xxxxxx00
00
00000000
FF
11111111
-
PSTH
-
-
-
-
PCH
-
PKBIH
PATN
_SEL
93H
Bit address
P0*
LSB
87
86
85
84
83
82
81
80
T1/KB7
CMP1
/KB6
CMPREF
/KB5
CIN1A
/KB4
CIN1B
/KB3
CIN2A
/KB2
CIN2B
/KB1
CMP2
/KB0
97
96
95
94
93
92
91
90
-
-
RST
INT1
INT0/
SDA
T0/SCL
RXD
TXD
B7
B6
B5
B4
B3
B2
B1
B0
-
-
-
-
-
-
XTAL1
XTAL2
[1]
[1]
[1]
P3*
Port 3
B0H
P0M1
Port 0 output mode 1
84H
(P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF
11111111
P0M2
Port 0 output mode 2
85H
(P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00
00000000
P1M1
Port 1 output mode 1
91H
(P1M1.7) (P1M1.6)
-
(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3[1]
11x1xx11
P89LPC920/921/922/9221
KBCON
Reset value
8-bit microcontrollers with two-clock 80C51 core
Rev. 08 — 15 December 2004
IP0H
Interrupt priority 0
Philips Semiconductors
9397 750 14469
Product data
Table 4:
Special function registers…continued
* indicates SFRs that are bit addressable.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
P1M2
Description
SFR Bit functions and addresses
addr.
MSB
Port 1 output mode 2
92H
(P1M2.7) (P1M2.6)
-
Reset value
LSB
(P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0)
Hex
Binary
00[1]
00x0xx00
03[1]
xxxxxx11
P3M1
Port 3 output mode 1
B1H
-
-
-
-
-
-
(P3M1.1) (P3M1.0)
P3M2
Port 3 output mode 2
B2H
-
-
-
-
-
-
(P3M2.1) (P3M2.0) 00[1]
xxxxxx00
PCON
Power control register
87H
SMOD1
SMOD0
BOPD
BOI
GF1
GF0
PMOD1
00
00000000
00[1]
00000000
B5H
-
VCPD
-
D7
D6
D5
D4
CY
AC
F0
RS1
I2PD
PMOD0
PCONA
Power control register A
PSW*
Program status word
D0H
PT0AD
Port 0 digital input disable
F6H
-
-
RSTSRC
Reset source register
DFH
-
-
BOF
POF
R_BK
R_WD
R_SF
R_EX
RTCCON
Real-time clock control
D1H
RTCF
RTCS1
RTCS0
-
-
-
ERTC
RTCEN
RTCH
Real-time clock register
HIGH
D2H
00[6]
00000000
RTCL
Real-time clock register LOW
D3H
00[6]
00000000
Bit address
RTCPD
-
SPD
-
D3
D2
D1
D0
RS0
OV
F1
P
00H
00000000
-
00H
xx00000x
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
[3]
A9H
00
00000000
Serial port address enable
B9H
00
00000000
SBUF
Serial Port data buffer
register
99H
xx
xxxxxxxx
9F
9E
9D
9C
9B
9A
99
98
12 of 46
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SCON*
Serial port control
98H
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
00
00000000
SSTAT
Serial port extended status
register
BAH
DBMOD
INTLO
CIDIS
DBISEL
FE
BR
OE
STINT
00
00000000
SP
Stack pointer
81H
07
00000111
TAMOD
Timer 0 and 1 auxiliary mode
00
xxx0xxx0
00
00000000
8FH
Bit address
-
-
-
T1M2
-
-
-
T0M2
8F
8E
8D
8C
8B
8A
89
88
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TCON*
Timer 0 and 1 control
88H
TH0
Timer 0 HIGH
8CH
00
00000000
TH1
Timer 1 HIGH
8DH
00
00000000
TL0
Timer 0 LOW
8AH
00
00000000
TL1
Timer 1 LOW
8BH
00
00000000
TMOD
Timer 0 and 1 mode
89H
00
00000000
T1GATE
T1C/T
T1M1
T1M0
T0GATE
T0C/T
T0M1
T0M0
P89LPC920/921/922/9221
Serial port address register
SADEN
8-bit microcontrollers with two-clock 80C51 core
Rev. 08 — 15 December 2004
60[1][6]
SADDR
Bit address
Philips Semiconductors
9397 750 14469
Product data
Table 4:
Special function registers…continued
* indicates SFRs that are bit addressable.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR Bit functions and addresses
addr.
MSB
Reset value
LSB
Hex
Binary
TRIM
Internal oscillator trim register
96H
-
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
[5] [6]
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
[4] [6]
WDL
Watchdog load
C1H
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
[1]
[2]
[3]
[4]
FF
11111111
All ports are in input only (high impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.
The RSTSRC register reflects the cause of the P89LPC920/921/922/9221 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on
reset value is xx110000.
After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after watchdog reset and is ‘0’ after power-on reset. Other resets will
not affect WDTOF.
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset source that affects these SFRs is power-on reset.
P89LPC920/921/922/9221
13 of 46
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8-bit microcontrollers with two-clock 80C51 core
Rev. 08 — 15 December 2004
[5]
[6]
Philips Semiconductors
9397 750 14469
Product data
Table 4:
Special function registers…continued
* indicates SFRs that are bit addressable.
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8. Functional description
Remark: Please refer to the P89LPC920/921/922/9221 User’s Manual for a more
detailed functional description.
8.1 Enhanced CPU
The P89LPC920/921/922/9221 uses an enhanced 80C51 CPU which runs at 6 times
the speed of standard 80C51 devices. A machine cycle consists of two CPU clock
cycles, and most instructions execute in one or two machine cycles.
8.2 Clocks
8.2.1
Clock definitions
The P89LPC920/921/922/9221 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four
clock sources (see Figure 5) and can also be optionally divided to a slower frequency
(see Section 8.7 “CPU Clock (CCLK) modification: DIVM register”).
Note: fosc is defined as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two
or four CCLK cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK/2
8.2.2
CPU clock (OSCCLK)
The P89LPC920/921/922/9221 provides several user-selectable oscillator options in
generating the CPU clock. This allows optimization for a range of needs from high
precision to lowest possible cost. These options are configured when the FLASH is
programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an
oscillator using an external crystal, or an external clock source. The crystal oscillator
can be optimized for low, medium, or high frequency crystals covering a range from
20 kHz to 12 MHz.
8.2.3
Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.
8.2.4
Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
8.2.5
High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until VDD has
reached its specified level. When system power is removed VDD will fall below
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
14 of 46
Philips Semiconductors
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when VDD falls below the minimum
specified operating voltage.
8.2.6
Clock output
The P89LPC920/921/922/9221 supports a user-selectable clock output function on
the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition
occurs if another clock source has been selected (on-chip RC oscillator, watchdog
oscillator, external clock input on X1) and if the Real-Time clock is not using the
crystal oscillator as its clock source. This allows external devices to synchronize to
the P89LPC920/921/922/9221. This output is enabled by the ENCLK bit in the TRIM
register. The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output
is not needed in Idle mode, it may be turned off prior to entering Idle, saving
additional power.
8.3 On-chip RC oscillator option
The P89LPC920/921/922/9221 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ±1% at room
temperature. End-user applications can write to the Trim register to adjust the on-chip
RC oscillator to other frequencies.
8.4 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This
oscillator can be used to save power when a high clock frequency is not needed.
8.5 External clock input option
In this configuration, the processor clock is derived from an external source driving
the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2/P3.0 pin
may be used as a standard port pin or a clock output. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until VDD has
reached its specified level. When system power is removed VDD will fall below
the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when VDD falls below the minimum
specified operating voltage.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
15 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
XTAL1
XTAL2
High freq.
Med. freq.
Low freq.
RTC
OSCCLK
DIVM
RC
OSCILLATOR
CCLK
CPU
÷2
(7.3728 MHz)
WDT
WATCHDOG
OSCILLATOR
(400 kHz)
PCLK
TIMER 0 and
TIMER 1
I2C
BAUD RATE
GENERATOR
UART
002aaa424
Fig 5. Block diagram of oscillator control.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
16 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8.6 CPU Clock (CCLK) wake-up delay
The P89LPC920/921/922/9221 has an internal wake-up timer that delays the clock
until it stabilizes depending to the clock source used. If the clock source is any of the
three crystal selections (low, medium and high frequencies) the delay is
992 OSCCLK cycles plus 60 to 100 µs. If the clock source is either the internal RC
oscillator, watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus
60 to 100 µs.
8.7 CPU Clock (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption. By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
mode by executing its normal program at a lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.
8.8 Low power select
The P89LPC920/921/922/9221 is designed to run at 18 MHz (CCLK) maximum.
However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’
to lower the power consumption further. On any reset, CLKLP is ‘0’ allowing highest
performance access. This bit can then be set in software if CCLK is running at 8 MHz
or slower.
8.9 Memory organization
The various P89LPC920/921/922/9221 memory spaces are as follows:
• DATA
128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect
addressing, using instruction other than MOVX and MOVC. All or part of the Stack
may be in this area.
• IDATA
Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of
the Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it.
• SFR
Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing.
• CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC920/921/922/9221 has 2 kB/4 kB/8 kB of on-chip
Code memory.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
17 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8.10 Data RAM arrangement
The 256 bytes of on-chip RAM are organized as shown in Table 5.
Table 5:
On-chip data memory usages
Type
Data RAM
Size (bytes)
DATA
Memory that can be addressed directly and indirectly
128
IDATA
Memory that can be addressed indirectly
256
8.11 Interrupts
The P89LPC920/921/922/9221 uses a four priority level interrupt structure. This
allows great flexibility in controlling the handling of the many interrupt sources. The
P89LPC920/921/922/9221 supports 12 interrupt sources: external interrupts 0 and 1,
timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout
detect, watchdog/real-time clock, I2C, keyboard, and comparators 1 and 2.
Each interrupt source can be individually enabled or disabled by setting or clearing a
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but not by another interrupt of the same or lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.
8.11.1
External interrupt inputs
The P89LPC920/921/922/9221 has two external interrupt inputs as well as the
Keypad Interrupt function. The two interrupt inputs are identical to those present on
the standard 80C51 microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered
by setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode if successive samples of the INTn pin show a HIGH in one
cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set,
causing an interrupt request.
If an external interrupt is enabled when the P89LPC920/921/922/9221 is put into
Power-down or Idle mode, the interrupt will cause the processor to wake-up and
resume operation. Refer to Section 8.14 “Power reduction modes” for details.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
18 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
IE0
EX0
IE1
EX1
BOF
EBO
RTCF
ERTC
(RTCCON.1)
WDOVF
WAKE-UP
(IF IN POWER-DOWN)
KBIF
EKBI
EWDRT
CMF2
CMF1
EC
EA (IE0.7)
TF0
ET0
TF1
ET1
TI & RI/RI
ES/ESR
INTERRUPT
TO CPU
TI
EST
SI
EI2C
002aaa418
Fig 6. Interrupt sources, interrupt enables, and power-down wake-up sources.
8.12 I/O ports
The P89LPC920/921/922/9221 has three I/O ports: Port 0, Port 1, and Port 3. Ports 0
and 1 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available
depend upon the clock and reset options chosen, as shown in Table 6.
Table 6:
Number of I/O pins available
Clock source
Reset option
Number of I/O pins
(20-pin package)
On-chip oscillator or
watchdog oscillator
No external reset (except during power-up)
18
External RST pin supported[1]
17
External clock input
No external reset (except during power-up)
17
External RST pin
Low/medium/high
speed oscillator
(external crystal or
resonator)
[1]
8.12.1
supported[1]
16
No external reset (except during power-up)
16
External RST pin supported[1]
15
Required for operation above 12 MHz.
Port configurations
All but three I/O port pins on the P89LPC920/921/922/9221 may be configured by
software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional
(standard 80C51 port outputs), push-pull, open drain, and input-only. Two
configuration registers for each port select the output type for each port pin.
P1.5 (RST) can only be an input and cannot be configured.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
19 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or
open-drain.
8.12.2
Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the
need to reconfigure the port. This is possible because when the port outputs a logic
HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the
pin is driven LOW, it is driven strongly and able to sink a fairly large current. These
features are somewhat similar to an open-drain output except that there are three
pull-up transistors in the quasi-bidirectional output that serve different purposes.
The P89LPC920/921/922/9221 is a 3 V device, but the pins are 5 V-tolerant. In
quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current
flowing from the pin to VDD, causing extra power consumption. Therefore, applying
5 V in quasi-bidirectional mode is discouraged.
A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
8.12.3
Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the
pull-down transistor of the port driver when the port latch contains a logic ‘0’. To be
used as a logic output, a port configured in this manner must have an external
pull-up, typically a resistor tied to VDD.
An open-drain port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
8.12.4
Input-only configuration
The input-only port configuration has no output drivers. It is a Schmitt-triggered input
that also has a glitch suppression circuit.
8.12.5
Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous
strong pull-up when the port latch contains a logic ‘1’. The push-pull mode may be
used when more source current is needed from a port output. A push-pull port pin
has a Schmitt-triggered input that also has a glitch suppression circuit. The
P89LPC9221 device has high source current on eight pins in push-pull mode. See
Table 8 “DC electrical characteristics”.
8.12.6
Port 0 analog functions
The P89LPC920/921/922/9221 incorporates two Analog Comparators. In order to
give the best analog function performance and to minimize power consumption, pins
that are being used for analog functions must have the digital outputs and digital
inputs disabled.
Digital outputs are disabled by putting the port output into the Input-Only (high
impedance) mode as described in Section 8.12.4.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register,
bits 1:5. On any reset, PT0AD1:5 defaults to ‘0’s to enable digital functions.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
20 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8.12.7
Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different
from the LPC76x series of devices.
• After power-up, all I/O pins except P1.5, may be configured by software.
• Pin P1.5 is input only. Pins P1.2 and P1.3 and are configurable for either input-only
or open-drain.
Every output on the P89LPC920/921/922/9221 has been designed to sink typical
LED drive current. However, there is a maximum total output current for all ports
which must not be exceeded. Please refer to Table 8 “DC electrical characteristics” for
detailed specifications.
All ports pins that can function as an output have slew rate controlled outputs to limit
noise generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
8.13 Power monitoring functions
The P89LPC920/921/922/9221 incorporates power monitoring functions designed to
prevent incorrect operation during initial power-up and power loss or reduction during
operation. This is accomplished with two hardware functions: Power-on Detect and
Brownout detect.
8.13.1
Brownout detection
The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor
reset, however it may alternatively be configured to generate an interrupt.
Brownout detection may be enabled or disabled in software.
If Brownout detection is enabled, the brownout condition occurs when VDD falls below
the brownout trip voltage, VBO (see Table 8 “DC electrical characteristics”), and is
negated when VDD rises above VBO. If the P89LPC920/921/922/9221 device is to
operate with a power supply that can be below 2.7 V, BOE should be left in the
unprogrammed state so that the device can operate at 2.4 V, otherwise continuous
brownout reset may prevent the device from operating.
For correct activation of Brownout detect, the VDD rise and fall times must be
observed. Please see Table 8 “DC electrical characteristics” for specifications.
8.13.2
Power-on detection
The Power-on Detect has a function similar to the Brownout detect, but is designed to
work as power comes up initially, before the power supply voltage reaches a level
where Brownout detect can work. The POF flag in the RSTSRC register is set to
indicate an initial power-up condition. The POF flag will remain set until cleared by
software.
8.14 Power reduction modes
The P89LPC920/921/922/9221 supports three different power reduction modes.
These modes are Idle mode, Power-down mode, and total Power-down mode.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
21 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8.14.1
Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate
Idle mode.
8.14.2
Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption.
The P89LPC920/921/922/9221 exits Power-down mode via any reset, or certain
interrupts. In Power-down mode, the power supply voltage may be reduced to the
RAM keep-alive voltage VRAM. This retains the RAM contents at the point where
Power-down mode was entered. SFR contents are not guaranteed after VDD has
been lowered to VRAM, therefore it is highly recommended to wake up the processor
via reset in this case. VDD must be raised to within the operating range before the
Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down. These include: Brownout detect,
Watchdog Timer, Comparators (note that Comparators can be powered-down
separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is
disabled unless both the RC oscillator has been selected as the system clock AND
the RTC is enabled.
8.14.3
Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry
and the voltage comparators are also disabled to conserve additional power. The
internal RC oscillator is disabled unless both the RC oscillator has been selected as
the system clock and the RTC is enabled. If the internal RC oscillator is used to clock
the RTC during Power-down, there will be high power consumption. Please use an
external low frequency clock to achieve low power with the Real-Time Clock running
during Power-down.
8.15 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital
input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the
external reset input function on P1.5. When cleared, P1.5 may be used as an input
pin.
Remark: During a power-up sequence, the RPE selection is overridden and this pin
will always function as a reset input. An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset. After power-up this input will function either as an external reset
input or as a digital input as defined by the RPE bit. Only a power-up reset will
temporarily override the selection defined by RPE bit. Other sources of reset will not
override the RPE bit.
Remark: During a power cycle, VDD must fall below VPOR (see Table 8 “DC electrical
characteristics” on page 36) before power is reapplied, in order to ensure a power-on
reset.
Reset can be triggered from the following sources:
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
22 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
• External reset pin (during power-up or if user configured via UCFG1). This option
must be used for an oscillator frequency above 12 MHz);
•
•
•
•
•
Power-on detect;
Brownout detect;
Watchdog Timer;
Software reset;
UART break character detect reset.
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can
read this register to determine the most recent reset source. These flag bits can be
cleared in software by writing a ‘0’ to the corresponding bit. More than one flag bit
may be set:
• During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
• For any other reset, previously set flag bits that have not been cleared will remain
set.
8.15.1
Reset vector
Following reset, the P89LPC920/921/922/9221 will fetch instructions from either
address 0000h or the Boot address. The Boot address is formed by using the Boot
Vector as the high byte of the address and the low byte of the address = 00h.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on
(see P89LPC920/921/922/9221 User’s Manual). Otherwise, instructions will be
fetched from address 0000H.
8.16 Timers/counters 0 and 1
The P89LPC920/921/922/9221 has two general purpose counter/timers which are
upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be
configured to operate either as timers or event counter. An option to automatically
toggle the T0 and/or T1 pins upon timer overflow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition
at its corresponding external input pin, T0 or T1. In this function, the external input is
sampled once during every machine cycle.
Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1,
2 and 6 are the same for both Timers/Counters. Mode 3 is different.
8.16.1
Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured
as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
8.16.2
Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
23 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8.16.3
Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload.
Mode 2 operation is the same for Timer 0 and Timer 1.
8.16.4
Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When
Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.
8.16.5
Mode 6
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.
8.16.6
Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a
timer overflow occurs. The same device pins that are used for the T0 and T1 count
inputs are also used for the timer toggle outputs. The port outputs will be a logic 1
prior to the first timer overflow when this mode is turned on.
8.17 Real-Time clock/system timer
The P89LPC920/921/922/9221 has a simple Real-Time clock that allows a user to
continue running an accurate timer while the rest of the device is powered-down. The
Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a
23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down
counter. When it reaches all ‘0’s, the counter will be reloaded again and the RTCF
flag will be set. The clock source for this counter can be either the CPU clock (CCLK)
or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU
clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as
its clock source. Only power-on reset will reset the Real-Time clock and its
associated SFRs to the default state.
8.18 UART
The P89LPC920/921/922/9221 has an enhanced UART that is compatible with the
conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud
rate source. The P89LPC920/921/922/9221 does include an independent Baud Rate
Generator. The baud rate can be selected from the oscillator (divided by a constant),
Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud
rate generation, enhancements over the standard 80C51 UART include Framing
Error detection, automatic address recognition, selectable double buffering and
several interrupt options.The UART can be operated in 4 modes: shift register, 8-bit
UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
8.18.1
Mode 0
Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at 1⁄16 of the CPU clock
frequency.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
24 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8.18.2
Mode 1
10 bits are transmitted (through TxD) or received (through RxD): a start bit
(logical ‘0’), 8 data bits (LSB first), and a stop bit (logical ‘1’). When data is received,
the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is
variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator
(described in Section 8.18.5 “Baud rate generator and selection”).
8.18.3
Mode 2
11 bits are transmitted (through TxD) or received (through RxD): start bit (logical ‘0’),
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical ‘1’). When
data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of ‘0’ or
‘1’. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When
data is received, the 9th data bit goes into RB8 in Special Function Register SCON,
while the stop bit is not saved. The baud rate is programmable to either 1⁄16 or 1⁄32 of
the CPU clock frequency, as determined by the SMOD1 bit in PCON.
8.18.4
Mode 3
11 bits are transmitted (through TxD) or received (through RxD): a start bit
(logical ‘0’), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit
(logical ‘1’). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate.
The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or
the Baud Rate Generator (described in Section 8.18.5 “Baud rate generator and
selection”).
8.18.5
Baud rate generator and selection
The P89LPC920/921/922/9221 enhanced UART has an independent Baud Rate
Generator. The baud rate is determined by a baud-rate preprogrammed into the
BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that
works in a similar manner as Timer 1 but is much more accurate. If the baud rate
generator is used, Timer 1 can be used for other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 7).
Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is set. The
independent Baud Rate Generator uses OSCCLK.
Timer 1 Overflow
(PCLK-based)
SMOD1 = 1
¸2
SBRGS = 0
Baud Rate Modes 1 and 3
SMOD1 = 0
Baud Rate Generator
(CCLK-based)
SBRGS = 1
002aaa419
Fig 7. Baud rate sources for UART (Modes 1, 3).
8.18.6
Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0
(PCON.6) is ‘1’, framing errors can be made available in SCON.7 respectively. If
SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)
are set up when SMOD0 is ‘0’.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
25 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8.18.7
Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the
device and force the device into ISP mode.
8.18.8
Double buffering
The UART has a transmit double buffer that allows buffering of the next character to
be written to SBUF while the first character is being transmitted. Double buffering
allows transmission of a string of characters with only one stop bit between any two
characters, as long as the next character is written between the start bit and the stop
bit of the previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = ‘0’), the UART
is compatible with the conventional 80C51 UART. If enabled, the UART allows writing
to SnBUF while the previous data is being shifted out. Double buffering is only
allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be
disabled (DBMOD = ‘0’).
8.18.9
Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated
when the double buffer is ready to receive new data.
8.18.10
The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as
long as TB8 is updated some time before that bit is shifted out. TB8 must not be
changed until the bit is shifted out, as indicated by the Tx interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8
will be double-buffered together with SBUF data.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
26 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8.19 I2C-bus serial interface
I2C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
• Bidirectional data transfer between masters and slaves
• Multimaster bus (no central master)
• Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
• Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus
• Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer
• The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus configuration is shown in Figure 8. The P89LPC920/921/922/9221
device provides a byte-oriented I2C-bus interface that supports data transfers up to
400 kHz.
RP
RP
SDA
I2C-BUS
SCL
P1.3/SDA
P1.2/SCL
P89LPC920/921/922
OTHER DEVICE
WITH I2C-BUS
INTERFACE
OTHER DEVICE
WITH I2C-BUS
INTERFACE
002aaa420
Fig 8. I2C-bus configuration.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
27 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8
I2ADR
ADDRESS REGISTER
INTERNAL BUS
P1.3
COMPARATOR
INPUT
FILTER
P1.3/SDA
SHIFT REGISTER
OUTPUT
STAGE
ACK
I2DAT
8
BIT COUNTER /
ARBITRATION &
SYNC LOGIC
INPUT
FILTER
P1.2/SCL
SERIAL CLOCK
GENERATOR
OUTPUT
STAGE
CCLK
TIMING
&
CONTROL
LOGIC
INTERRUPT
TIMER 1
OVERFLOW
P1.2
I2CON
I2SCLH
I2SCLL
CONTROL REGISTERS &
SCL DUTY CYCLE REGISTERS
8
STATUS BUS
I2STAT
STATUS
DECODER
STATUS REGISTER
8
002aaa421
Fig 9. I2C-bus serial interface block diagram.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
28 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8.20 Analog comparators
Two analog comparators are provided on the P89LPC920/921/922/9221. Input and
output options allow use of the comparators in a number of different configurations.
Comparator operation is such that the output is a logical one (which may be read in a
register and/or routed to a pin) when the positive input (one of two selectable pins) is
greater than the negative input (selectable from a pin or an internal reference
voltage). Otherwise the output is a zero. Each comparator may be configured to
cause an interrupt when the output value changes.
The overall connections to both comparators are shown in Figure 10. The
comparators function to VDD = 2.4 V.
When each comparator is first enabled, the comparator output and interrupt flag are
not guaranteed to be stable for 10 microseconds. The corresponding comparator
interrupt should not be enabled during that time, and the comparator interrupt flag
must be cleared before the interrupt is enabled in order to prevent an immediate
interrupt service.
When a comparator is disabled the comparator’s output, COx, goes HIGH. If the
comparator output was LOW and then is disabled, the resulting transition of the
comparator output from a LOW to HIGH state will set the comparator flag, CMFx.
This will cause an interrupt if the comparator interrupt is enabled. The user should
therefore disable the comparator interrupt prior to disabling the comparator.
Additionally, the user should clear the comparator flag, CMFx, after disabling the
comparator.
CP1
Comparator 1
OE1
(P0.4) CIN1A
(P0.3) CIN1B
CO1
CMP1 (P0.6)
(P0.5) CMPREF
Change Detect
VREF
CMF1
CN1
Interrupt
Change Detect
CP2
Comparator 2
EC
CMF2
(P0.2) CIN2A
(P0.1) CIN2B
CMP2 (P0.0)
CO2
OE2
002aaa422
CN2
Fig 10. Comparator input and output connections.
8.20.1
Internal reference voltage
An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to
as VREF, is 1.23 V ±10%.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
29 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8.20.2
Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag
is set whenever the comparator output changes state. The flag may be polled by
software or may be used to generate an interrupt. The two comparators use one
common interrupt vector. If both comparators enable interrupts, after entering the
interrupt service routine, the user needs to read the flags to determine which
comparator caused the interrupt.
8.20.3
Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is
activated, but both comparators are disabled automatically in Total Power-down
mode. If a comparator interrupt is enabled (except in Total Power-down mode), a
change of the comparator output state will generate an interrupt and wake up the
processor. If the comparator output to a pin is enabled, the pin should be configured
in the push-pull mode in order to obtain fast switching times while in Power-down
mode. The reason is that with the oscillator stopped, the temporary strong pull-up that
normally occurs during switching on a quasi-bidirectional port pin does not take
place.
Comparators consume power in Power-down and Idle modes, as well as in the
normal operating mode. This fact should be taken into account when system power
consumption is an issue. To minimize power consumption, the user can disable the
comparators via PCONA.5, or put the device in Total Power-down mode.
8.21 Keypad interrupt (KBI)
The Keypad Interrupt function is intended primarily to allow a single interrupt to be
generated when Port 0 is equal to or not equal to a certain pattern. This function can
be used for bus address recognition or keypad recognition. The user can configure
the port via SFRs for different tasks.
The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins
connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN)
is used to define a pattern that is compared to the value of Port 0. The Keypad
Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when
the condition is matched while the Keypad Interrupt function is active. An interrupt will
be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register
(KBCON) is used to define equal or not-equal for the comparison.
In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x
series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then
any key connected to Port 0 which is enabled by the KBMASK register will cause the
hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt
may be used to wake up the CPU from Idle or Power-down modes. This feature is
particularly useful in handheld, battery-powered systems that need to carefully
manage power consumption yet also need to be convenient to use.
In order to set the flag and cause an interrupt, the pattern on Port 0 must be held
longer than 6 CCLKs.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
30 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8.22 Watchdog timer
The Watchdog timer causes a system reset when it underflows as a result of a failure
to feed the timer prior to the timer reaching its terminal count. It consists of a
programmable 12-bit prescaler, and an 8-bit down counter. The down counter is
decremented by a tap taken from the prescaler. The clock source for the prescaler is
either the PCLK or the nominal 400 kHz Watchdog oscillator. The Watchdog timer
can only be reset by a power-on reset. When the watchdog feature is disabled, it can
be used as an interval timer and may generate an interrupt. Figure 11 shows the
Watchdog timer in watchdog mode. Feeding the watchdog requires a two-byte
sequence. If PCLK is selected as the watchdog clock and the CPU is powered-down,
the watchdog is disabled. The Watchdog timer has a time-out period that ranges from
a few µs to a few seconds. Please refer to the P89LPC920/921/922/9221 User’s
Manual for more details.
WDL (C1H)
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
Watchdog
oscillator
PCLK
÷32
8-BIT DOWN
COUNTER
PRESCALER
RESET
see note (1)
SHADOW
REGISTER
FOR WDCON
CONTROL REGISTER
WDCON (A7H)
PRE2
PRE1
PRE0
–
–
WDRUN
WDTOF
WDCLK
002aaa423
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
feed sequence.
Fig 11. Watchdog timer in watchdog mode (WDTE = ‘1’).
8.23 Additional features
8.23.1
Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor
completely, as if an external reset or watchdog reset had occurred. Care should be
taken when writing to AUXR1 to avoid accidental software resets.
8.23.2
Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects
one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so
that the DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of inadvertently altering other
bits in the register.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
31 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8.24 Flash program memory
8.24.1
General description
The P89LPC920/921/922/9221 Flash memory provides in-circuit electrical erasure
and programming. The Flash can be read, erased, or written as bytes. The Sector
and Page Erase functions can erase any Flash sector (1 kB) or page (64 bytes). The
Chip Erase operation will erase the entire program memory. In-System Programming
and standard parallel programming are both available. On-chip erase and write timing
generation contribute to a user-friendly programming interface. The
P89LPC920/921/922/9221 Flash reliably stores memory contents even after
10,000 erase and program cycles. The cell is designed to optimize the erase and
programming mechanisms. The P89LPC920/921/922/9221 uses VDD as the supply
voltage to perform the Program/Erase algorithms.
8.24.2
Features
• Parallel programming with industry-standard commercial programmers.
• In-Circuit serial Programming (ICP) with industry-standard commercial
programmers.
• IAP-Lite allows individual and multiple bytes of code memory to be used for data
storage and programmed under control of the end application.
• Internal fixed boot ROM, containing low-level In-Application Programming (IAP)
routines that can be called from the end application (in addition to IAP-Lite).
• Default serial loader providing In-System Programming (ISP) via the serial port,
located in upper end of user program memory.
• Boot vector allows user-provided Flash loader code to reside anywhere in the
Flash memory space, providing flexibility to the user.
•
•
•
•
•
•
8.24.3
Programming and erase over the full operating voltage range.
Read/Programming/Erase using ISP/IAP/IAP-Lite.
Any flash program or erase operation in 2 ms.
Programmable security for the code in the Flash for each sector.
>100,000 typical erase/program cycles for each byte.
10 year minimum data retention.
ISP and IAP capabilities of the P89LPC920/921/922/9221
Flash organization: The P89LPC920/921/922/9221 program memory consists of
two/four/eight 1 kB sectors. Each sector can be further divided into 64-byte pages. In
addition to sector erase, page erase, and byte erase, a 64-byte page register is
included which allows from 1 to 64 bytes of a given page to be programmed at the
same time, substantially reducing overall programming time. An In-Application
Programming (IAP) interface is provided to allow the end user’s application to erase
and reprogram the user code memory. In addition, erasing and reprogramming of
user-programmable bytes including UCFG1, the Boot Status Bit and the Boot Vector
are supported. As shipped from the factory, the upper 512 bytes of user code space
contains a serial In-System Programming (ISP) routine allowing for the device to be
programmed in circuit through the serial port.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
32 of 46
Philips Semiconductors
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
Flash programming and erasing: There are three methods of erasing or
programming of the Flash memory that may be used. First, the Flash may be
programmed or erased in the end-user application by calling low-level routines
through a common entry point. Second, the on-chip ISP boot loader may be invoked.
This ISP boot loader will, in turn, call low-level routines through the same common
entry point that can be used by the end-user application. Third, the Flash may be
programmed or erased using the parallel method by using a commercially available
EPROM programmer which supports this device. This device does not provide for
direct verification of code memory contents. Instead this device provides a 32-bit
CRC result on either a sector or the entire 2 kB/4 kB/8 kB of user code space.
Boot ROM: When the microcontroller programs its own Flash memory, all of the
low-level details are handled by code that is contained in a Boot ROM that is separate
from the Flash memory. A user program simply calls the common entry point in the
Boot ROM with appropriate parameters to accomplish the desired operation. The
Boot ROM include operations such as erase sector, erase page, program page, CRC,
program security bit, etc. The Boot ROM occupies the program memory space at the
top of the address space from FF00H to FEFFH, thereby not conflicting with the user
program memory space.
Power-on reset code execution: The P89LPC920/921/922/9221 contains two
special Flash elements: the Boot Vector and the Boot Status Bit. Following reset, the
P89LPC920/921/922/9221 examines the contents of the Boot Status Bit. If the Boot
Status Bit is set to zero, power-up execution starts at location 0000H, which is the
normal start address of the user’s application code. When the Boot Status Bit is set to
a one, the contents of the Boot Vector is used as the high byte of the execution
address and the low byte is set to 00H. The factory default setting is 1FH for the
P89LPC9221 and P89LPC922, and corresponds to the address 1F00H for the default
ISP boot loader. The factory default setting is 0FH for the P89LPC921 and
corresponds to the address 0F00H for the default ISP boot loader. The factory default
setting for the LPC920 is 07H and corresponds to the address 0700H. This boot
loader is pre-programmed at the factory into this address space and can be erased
by the user. Users who wish to use this loader should take precautions to avoid
erasing the 1 kB sector from 1C00H to 1FFFH in the P89LPC922/9221 or the
1 kB sector from 0C00H to 0FFFH in the P89LPC921, or the 1 kB sector from
0400H to 07FFH in the P89LPC920. Instead, the page erase function can be
used to erase the eight 64-byte pages which comprise the lower 512 bytes of
the sector. A custom boot loader can be written with the Boot Vector set to the
custom boot loader, if desired.
Hardware activation of the boot loader: The boot loader can also be executed by
forcing the device into ISP mode during a power-on sequence (see the
P89LPC920/921/922/9221 User’s Manual for specific information). This has the same
effect as having a non-zero Boot Status Bit. This allows an application to be built that
will normally execute user code but can be manually forced into ISP operation. If the
factory default setting for the Boot Vector is changed, it will no longer point to the
factory pre-programmed ISP boot loader code. If this happens, the only way it is
possible to change the contents of the Boot Vector is through the parallel
programming method, provided that the end user application does not contain a
customized loader that provides for erasing and reprogramming of the Boot Vector
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
33 of 46
Philips Semiconductors
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
and Boot Status Bit. After programming the Flash, the Boot Status Bit should be
programmed to zero in order to allow execution of the user’s application code
beginning at address 0000H.
In-System Programming (ISP): In-System Programming is performed without
removing the microcontroller from the system. The In-System Programming facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89LPC920/921/922/9221 through the serial
port. This firmware is provided by Philips and embedded within each
P89LPC920/921/922/9221 device. The Philips In-System Programming facility has
made in-system programming in an embedded application possible with a minimum
of additional expense in components and circuit board area. The ISP function uses
five pins (VDD, VSS, TXD, RXD, and RST). Only a small connector needs to be
available to interface your application to an external circuit in order to use this feature.
Please see the P89LPC920/921/922/9221 User’s Manual for additional details.
In-Application Programming (IAP): Several In-Application Programming (IAP) calls
are available for use by an application program to permit selective erasing and
programming of Flash sectors, pages, security bits, configuration bytes, and device
identification. All calls are made through a common interface, PGM_MTP. The
programming functions are selected by setting up the microcontroller’s registers
before making a call to PGM_MTP at FF00H. Please see the
P89LPC920/921/922/9221 User’s Manual for additional details.
In-Circuit Programming (ICP): In-Circuit Programming is a method intended to
allow commercial programmers to program and erase these devices without
removing the microcontroller from the system. The In-Circuit Programming facility
consists of a series of internal hardware resources to facilitate remote programming
of the P89LPC920/921/922/9221 through a two-wire serial interface. Philips has
made in-circuit programming in an embedded application possible with a minimum of
additional expense in components and circuit board area. The ICP function uses five
pins (VDD, VSS, P0.5, P0.4, and RST). Only a small connector needs to be available
to interface your application to an external programmer in order to use this feature.
8.25 User configuration bytes
A number of user-configurable features of the P89LPC920/921/922/9221 must be
defined at power-up and therefore cannot be set by the program after start of
execution. These features are configured through the use of the Flash byte UCFG1.
Please see the P89LPC920/921/922/9221 User’s Manual for additional details.
8.26 User sector security bytes
There are two/four/eight User Sector Security Bytes, each corresponding to one
sector. Please see the P89LPC920/921/922/9221 User’s Manual for additional
details.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
34 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
9. Limiting values
Table 7:
Limiting values[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Tamb(bias)
Conditions
Min
Max
Unit
operating bias ambient temperature
−55
+125
°C
Tstg
storage temperature range
−65
+150
°C
Vxtal
voltage on XTAL1, XTAL2 pin to VSS
-
VDD + 0.5
V
Vn
voltage on any other pin to VSS
−0.5
+5.5
V
IOH(I/O)
HIGH-level output current per I/O pin, P0.3 to P0.7, P1.4, P1.6,
P89LPC9221
P1.7
-
20
mA
-
8
mA
HIGH-level output current per I/O pin,
P89LPC920/921/922
-
8
mA
IOL(I/O)
LOW-level output current per I/O pin
-
20
mA
II/O(tot)(max)
maximum total I/O current,
P89LPC9221
-
160
mA
maximum total I/O current,
P89LPC920/921/922
-
80
mA
-
1.5
W
all other I/O pins
Ptot(pack)
[1]
total power dissipation per package
based on package heat
transfer, not device power
consumption
The following applies to Limiting values:
a) Stresses above those listed under Table 7 may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any conditions other than those described in Table 8 “DC electrical characteristics”, Table 9 “AC
characteristics” and Table 10 “AC characteristics” of this specification are not implied.
b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
35 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
10. Static characteristics
Table 8:
DC electrical characteristics
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, unless otherwise specified.
Symbol
IDD(oper)
IDD(idle)
Parameter
power supply current, operating
power supply current, Idle mode
Min
Typ[1]
Max
Unit
3.6 V; 12 MHz
[2]
-
9
15
mA
3.6 V; 18 MHz
[2]
-
11.5
20
mA
3.6 V; 12 MHz
[2]
-
3.25
5
mA
3.6 V; 18 MHz
[2]
-
5
7
mA
-
55
80
µA
-
1
5
µA
Conditions
IDD(PD)
power supply current, Power-down 3.6 V
mode, voltage comparators
powered-down
[2]
IDD(TPD)
power supply current, Total
Power-down mode
[2]
(dVDD/dt)r
VDD rise rate
-
-
2
mV/µs
(dVDD/dt)f
VDD fall rate
-
-
50
mV/µs
VPOR
Power-on reset detect voltage
-
-
0.2
V
VRAM
RAM keep-alive voltage
1.5
-
-
V
Vth(HL)
negative-going threshold voltage
except SCL, SDA
0.22VDD
0.4VDD
-
V
VIL
LOW-level input voltage
SCL, SDA only
−0.5
-
0.3VDD
V
Vth(LH)
positive-going threshold voltage
except SCL, SDA
-
0.6VDD
0.7VDD
V
VIH
HIGH-level input voltage
SCL, SDA only
0.7VDD
-
5.5
V
Vhys
hysteresis voltage
Port 1
-
0.2VDD
-
V
VOL
LOW-level output voltage; all ports, IOL = 20 mA
all modes except Hi-Z[3]
IOL = 3.2 mA
-
0.6
1.0
V
-
0.2
0.3
V
IOH = −20 mA;
push-pull mode P0.3
to P0.7, P1.4, P1.6,
P1.7
0.8VDD
-
-
V
IOH = −3.2 mA;
push-pull mode, all
other ports
VDD − 0.7 VDD − 0.4 -
V
IOH = −20 µA;
quasi-bidirectional
mode, all ports
VDD − 0.3 VDD − 0.2 -
V
VOH
Cig
IIL
ILI
HIGH-level output voltage
3.6 V
input/output pin capacitance
[4]
-
-
15
pF
logical 0 input current, all ports
VIN = 0.4 V
[5]
-
-
−80
µA
VIN = VIL or VIH
[6]
-
-
±10
µA
−30
-
−450
µA
10
-
30
kΩ
input leakage current, all ports
ITL
logical 1-to-0 transition current,
all ports
RRST
internal reset pull-up resistor
VIN = 2.0 V at
VDD = 3.6 V
[7], [8]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
36 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
Table 8:
DC electrical characteristics…continued
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VBO
brownout trip voltage with
BOV = ‘0’, BOPD = ‘1’
2.4 V < VDD < 3.6 V
2.40
-
2.70
V
VREF
bandgap reference voltage
1.11
1.23
1.34
V
TC(VREF)
bandgap temperature coefficient
-
10
20
ppm/°C
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.
The IDD(oper), IDD(idle), and IDD(PD) specifications are measured using an external clock with the following functions disabled: comparators,
brownout detect, and Watchdog timer.
See Table 7 “Limiting values[1]” on page 35 for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition,
VOL/VOH may exceed the related specification.
Pin capacitance is characterized but not tested.
Measured with port in quasi-bidirectional mode.
Measured with port in high-impedance mode.
Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). Does not apply to open-drain pins.
Port pins source a transition current when used in quasi-bidirectional mode and externally driven from ‘1’ to ‘0’. This current is highest
when VIN is approximately 2 V.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
37 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
11. Dynamic characteristics
Table 9:
AC characteristics
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, unless otherwise specified.[1]
Symbol
Parameter
Conditions
Variable clock
Min
Max
Min
Max
fRCOSC
internal RC oscillator frequency
(nominal f = 7.3728 MHz)
trimmed to ±1%
at Tamb = 25 °C
7.189
7.557
7.189
7.557
MHz
fWDOSC
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
320
520
320
520
kHz
fosc
oscillator frequency
tCLCL
clock cycle
fCLKP
CLKLP active frequency
see Figure 13
fosc = 12 MHz
Unit
0
12
-
-
MHz
83
-
-
-
ns
0
8
-
-
MHz
Glitch filter
glitch rejection, P1.5/RST pin
-
50
-
50
ns
signal acceptance, P1.5/RST pin
125
-
125
-
ns
glitch rejection, any pin except
P1.5/RST
-
15
-
15
ns
signal acceptance, any pin except
P1.5/RST
50
-
50
-
ns
External clock
tCHCX
HIGH time
see Figure 13
33
tCLCL − tCLCX
33
-
ns
tCLCX
LOW time
see Figure 13
33
tCLCL − tCHCX
33
-
ns
tCLCH
rise time
see Figure 13
-
8
-
8
ns
tCHCL
fall time
see Figure 13
-
8
-
8
ns
Shift register (UART mode 0)
tXLXL
serial port clock cycle time
16 tCLCL
-
1333
-
ns
tQVXH
output data set-up to clock rising
edge
13 tCLCL
-
1083
-
ns
tXHQX
output data hold after clock rising
edge
-
tCLCL + 20
-
103
ns
tXHDX
input data hold after clock rising edge
-
0
-
0
ns
tDVXH
input data valid to clock rising edge
150
-
150
-
ns
[1]
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
38 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
Table 10: AC characteristics
VDD = 3.0 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, unless otherwise specified.[1]
Symbol
Parameter
Variable clock
fosc = 18 MHz
Min
Max
Min
Max
7.189
7.557
7.189
7.557
MHz
320
520
320
520
kHz
0
18
-
-
MHz
55
-
-
-
ns
0
8
-
-
MHz
glitch rejection, P1.5/RST pin
-
50
-
50
ns
signal acceptance, P1.5/RST pin
125
-
125
-
ns
glitch rejection, any pin except
P1.5/RST
-
15
-
15
ns
signal acceptance, any pin except
P1.5/RST
50
-
50
-
ns
tCLCL − tCLCX
22
-
ns
fRCOSC
internal RC oscillator frequency
(nominal f = 7.3728 MHz)
fWDOSC
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
fosc
oscillator frequency
tCLCL
clock cycle
fCLKP
CLKLP active frequency
Conditions
trimmed to ±1%
at Tamb = 25 °C
[2]
see Figure 13
Unit
Glitch filter
External clock
tCHCX
HIGH time
see Figure 13
22
tCLCX
LOW time
see Figure 13
22
tCLCL − tCHCX
22
-
ns
tCLCH
rise time
see Figure 13
-
5
-
5
ns
tCHCL
fall time
see Figure 13
-
5
-
5
ns
Shift register (UART mode 0)
tXLXL
serial port clock cycle time
16 tCLCL
-
888
-
ns
tQVXH
output data set-up to clock rising
edge
13 tCLCL
-
722
-
ns
tXHQX
output data hold after clock rising
edge
-
tCLCL + 20
-
75
ns
tXHDX
input data hold after clock rising edge
-
0
-
0
ns
tDVXH
input data valid to clock rising edge
150
-
150
-
ns
[1]
[2]
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the
minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout
detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
39 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
tXLXL
Clock
tXHQX
tQVXH
Output Data
0
Write to SBUF
Input Data
1
2
3
4
5
6
7
tXHDX
tXHDV
Set TI
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Clear RI
Set RI
002aaa425
Fig 12. Shift register mode timing.
VDD - 0.5 V
0.2 VDD + 0.9
0.2 VDD - 0.1 V
0.45 V
tCHCX
tCHCL
tCLCX
tCLCH
tC
002aaa416
Fig 13. External clock timing.
Table 11: AC characteristics, ISP entry mode
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
tVR
RST delay from VDD active
Conditions
50
-
-
µs
tRH
RST HIGH time
1
-
32
µs
tRL
RST LOW time
1
-
-
µs
VDD
tVR
tRH
RST
002aaa426
tRL
Fig 14. ISP entry waveform.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
40 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
12. Comparator electrical characteristics
Table 12: Comparator electrical characteristics
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, unless otherwise specified.
Symbol
Parameter
VIO
VCR
CMRR
common mode rejection ratio
Conditions
Min
Typ
Max
offset voltage comparator inputs
-
-
±20
mV
common mode range comparator inputs
0
-
VDD − 0.3
V
-
-
−50
dB
-
250
500
ns
[1]
response time
comparator enable to output valid
input leakage current, comparator
IIL
[1]
0 < VIN < VDD
Unit
-
-
10
µs
-
-
±10
µA
This parameter is characterized, but not tested in production.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
41 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
13. Package outline
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
E
D
A
X
c
HE
y
v M A
Z
11
20
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
10
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
SOT360-1
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 15. TSSOP20 (SOT360-1).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
42 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
b1
w M
(e 1)
b
MH
11
20
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
inches
0.17
0.02
0.13
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
D
e
e1
L
ME
MH
w
Z (1)
max.
6.40
6.22
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
2
0.25
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.078
(1)
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
SOT146-1
REFERENCES
IEC
JEDEC
JEITA
MS-001
SC-603
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Fig 16. DIP20 (SOT146-1).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
43 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
14. Revision history
Table 13:
Revision history
Rev Date
08
20041215
CPCN
Description
-
Product data (9397 750 14469)
Modification:
•
Added 18 MHz information.
07
20041203
-
Product data (9397 750 14251)
06
20031121
-
Product data (9397 750 12285); ECN 853-2403 01-A14557 of 18 November 2003
05
20031007
-
Product data (9397 750 12121); ECN 853-2403 30391 of 30 September 2003
04
20030909
-
Product data (9397 750 11945); ECN 853-2403 30305 of 5 September 2003
03
20030811
-
Preliminary data (9397 750 11786)
02
20030522
-
Objective data (9397 750 11532)
01
20030505
-
Preliminary data (9397 750 11387)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Product data
Rev. 08 — 15 December 2004
44 of 46
P89LPC920/921/922/9221
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
15. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
17. Disclaimers
18. Licenses
Purchase of Philips I2C components
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Purchase of Philips I2C components conveys a license
under the Philips’ I2C patent to use the components in the
I2C system provided the system conforms to the I2C
specification defined by Philips. This specification can be
ordered using the code 9398 393 40011.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected]
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14469
Rev. 08 — 15 December 2004
45 of 46
Philips Semiconductors
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
Contents
1
2
2.1
2.2
3
3.1
4
5
5.1
5.2
6
7
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.11.1
8.12
8.12.1
8.12.2
8.12.3
8.12.4
8.12.5
8.12.6
8.12.7
8.13
8.13.1
8.13.2
8.14
8.14.1
8.14.2
8.14.3
8.15
8.15.1
8.16
8.16.1
8.16.2
8.16.3
8.16.4
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Principal features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Special function registers. . . . . . . . . . . . . . . . . . . . . . 9
Functional description . . . . . . . . . . . . . . . . . . . . . . . 14
Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CPU clock (OSCCLK) . . . . . . . . . . . . . . . . . . . . . . . 14
Low speed oscillator option . . . . . . . . . . . . . . . . . . . 14
Medium speed oscillator option . . . . . . . . . . . . . . . . 14
High speed oscillator option . . . . . . . . . . . . . . . . . . . 14
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
On-chip RC oscillator option . . . . . . . . . . . . . . . . . . 15
Watchdog oscillator option . . . . . . . . . . . . . . . . . . . . 15
External clock input option . . . . . . . . . . . . . . . . . . . . 15
CPU Clock (CCLK) wake-up delay. . . . . . . . . . . . . . 17
CPU Clock (CCLK) modification: DIVM register . . . 17
Low power select . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . 17
Data RAM arrangement . . . . . . . . . . . . . . . . . . . . . . 18
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
External interrupt inputs . . . . . . . . . . . . . . . . . . . . . . 18
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Quasi-bidirectional output configuration. . . . . . . . . . 20
Open-drain output configuration. . . . . . . . . . . . . . . . 20
Input-only configuration . . . . . . . . . . . . . . . . . . . . . . 20
Push-pull output configuration . . . . . . . . . . . . . . . . . 20
Port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . 20
Additional port features . . . . . . . . . . . . . . . . . . . . . . 21
Power monitoring functions . . . . . . . . . . . . . . . . . . . 21
Brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-on detection . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power reduction modes . . . . . . . . . . . . . . . . . . . . . . 21
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Total Power-down mode . . . . . . . . . . . . . . . . . . . . . . 22
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . . . . . 23
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
© Koninklijke Philips Electronics N.V. 2004.
Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 15 December 2004
Document order number: 9397 750 14469
8.16.5
8.16.6
8.17
8.18
8.18.1
8.18.2
8.18.3
8.18.4
8.18.5
8.18.6
8.18.7
8.18.8
8.18.9
Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Timer overflow toggle output. . . . . . . . . . . . . . . . . . . 24
Real-Time clock/system timer. . . . . . . . . . . . . . . . . . 24
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Baud rate generator and selection . . . . . . . . . . . . . . 25
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Transmit interrupts with double buffering
enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . 26
8.18.10
The 9th bit (bit 8) in double buffering (Modes 1, 2 and
3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.19
I2C-bus serial interface . . . . . . . . . . . . . . . . . . . . . . . 27
8.20
Analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.20.1
Internal reference voltage . . . . . . . . . . . . . . . . . . . . . 29
8.20.2
Comparator interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 30
8.20.3
Comparators and power reduction modes . . . . . . . . 30
8.21
Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . . . . . . 30
8.22
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.23
Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.23.1
Software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.23.2
Dual data pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.24
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . 32
8.24.1
General description. . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.24.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.24.3
ISP and IAP capabilities of
the P89LPC920/921/922/9221 . . . . . . . . . . . . . . . . 32
8.25
User configuration bytes . . . . . . . . . . . . . . . . . . . . . . 34
8.26
User sector security bytes . . . . . . . . . . . . . . . . . . . . 34
9
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10
Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 36
11
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 38
12
Comparator electrical characteristics . . . . . . . . . . . 41
13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
18
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45