Freescale Semiconductor, Inc. Chip Errata DSP56156 Digital Signal Processor Mask: E98S/F44E/G68P Freescale Semiconductor, Inc... ERRATA Applies to Mask Errata Description 1. Description: There are three speed grades of the E98S/F44E/G68P silicon of the DSP56156: 40 MHz, 50 MHz, and 60 MHz. These three speed grades are tested as shown in the table below. E98S F44E G68P Table 1 E98S/F44E/G68P Marking and Testing Conditions 40 MHz Characteristic 50 MHz 60 MHz Symbol Unit Min Max Min Max Min Max Supply Voltage VCC 4.75 5.25 4.75 5.25 4.75 5.25 V Junction Temperature TJ — 115 — 115 — 115 °C The PLL is functional and tested at 60 MHz for the speed grades. The codec is functional and tested with a 20 MHz external clock, 0 dB gain on the A/D input and D/A output, and 128 decimation ratio. The A/D is tested with a 0.4 Vrms signal at 1.5 KHz and the D/A with a digitally generated sine wave 50% full scale at 2 KHz. Under those conditions, the SNR and THD of the A/D and D/A are better than 65 dB. 2. Description: The BS signal is being deasserted before TA is deasserted if the BCR is programmed for one or more wait states. In this case, the BS signal ignores the TA signal and is deasserted under control of the BCR even though TA is still active and should cause BS to remain active. This problem occurs at: E98S F44E G68P fOSC = 60 MHz TJ ≥ 25 °C VCC ≥ 5 V This problem has not been fully characterized. Although it has not been reported on parts rated at less than 60 MHz, it has been seen at 50 MHz at 5 V and may be appear at other speeds. Workaround: Insert wait states using either the BCR or the TA signal, but not both. Motorola, Digital Signal Processing Division More 6501 William Cannon Drive West, For Austin, TexasInformation 78735-8598 On This Product, Go to: www.freescale.com pg. 1 /gsp/9/24/96 1994, 1996 Motorola Freescale Semiconductor, Inc. Chip Errata DSP56156 Digital Signal Processor Mask: E98S/F44E/G68P Applies to Mask Errata Description 3. Description: Freescale Semiconductor, Inc... The lock bit detection circuitry in the PLL fails to operate correctly in an overdamped system. E98S F44E G68P Workaround: Use a smaller value capacitor for the SXFC capacitor connection to GND. However, reducing this capacitor value increases PLL jitter. If the resulting jitter level is unacceptable, then switch to a larger capacitor once the lock bit has been asserted. The table below lists the recommended SXFC capacitor values to utilize the lock bit detection circuitry. Table 2 SXFC Size Mask Recommended Value E98S 680 pF F44E 680 pF G68P 390 pF If this second (hardware) fix is not possible within specific design constraints, then, instead of using the operating software to poll the lock bit, insert a simple 5 ms wait into the operating software to allow the PLL to lock before enabling the PLL to the core. NOTES 1. An over-bar (i.e., xxxx) indicates an active-low signal. 2. The letters seen to the right of the errata tell which DSP56156 mask numbers apply. -end- DSP56156 Errata 1994, 1996 Motorola For More Information On This Product, Go to: www.freescale.com pg. 2 /gsp/6/11/97