Data Sheet

P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
1 kB 3 V Flash with 128-byte RAM
Rev. 05 — 17 December 2004
Product data
1. General description
The P89LPC901/902/903 are single-chip microcontrollers in low-cost 8-pin packages,
based on a high performance processor architecture that executes instructions in two
to four clocks, six times the rate of standard 80C51 devices. Many system-level
functions have been incorporated into the P89LPC901/902/903 in order to reduce
component count, board space, and system cost.
2. Features
2.1 Principal features
■ 1 kB byte-erasable Flash code memory organized into 256-byte sectors and
16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage.
■ 128-byte RAM data memory.
■ Two 16-bit counter/timers. (P89LPC901 Timer 0 may be configured to toggle a
port output upon timer overflow or to become a PWM output.)
■ 23-bit system timer that can also be used as a Real-Time clock.
■ Two analog comparators (P89LPC902 and P89LPC903, single analog
comparator on P89LPC901).
■ Enhanced UART with fractional baudrate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities
(P89LPC903).
■ High-accuracy internal RC oscillator option allows operation without external
oscillator components. The RC oscillator (factory calibrated to ±1 %) option is
selectable and fine tunable.
■ 2.4 V to 3.6 V VDD operating range with 5 V tolerant I/O pins (may be pulled up or
driven to 5.5 V). Industry-standard pinout with VDD, VSS, and reset at locations 1,
8, and 4.
■ Up to six I/O pins when using internal oscillator and reset options.
■ 8-pin SO-8 package.
2.2 Additional features
■ A high performance 80C51 CPU provides instruction cycle times of 111 ns to
222 ns for all instructions except multiply and divide when executing at 18 MHz
(167 ns to 333 ns at 12 MHz). This is six times the performance of the standard
80C51 running at the same clock frequency. A lower clock frequency for the same
performance results in power savings and reduced EMI.
■ In-Application Programming (IAP-Lite) and byte erase allows code memory to be
used for non-volatile data storage.
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
■ Serial Flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.
■ Watchdog timer with separate on-chip oscillator, requiring no external
components. The watchdog prescaler is selectable from 8 values.
■ Low voltage reset (Brownout detect) allows a graceful system shutdown when
power fails. May optionally be configured as an interrupt.
■ Idle and two different Power-down reduced power modes. Improved wake-up from
Power-down mode (a low interrupt input starts execution). Typical Power-down
current is 1 µA (total Power-down with voltage comparators disabled).
■ Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.
■ Configurable on-chip oscillator with frequency range options selected by user
programmed Flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz (P89LPC901).
■ Watchdog timer with separate on-chip oscillator, requiring no external
components. The watchdog prescaler is selectable from 8 values.
■ Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
■ Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value
of the pins match or do not match a programmable pattern.
■ LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip.
■ Controlled slew rate port outputs to reduce EMI. Outputs have approximately
10 ns minimum ramp times.
■ Only power and ground connections are required to operate the
P89LPC901/902/903 when internal reset option is selected.
■ Four interrupt priority levels.
■ Two (P89LPC901), three (P89LPC903), or five (P89LPC902) keypad interrupt
inputs.
■ Second data pointer.
■ Schmitt trigger port inputs.
■ Emulation support.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14465
Product data
Rev. 05 — 17 December 2004
2 of 53
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
3. Ordering information
Table 1:
Ordering information
Type number
P89LPC901FD
Package
Name
Description
Version
SO8
plastic small outline package; 8 leads;
body width 7.5 mm
SOT96-1
DIP8
plastic dual in-line package; 8 leads (300 mil) SOT97-1
P89LPC902FD
P89LPC903FD
P89LPC901FN
P89LPC902FN
3.1 Ordering options
Table 2:
Part options
Type number
Temperature range
Frequency
P89LPC901xx
−40 °C to +85 °C
0 MHz to 18 MHz
P89LPC902xx
Internal RC or watchdog
P89LPC903xx
Internal RC or watchdog
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9397 750 14465
Product data
Rev. 05 — 17 December 2004
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P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
4. Block diagram
P89LPC901
HIGH PERFORMANCE
ACCELERATED 2-CLOCK 80C51 CPU
1 kB
CODE FLASH
TIMER 0
TIMER 1
INTERNAL BUS
128-BYTE
DATA RAM
REAL-TIME CLOCK/
SYSTEM TIMER
PORT 3
CONFIGURABLE I/Os
ANALOG
COMPARATOR
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
KEYPAD
INTERRUPT
WATCHDOG TIMER
AND OSCILLATOR
PROGRAMMABLE
OSCILLATOR DIVIDER
CRYSTAL
OR
RESONATOR
CONFIGURABLE
OSCILLATOR
CPU
CLOCK
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
ON-CHIP
RC
OSCILLATOR
002aaa444
Fig 1. P89LPC901 block diagram.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14465
Product data
Rev. 05 — 17 December 2004
4 of 53
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
P89LPC902
HIGH PERFORMANCE
ACCELERATED 2-CLOCK 80C51 CPU
1 kB
CODE FLASH
TIMER 0
TIMER 1
INTERNAL
BUS
128-BYTE
DATA RAM
REAL-TIME CLOCK/
SYSTEM TIMER
PORT 1
INPUT
ANALOG
COMPARATORS
PORT 0
CONFIGURABLE I/Os
KEYPAD
INTERRUPT
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
WATCHDOG TIMER
AND OSCILLATOR
PROGRAMMABLE
OSCILLATOR DIVIDER
CPU
CLOCK
ON-CHIP
RC
OSCILLATOR
002aaa445
Fig 2. P89LPC902 block diagram.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14465
Product data
Rev. 05 — 17 December 2004
5 of 53
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
P89LPC903
HIGH PERFORMANCE
ACCELERATED 2-CLOCK 80C51 CPU
1 kB
CODE FLASH
UART
INTERNAL
BUS
128-BYTE
DATA RAM
TIMER 0
TIMER 1
PORT 1
INPUT
REAL-TIME CLOCK/
SYSTEM TIMER
PORT 0
CONFIGURABLE I/Os
ANALOG
COMPARATORS
KEYPAD
INTERRUPT
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
WATCHDOG TIMER
AND OSCILLATOR
PROGRAMMABLE
OSCILLATOR DIVIDER
CPU
CLOCK
ON-CHIP
RC
OSCILLATOR
002aaa446
Fig 3. P89LPC903 block diagram.
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9397 750 14465
Product data
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P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
5. Pinning information
5.1 Pinning
VDD 1
XTAL1/P3.1 2
CLKOUT/XTAL2/P3.0 3
RST/P1.5 4
P89LPC901FD
handbook, halfpage
8
VSS
7
P0.4/CIN1A/KBI4
6
P0.5/CMPREF/KBI5
5
P1.2/T0
002aaa438
Fig 4. P89LPC901 pinning (SO8).
VDD 1
XTAL1/P3.1 2
CLKOUT/XTAL2/P3.0 3
RST/P1.5 4
P89LPC901FN
handbook, halfpage
8 VSS
7 P0.4/CIN1A/KBI4
6 P0.5/CMPREF/KBI5
5 P1.2/T0
002aaa469
Fig 5. P89LPC901 pinning (DIP8).
VDD 1
P0.2/CIN2A/KBI2 2
P0.0/CMP2/KBI0 3
RST/P1.5 4
P89LPC902FD
handbook, halfpage
8
VSS
7
P0.4/CIN1A/KBI4
6
P0.5/CMPREF/KBI5
5
P0.6/CMP1/KBI6
002aaa439
Fig 6. P89LPC902 pinning (SO8).
VDD 1
P0.2/CIN2A/KBI2 2
P0.0/CMP2/KBI0 3
RST/P1.5 4
P89LPC902FN
handbook, halfpage
8 VSS
7 P0.4/CIN1A/KBI4
6 P0.5/CMPREF/KBI5
5 P0.6/CMP1/KBI6
002aaa470
Fig 7. P89LPC902 pinning (DIP8).
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9397 750 14465
Product data
Rev. 05 — 17 December 2004
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P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
VDD 1
P0.2/CIN2A/KBI2 2
P1.1/RxD 3
RST/P1.5 4
P89LPC903FD
handbook, halfpage
8
VSS
7
P0.4/CIN1A/KBI4
6
P0.5/CMPREF/KBI5
5
P1.0/TxD
002aaa440
Fig 8. P89LPC903 pinning (SO8).
5.2 Pin description
Table 3:
P89LPC901 pin description
Symbol
Pin
P0.0 to P0.6
Type
Description
I/O
Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0
latches are configured in the input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 8.12.1 “Port
configurations” and Table 13 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
7
6
I/O
P0.4 — Port 0 bit 4.
I
CIN1A — Comparator 1 positive input.
I
KBI4 — Keyboard input 4.
I/O
P0.5 — Port 0 bit 5.
I
CMPREF — Comparator reference (negative) input.
I
KBI5 — Keyboard input 5.
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9397 750 14465
Product data
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P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
Table 3:
P89LPC901 pin description…continued
Symbol
Pin
Type
P1.0 to P1.5
Description
Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1
latches are configured in the input only mode with the internal pull-up disabled. The
operation of the configurable Port 1 pins as inputs and outputs depends upon the
port configuration selected. Each of the configurable port pins are programmed
independently. Refer to Section 8.12.1 “Port configurations” and Table 13 “DC
electrical characteristics” for details. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
5
4
P3.0 to P3.1
I/O
P1.2 — Port 1 bit 2.
O
T0 — Timer/counter 0 external count input or overflow output.
I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specified level.
When system power is removed VDD will fall below the minimum specified
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating voltage.
Also used during a power-on sequence to force In-System Programming mode.
I/O
Port 3: Port 3 is an I/O port with a user-configurable output types. During reset Port 3
latches are configured in the input only mode with the internal pull-up disabled. The
operation of port 3 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 8.12.1 “Port
configurations” and Table 13 “DC electrical characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below:
3
2
I/O
P3.0 — Port 3 bit 0.
O
XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the FLASH configuration).
O
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK to TRIM.6). It
can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the real time clock/system timer.
I/O
P3.1 — Port 3 bit 1.
I
XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selected via the FLASH configuration). It can be a port pin if internal RC oscillator or
Watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not
used to generate the clock for the real time clock/system timer.
VSS
8
I
Ground: 0 V reference.
VDD
1
I
Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14465
Product data
Rev. 05 — 17 December 2004
9 of 53
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
Table 4:
P89LPC902 pin description
Symbol
Pin
P0.0 to P0.6
Type
Description
I/O
Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0
latches are configured in the input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 8.12.1 “Port
configurations” and Table 13 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
3
2
7
6
5
I/O
P0.0 — Port 0 bit 0.
I
CMP2 — Comparator 2 output.
I
KBI0 — Keyboard input 0.
I/O
P0.2 — Port 0 bit 2.
I
CIN2A — Comparator 2 positive input.
I
KBI2 — Keyboard input 2.
I/O
P0.4 — Port 0 bit 4.
I
CIN1A — Comparator 1 positive input.
I
KBI4 — Keyboard input 4.
I/O
P0.5 — Port 0 bit 5.
I
CMPREF — Comparator reference (negative) input.
I
KBI5 — Keyboard input 5.
I/O
P0.6 — Port 0 bit 6.
O
CMP1 — Comparator 1 output.
I
KBI6 — Keyboard input 6.
P1.0 to P1.5
Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1
latches are configured in the input only mode with the internal pull-up disabled. The
operation of the configurable Port 1 pins as inputs and outputs depends upon the
port configuration selected. Each of the configurable port pins are programmed
independently. Refer to Section 8.12.1 “Port configurations” and Table 13 “DC
electrical characteristics” for details. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
4
I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force In-System
Programming mode.
VSS
8
I
Ground: 0 V reference.
VDD
1
I
Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
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9397 750 14465
Product data
Rev. 05 — 17 December 2004
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P89LPC901/902/903
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8-bit microcontrollers with two-clock 80C51 core
Table 5:
P89LPC903 pin description
Symbol
Pin
P0.0 to P0.6
Type
Description
I/O
Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0
latches are configured in the input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 8.12.1 “Port
configurations” and Table 13 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
2
7
6
I/O
P0.2 — Port 0 bit 2.
I
CIN2A — Comparator 2 positive input.
I
KBI2 — Keyboard input 2.
I/O
P0.4 — Port 0 bit 4.
I
CIN1A — Comparator 1 positive input.
I
KBI4 — Keyboard input 4.
I/O
P0.5 — Port 0 bit 5.
I
CMPREF — Comparator reference (negative) input.
I
KBI5 — Keyboard input 5.
P1.0 to P1.5
Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1
latches are configured in the input only mode with the internal pull-up disabled. The
operation of the configurable Port 1 pins as inputs and outputs depends upon the
port configuration selected. Each of the configurable port pins are programmed
independently. Refer to Section 8.12.1 “Port configurations” and Table 13 “DC
electrical characteristics” for details. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
5
3
4
I/O
P1.0 — Port 1 bit 0.
O
TxD — Serial port transmitter data.
I/O
P1.1 — Port 1 bit 1.
I
RxD — Serial port receiver data.
I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force In-System
Programming mode.
VSS
8
I
Ground: 0 V reference.
VDD
1
I
Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
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9397 750 14465
Product data
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8-bit microcontrollers with two-clock 80C51 core
6. Logic symbols
XTAL1
PORT 1
XTAL2
VSS
P89LPC901
CLKOUT
CIN1A
CMPREF
PORT 0
KBI4
KBI5
PORT 3
VDD
RST
T0
002aaa441
Fig 9. P89LPC901 logic symbol.
PORT 1
RST
PORT 1
CIN1A
CMPREF
CMP1
CIN2A
CMP2
VSS
P89LPC902
KBI4
KBI5
KBI6
KBI2
KBI0
PORT 0
VDD
RST
RxD
TxD
002aaa442
Fig 10. P89LPC902 logic symbol.
CIN1A
CMPREF
CIN2A
VSS
P89LPC903
KBI4
KBI5
KBI2
PORT 0
VDD
002aaa443
Fig 11. P89LPC903 logic symbol.
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Product data
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8-bit microcontrollers with two-clock 80C51 core
Table 6 highlights the differences between these three devices. For a complete list of
device features, please see Section 2 “Features” on page 1.
Table 6:
Product comparison overview
Type number
External
crystal pins
CLKOUT output T0 PWM output CMP2 input
CMP1 and
CMP2 outputs
UART
P89LPC901xx
X
X
X
-
-
-
-
P89LPC902xx
-
-
-
X
X
-
-
P89LPC903xx
-
-
-
X
-
X
X
Rxd
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Product data
TxD
Rev. 05 — 17 December 2004
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Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
7. Special function registers
Remark: Special Function Registers (SFRs) accesses are restricted in the following
ways:
• User must not attempt to access any SFR locations not defined.
• Accesses to any defined SFR locations must be strictly for the functions for the
SFRs.
• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:
– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value
when read (even if it was written with ‘0’). It is a reserved bit and may be used in
future derivatives.
– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.
– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.
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9397 750 14465
Product data
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Product data
Table 7:
P89LPC901 Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Accumulator
AUXR1
Auxiliary function register
B*
B register
Reset value
Hex
Binary
E0H
00
00000000
A2H
00[1]
000000x0
F0H
00
00000000
00[1]
xx000000
Bit address
ACC*
Bit functions and addresses
Bit address
MSB
E7
LSB
E6
E5
E4
E3
E2
E1
E0
CLKLP
-
-
ENT0
SRST
0
-
DPS
F7
F6
F5
F4
F3
F2
F1
F0
CMP1
Comparator 1 control register
ACH
-
-
CE1
-
CN1
-
CO1
CMF1
DIVM
CPU clock divide-by-M
control
95H
00
00000000
DPTR
Data pointer (2 bytes)
83H
00
00000000
DPL
Data pointer low
82H
00
00000000
FMADRH
Program Flash address high
E7H
00
00000000
FMADRL
Program Flash address low
E6H
00
00000000
FMCON
Program Flash Control
(Read)
E4H
70
01110000
00
00000000
00
00000000
00[1]
00x00000
Program Flash Control
(Write)
FMDATA
Program Flash data
E5H
IEN0*
Interrupt enable 0
A8H
Bit address
IEN1*
Interrupt enable 1
E8H
15 of 53
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Bit address
IP0*
IP0H
Interrupt priority 0
Interrupt priority 0 high
B8H
B7H
Bit address
IP1*
IP1H
KBCON
Interrupt priority 1
Interrupt priority 1 high
Keypad control register
F8H
F7H
94H
BUSY
-
-
-
HVA
HVE
SV
OI
FMCMD.
7
FMCMD.
6
FMCMD.
5
FMCMD.
4
FMCMD.
3
FMCMD.
2
FMCMD.
1
FMCMD.
0
EA
EWDRT
EBO
-
ET1
-
ET0
-
EF
EE
ED
EC
EB
EA
E9
E8
-
-
-
-
-
EC
EKBI
-
BF
BE
BD
BC
BB
BA
B9
B8
-
PWDRT
PBO
-
PT1
-
PT0
-
00[1]
x0000000
00[1]
x0000000
-
PWDRT
H
PBOH
-
PT1H
-
PT0H
-
FF
FE
FD
FC
FB
FA
F9
F8
-
-
-
-
-
PC
PKBI
-
00[1]
00x00000
-
00[1]
00x00000
KBIF
00[1]
xxxxxx00
-
-
-
-
-
PCH
-
PKBIH
PATN
_SEL
P89LPC901/902/903
Data pointer high
8-bit microcontrollers with two-clock 80C51 core
Rev. 05 — 17 December 2004
DPH
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Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
KBMASK
Keypad interrupt mask
register
86H
00
00000000
KBPATN
Keypad pattern register
93H
FF
11111111
Bit address
P0*
Port 0
P1*
Port 1
80H
Bit address
90H
Bit address
P3*
Port 3
B0H
87
86
85
84
83
82
81
80
-
-
CMPREF
/KB5
CIN1A
/KB4
-
-
-
-
97
96
95
94
93
92
91
90
-
-
RST
-
-
T0
-
-
B7
B6
B5
B4
B3
B2
B1
B0
-
-
-
-
-
-
XTAL1
XTAL2
[1]
[1]
[1]
Port 0 output mode 1
84H
-
-
(P0M1.5) (P0M1.4)
-
-
-
-
FF
11111111
Port 0 output mode 2
85H
-
-
(P0M2.5) (P0M2.4)
-
-
-
-
00
00000000
-
FF[1]
11111111
-
00[1]
00000000
03[1]
xxxxxx11
P1M2
Port 1 output mode 1
91H
Port 1 output mode 2
92H
-
-
(P1M1.5)
(P1M2.5)
-
-
(P1M1.2)
(P1M2.2)
-
Port 3 output mode 1
B1H
-
-
-
-
-
-
(P3M1.1) (P3M1.0)
P3M2
Port 3 output mode 2
B2H
-
-
-
-
-
-
(P3M2.1) (P3M2.0) 00[1]
xxxxxx00
PCON
Power control register
87H
-
-
BOPD
BOI
GF1
GF0
PMOD1
00
00000000
-
00[1]
00000000
00[1]
xxxxxxxx
PCONA
PCONB
Power control register A
B5H
reserved for Power Control
Register B
B6H
RTCPD
VCPD
-
PMOD0
-
-
-
-
-
-
-
-
D7
D6
D5
D4
D3
D2
D1
D0
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
00
00000000
xx00000x
Bit address
16 of 53
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
PSW*
Program status word
PT0AD
Port 0 digital input disable
F6H
-
-
PT0AD.5
PT0AD.4
-
-
-
-
00
RSTSRC
Reset source register
DFH
-
-
BOF
POF
-
R_WD
R_SF
R_EX
[3]
RTCCON
Real-time clock control
D1H
RTCF
RTCS1
RTCS0
-
-
-
ERTC
RTCEN
60[1]
011xxx00
[6]
RTCH
Real-time clock register high
D2H
00[6]
00000000
00000000
RTCL
Real-time clock register low
D3H
00[6]
SP
Stack pointer
81H
07
00000111
TAMOD
Timer 0 auxiliary mode
8FH
00
xxx0xxx0
-
-
-
-
-
-
-
T0M2
P89LPC901/902/903
P3M1
8-bit microcontrollers with two-clock 80C51 core
Rev. 05 — 17 December 2004
P0M1
P0M2
P1M1
Philips Semiconductors
9397 750 14465
Product data
Table 7:
P89LPC901 Special function registers…continued
* indicates SFRs that are bit addressable.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR
addr.
Bit address
Bit functions and addresses
Reset value
MSB
LSB
8F
8E
8D
8C
8B
8A
89
88
TF1
TR1
TF0
TR0
-
-
-
-
Hex
Binary
TCON*
Timer 0 and 1 control
88H
00
00000000
TH0
Timer 0 high
8CH
00
00000000
TH1
Timer 1 high
8DH
00
00000000
TL0
Timer 0 low
8AH
00
00000000
TL1
Timer 1 low
8BH
00
00000000
TMOD
Timer 0 and 1 mode
89H
00
00000000
-
-
T1M1
T1M0
-
-
T0M1
T0M0
Internal oscillator trim register
96H
-
-
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
[4] [6]
WDL
Watchdog load
C1H
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
[3]
[5]
[6]
11111111
All ports are in input only (high impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.
The RSTSRC register reflects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx110000.
After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after Watchdog reset and is ‘0’ after power-on reset. Other resets will
not affect WDTOF.
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset source that affects these SFRs is power-on reset.
17 of 53
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P89LPC901/902/903
[4]
FF
8-bit microcontrollers with two-clock 80C51 core
Rev. 05 — 17 December 2004
TRIM
[5] [6]
[1]
[2]
Philips Semiconductors
9397 750 14465
Product data
Table 7:
P89LPC901 Special function registers…continued
* indicates SFRs that are bit addressable.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors
9397 750 14465
Product data
Table 8:
P89LPC902 Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Accumulator
AUXR1
Auxiliary function register
B*
B register
Binary
E0H
00
00000000
A2H
00[1]
000000x0
F0H
00
00000000
ACH
CMF1
00[1]
xx000000
CMF2
00[1]
xx000000
Bit address
CMP1
Comparator 1 control register
Reset value
Hex
Bit address
ACC*
Bit functions and addresses
MSB
E7
LSB
E6
E5
E4
E3
E2
E1
E0
-
-
-
-
SRST
0
-
DPS
F7
F6
F5
F4
F3
F2
F1
F0
-
-
CN1
CN2
OE1
OE2
CO1
CO2
DIVM
CPU clock divide-by-M
control
95H
00
00000000
DPTR
Data pointer (2 bytes)
83H
00
00000000
82H
00
00000000
Program Flash address high
E7H
00
00000000
FMADRL
Program Flash address low
E6H
00
00000000
FMCON
Program Flash Control
(Read)
E4H
70
01110000
00
00000000
00
00000000
00[1]
00x00000
Program Flash Control
(Write)
FMDATA
Program Flash data
E5H
IEN0*
Interrupt enable 0
A8H
IEN1*
Interrupt enable 1
Bit address
18 of 53
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
E8H
Bit address
IP0*
IP0H
Interrupt priority 0
Interrupt priority 0 high
B8H
B7H
Bit address
IP1*
IP1H
Interrupt priority 1
Interrupt priority 1 high
F8H
F7H
BUSY
-
-
-
HVA
HVE
SV
OI
FMCMD.
7
FMCMD.
6
FMCMD.
5
FMCMD.
4
FMCMD.
3
FMCMD.
2
FMCMD.
1
FMCMD.
0
EA
EWDRT
EBO
-
ET1
-
ET0
-
EF
EE
ED
EC
EB
-
-
-
-
-
EA
E9
E8
EC
EKBI
-
BF
BE
BD
BC
BB
BA
B9
B8
-
PWDRT
PBO
-
PT1
-
PT0
-
00[1]
x0000000
00[1]
x0000000
-
PWDRT
H
PBOH
-
PT1H
-
PT0H
-
FF
FE
FD
FC
FB
FA
F9
F8
-
-
-
-
-
PC
PKBI
-
00[1]
00x00000
-
00[1]
00x00000
-
-
-
-
-
PCH
PKBIH
P89LPC901/902/903
Data pointer low
FMADRH
8-bit microcontrollers with two-clock 80C51 core
Rev. 05 — 17 December 2004
ADH
DPL
CE2
-
Comparator 2 control register
Data pointer high
-
CE1
CMP2
DPH
-
-
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
-
-
PATN
_SEL
KBIF
xxxxxx00
KBMASK
Keypad interrupt mask
register
86H
00
00000000
KBPATN
Keypad pattern register
93H
FF
11111111
P0*
Port 0
90H
-
Binary
00[1]
94H
Bit address
-
Hex
Keypad control register
80H
-
LSB
KBCON
Bit address
-
86
85
84
83
82
81
80
-
CMP1
/KB6
CMPREF
/KB5
CIN1A
/KB4
-
KB2
-
KB0
97
96
95
94
93
92
91
90
-
-
RST
-
-
-
-
-
B6
B5
B4
[1]
Port 1
B3
B2
B1
P0M1
Port 0 output mode 1
84H
-
(P0M1.6) (P0M1.5) (P0M1.4)
-
(P0M1.2)
-
(P0M1.0) FF
11111111
P0M2
Port 0 output mode 2
85H
-
(P0M2.6) (P0M2.5) (P0M2.4)
-
(P0M2.2)
-
(P0M2.0) 00
00000000
P1M1
Port 1 output mode 1
91H
B7
-
-
(P1M1.5)
-
-
-
B0
11111111
00[1]
00000000
00
00000000
-
00[1]
00000000
00[1]
xxxxxxxx
-
P1M2
Port 1 output mode 2
92H
-
-
(P1M2.5)
-
-
-
-
-
PCON
Power control register
87H
-
-
BOPD
BOI
GF1
GF0
PMOD1
PMOD0
PCONA
PCONB
Power control register A
B5H
reserved for Power Control
Register B
B6H
Bit address
RTCPD
VCPD
-
-
-
-
-
-
-
-
-
D7
D6
D5
D4
D3
D2
D1
D0
19 of 53
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
PSW*
Program status word
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
00
00000000
PT0AD
Port 0 digital input disable
F6H
-
-
PT0AD.5
PT0AD.4
-
PT0AD.2
-
-
00
xx00000x
[3]
RSTSRC
Reset source register
DFH
-
-
BOF
POF
-
R_WD
R_SF
R_EX
RTCCON
Real-time clock control
D1H
RTCF
RTCS1
RTCS0
-
-
-
ERTC
RTCEN
60[1]
011xxx00
[6]
RTCH
Real-time clock register high
D2H
00[6]
00000000
00000000
00000111
RTCL
Real-time clock register low
D3H
00[6]
SP
Stack pointer
81H
07
P89LPC901/902/903
-
FF[1]
8-bit microcontrollers with two-clock 80C51 core
Rev. 05 — 17 December 2004
87
P1*
Bit address
Philips Semiconductors
9397 750 14465
Product data
Table 8:
P89LPC902 Special function registers…continued
* indicates SFRs that are bit addressable.
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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR
addr.
Bit address
Bit functions and addresses
Reset value
MSB
LSB
8F
8E
8D
8C
8B
8A
89
88
TF1
TR1
TF0
TR0
-
-
-
-
Hex
Binary
TCON*
Timer 0 and 1 control
88H
00
00000000
TH0
Timer 0 high
8CH
00
00000000
TH1
Timer 1 high
8DH
00
00000000
TL0
Timer 0 low
8AH
00
00000000
TL1
Timer 1 low
8BH
00
00000000
TMOD
Timer 0 and 1 mode
89H
00
00000000
-
-
T1M1
T1M0
-
-
T0M1
T0M0
Internal oscillator trim register
96H
-
-
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
[4] [6]
WDL
Watchdog load
C1H
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
[3]
[5]
[6]
11111111
All ports are in input only (high impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.
The RSTSRC register reflects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx110000.
After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after Watchdog reset and is ‘0’ after power-on reset. Other resets will
not affect WDTOF.
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset source that affects these SFRs is power-on reset.
20 of 53
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P89LPC901/902/903
[4]
FF
8-bit microcontrollers with two-clock 80C51 core
Rev. 05 — 17 December 2004
TRIM
[5] [6]
[1]
[2]
Philips Semiconductors
9397 750 14465
Product data
Table 8:
P89LPC902 Special function registers…continued
* indicates SFRs that are bit addressable.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors
9397 750 14465
Product data
Table 9:
P89LPC903 Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Accumulator
Reset value
Hex
Binary
E0H
00
00000000
A2H
00[1]
000000x0
Bit address
ACC*
Bit functions and addresses
MSB
E7
LSB
E6
E5
E4
E3
E2
E1
E0
AUXR1
Auxiliary function register
B*
B register
F0H
00
00000000
BRGR0[2]
Baud rate generator rate low
BEH
00
00000000
BRGR1[2]
Baud rate generator rate high
BFH
00
00000000
xxxxxx00
Bit address
-
EBRR
-
-
SRST
0
-
DPS
F7
F6
F5
F4
F3
F2
F1
F0
Baud rate generator control
BDH
-
-
-
-
-
-
SBRGS
BRGEN
CMP1
Comparator 1 control register
ACH
-
-
CE1
-
CN1
-
CO1
CMF1
00[1]
xx000000
CMF2
00[1]
xx000000
CMP2
Comparator 2 control register
ADH
-
-
CE2
-
CN2
-
CO2
DIVM
CPU clock divide-by-M
control
95H
00
00000000
DPTR
Data pointer (2 bytes)
Data pointer high
83H
00
00000000
DPL
Data pointer low
82H
00
00000000
FMADRH
Program Flash address high
E7H
00
00000000
FMADRL
Program Flash address low
E6H
00
00000000
FMCON
Program Flash Control
(Read)
E4H
70
01110000
00
00000000
00
00000000
00[1]
00x00000
Program Flash Control
(Write)
21 of 53
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
FMDATA
Program Flash data
E5H
IEN0*
Interrupt enable 0
A8H
Bit address
IEN1*
Interrupt enable 1
E8H
Bit address
IP0*
IP0H
Interrupt priority 0
Interrupt priority 0 high
B8H
B7H
Bit address
BUSY
-
-
-
HVA
HVE
SV
OI
FMCMD.
7
FMCMD.
6
FMCMD.
5
FMCMD.
4
FMCMD.
3
FMCMD.
2
FMCMD.
1
FMCMD.
0
EA
EWDRT
EBO
ES/ESR
ET1
-
ET0
-
EF
EE
ED
EC
EB
EA
E9
E8
-
EST
-
-
-
EC
EKBI
-
BF
BE
BD
BC
BB
BA
B9
B8
-
PWDRT
PBO
PS/PSR
PT1
-
PT0
-
00[1]
x0000000
00[1]
x0000000
-
PWDRT
H
PBOH
PSH
/PSRH
PT1H
-
PT0H
-
FF
FE
FD
FC
FB
FA
F9
F8
P89LPC901/902/903
DPH
8-bit microcontrollers with two-clock 80C51 core
Rev. 05 — 17 December 2004
BRGCON
00[6]
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
IP1*
Description
SFR
addr.
Interrupt priority 1
F8H
Bit functions and addresses
Reset value
MSB
-
PST
-
-
-
PC
PKBI
LSB
Hex
Binary
-
00[1]
00x00000
00x00000
IP1H
Interrupt priority 1 high
F7H
-
PSTH
-
-
-
PCH
PKBIH
-
00[1]
KBCON
Keypad control register
94H
-
-
-
-
-
-
PATN
_SEL
KBIF
00[1]
xxxxxx00
KBMASK
Keypad interrupt mask
register
86H
00
00000000
KBPATN
Keypad pattern register
93H
FF
11111111
Bit address
80H
87
86
85
84
83
82
81
80
-
-
CMPREF
/KB5
CIN1A
/KB4
-
KB2
-
-
[1]
Port 0
97
96
95
94
93
92
91
90
P1*
Port 1
90H
-
-
RST
-
-
-
RxD
TxD
P0M1
Port 0 output mode 1
84H
-
-
(P0M1.5) (P0M1.4)
-
(P0M1.2)
-
-
FF
11111111
P0M2
Port 0 output mode 2
85H
-
-
(P0M2.5) (P0M2.4)
-
(P0M2.2)
-
-
00
00000000
FF[1]
11111111
Port 1 output mode 1
91H
-
-
(P1M1.5)
-
-
-
(P1M1.1) (P1M1.0)
Port 1 output mode 2
92H
-
-
(P1M2.5)
-
-
-
(P1M2.1) (P1M2.0) 00[1]
00000000
PCON
Power control register
87H
SMOD1
SMOD0
BOPD
BOI
GF1
GF0
PMOD1
00
00000000
SPD
00[1]
00000000
00[1]
xxxxxxxx
PCONA
PCONB
Power control register A
B5H
reserved for Power Control
Register B
B6H
Bit address
RTCPD
VCPD
-
PMOD0
-
-
-
-
-
-
-
-
D7
D6
D5
D4
D3
D2
D1
D0
22 of 53
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
PSW*
Program status word
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
00
00000000
PT0AD
Port 0 digital input disable
F6H
-
-
PT0AD.5
PT0AD.4
-
PT0AD.2
-
-
00
xx00000x
[3]
RSTSRC
Reset source register
DFH
-
-
BOF
POF
R_BK
R_WD
R_SF
R_EX
RTCCON
Real-time clock control
D1H
RTCF
RTCS1
RTCS0
-
-
-
ERTC
RTCEN
60[1]
011xxx00
[6]
RTCH
Real-time clock register high
D2H
00[6]
00000000
00000000
RTCL
Real-time clock register low
D3H
00[6]
SADDR
Serial port address register
A9H
00
00000000
SADEN
Serial port address enable
B9H
00
00000000
P89LPC901/902/903
P1M1
P1M2
8-bit microcontrollers with two-clock 80C51 core
Rev. 05 — 17 December 2004
P0*
Bit address
Philips Semiconductors
9397 750 14465
Product data
Table 9:
P89LPC903 Special function registers…continued
* indicates SFRs that are bit addressable.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
99H
Hex
Binary
xx
xxxxxxxx
SBUF
Serial port data buffer register
9F
9E
9D
9C
9B
9A
99
98
SCON*
Serial port control
98H
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
00
00000000
SSTAT
Serial port extended status
register
BAH
DBMOD
INTLO
CIDIS
DBISEL
FE
BR
OE
STINT
00
00000000
SP
Stack pointer
81H
07
00000111
8F
8E
8D
8C
8B
8A
89
88
TF1
TR1
TF0
TR0
-
-
-
-
00
00000000
Bit address
Bit address
Timer 0 and 1 control
88H
TH0
Timer 0 high
8CH
00
00000000
TH1
Timer 1 high
8DH
00
00000000
TL0
Timer 0 low
8AH
00
00000000
TL1
Timer 1 low
8BH
00
00000000
TMOD
Timer 0 and 1 mode
89H
00
00000000
-
T1M1
T1M0
-
-
T0M1
T0M0
Internal oscillator trim register
96H
-
-
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
[4] [6]
WDL
Watchdog load
C1H
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
[1]
[2]
23 of 53
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[3]
[4]
[5]
[6]
FF
11111111
All ports are in input only (high impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.
The RSTSRC register reflects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx110000.
After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after Watchdog reset and is ‘0’ after power-on reset. Other resets will
not affect WDTOF.
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset source that affects these SFRs is power-on reset.
P89LPC901/902/903
TRIM
[5] [6]
8-bit microcontrollers with two-clock 80C51 core
Rev. 05 — 17 December 2004
TCON*
-
Philips Semiconductors
9397 750 14465
Product data
Table 9:
P89LPC903 Special function registers…continued
* indicates SFRs that are bit addressable.
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
8. Functional description
Remark: Please refer to the P89LPC901/902/903 User’s Manual for a more detailed
functional description.
8.1 Enhanced CPU
The P89LPC901/902/903 uses an enhanced 80C51 CPU which runs at 6 times the
speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles,
and most instructions execute in one or two machine cycles.
8.2 Clocks
8.2.1
Clock definitions
The P89LPC901/902/903 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of the
clock sources (see Figure 12, 13, and 14) and can also be optionally divided to a
slower frequency (see Section 8.7 “CPU CLOCK (CCLK) modification: DIVM
register”).
Note: fosc is defined as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two
or four CCLK cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK/2
8.2.2
CPU clock (OSCCLK)
The P89LPC901/902/903 provides several user-selectable oscillator options in
generating the CPU clock. This allows optimization for a range of needs from high
precision to lowest possible cost. These options are configured when the FLASH is
programmed and include an on-chip Watchdog oscillator and an on-chip RC
oscillator.
The P89LPC901, in addition, includes an option for an oscillator using an external
crystal or an external clock source. The crystal oscillator can be optimized for low,
medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.
8.2.3
Low speed oscillator option (P89LPC901)
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.
8.2.4
Medium speed oscillator option (P89LPC901)
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
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8.2.5
High speed oscillator option (P89LPC901)
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until VDD has
reached its specified level. When system power is removed VDD will fall below
the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when VDD falls below the minimum
specified operating voltage. If CCLK is 8 MHz or slower, the CLKLP SFR bit
(AUXR1.7) can be set to ‘1’ to reduce power consumption. On reset, CLKLP is ‘0’
allowing highest performance access. This bit can then be set in software if CCLK is
running at 8 MHz or slower.
8.2.6
Clock output (P89LPC901)
The P89LPC901 supports a user selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if
another clock source has been selected (on-chip RC oscillator, Watchdog oscillator,
external clock input on X1) and if the Real-Time clock is not using the crystal
oscillator as its clock source. This allows external devices to synchronize to the
P89LPC901. This output is enabled by the ENCLK bit in the TRIM register. The
frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power.
8.3 On-chip RC oscillator option
The P89LPC901/902/903 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ±2.5%.
End-user applications can write to the Trim register to adjust the on-chip RC oscillator
to other frequencies. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can
be set to ‘1’ to reduce power consumption. On reset, CLKLP is ‘0’ allowing highest
performance access. This bit can then be set in software if CCLK is running at 8 MHz
or slower.
8.4 Watchdog oscillator option
The Watchdog has a separate oscillator which has a frequency of 400 kHz. This
oscillator can be used to save power when a high clock frequency is not needed.
8.5 External clock input option (P89LPC901)
In this configuration, the processor clock is derived from an external source driving
the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2/P3.0 pin
may be used as a standard port pin or a clock output. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until VDD has
reached its specified level. When system power is removed VDD will fall below
the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when VDD falls below the minimum
specified operating voltage.
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XTAL1
High freq.
Med. freq.
Low freq.
XTAL2
RTC
OSCCLK
DIVM
CCLK
RC
OSCILLATOR
CPU
¸2
(7.3728 MHz)
WDT
WATCHDOG
OSCILLATOR
PCLK
(400 kHz)
TIMERS 0 & 1
002aaa447
Fig 12. Block diagram of oscillator control (P89LPC901).
RTC
RC
OSCILLATOR
OSCCLK
DIVM
CCLK
CPU
(7.3728 MHz)
¸2
WDT
WATCHDOG
OSCILLATOR
PCLK
(400 kHz)
TIMERS 0 & 1
002aaa448
Fig 13. Block diagram of oscillator control (P89LPC902).
RTC
RC
OSCILLATOR
OSCCLK
DIVM
CCLK
CPU
(7.3728 MHz)
¸2
WDT
WATCHDOG
OSCILLATOR
PCLK
(400 kHz)
BAUD RATE
GENERATOR
TIMERS 0 & 1
002aaa449
UART
Fig 14. Block diagram of oscillator control (P89LPC903).
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8.6 CPU CLock (CCLK) wake-up delay
The P89LPC901/902/903 has an internal wake-up timer that delays the clock until it
stabilizes depending to the clock source used. If the clock source is any of the three
crystal selections (P89LPC901) the delay is 992 OSCCLK cycles plus 60 to 100 µs.
8.7 CPU CLOCK (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption. By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
mode by executing its normal program at a lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.
8.8 Low power select
The P89LPC901 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK
is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power
consumption further. On any reset, CLKLP is ‘0’ allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
8.9 Memory organization
The various P89LPC901/902/903 memory spaces are as follows:
• DATA
128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect
addressing, using instruction other than MOVX and MOVC. All or part of the Stack
may be in this area.
• SFR
Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing.
• CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC901/902/903 has 1 kB of on-chip Code memory.
8.10 Data RAM arrangement
The 128 bytes of on-chip RAM is organized as follows:
Table 10:
On-chip data memory usages
Type
Data RAM
Size (Bytes)
DATA
Memory that can be addressed directly and indirectly 128
8.11 Interrupts
The P89LPC901/902/903 uses a four priority level interrupt structure. This allows
great flexibility in controlling the handling of the many interrupt sources.
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The P89LPC901 supports 6 interrupt sources: timers 0 and 1, brownout detect,
Watchdog/real-time clock, keyboard, and the comparator.
The P89LPC902 supports 6 interrupt sources: timers 0 and 1, brownout detect,
Watchdog/real-time clock, keyboard, and comparators 1 and 2.
The P89LPC903 supports 9 interrupt sources: timers 0 and 1, serial port Tx, serial
port Rx, combined serial port Rx/Tx, brownout detect, Watchdog/real-time clock,
keyboard, and comparators 1 and 2.
Each interrupt source can be individually enabled or disabled by setting or clearing a
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but not by another interrupt of the same or lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.
8.11.1
External interrupt inputs
The P89LPC901/902/903 has a Keypad Interrupt function. This can be used as an
external interrupt input.
If enabled when the P89LPC901/902/903 is put into Power-down or Idle mode, the
interrupt will cause the processor to wake-up and resume operation. Refer to Section
8.14 “Power reduction modes” for details.
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8-bit microcontrollers with two-clock 80C51 core
BOF
EBO
RTCF
ERTC
(RTCCON.1)
WDOVF
KBIF
EKBI
WAKE-UP
(IF IN POWER-DOWN)
EWDRT
CMF
EC
EA (IE0.7)
TF1
ET1
INTERRUPT
TO CPU
TF0
ET0
002aaa450
Fig 15. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC901).
BOF
EBO
RTCF
ERTC
(RTCCON.1)
WDOVF
KBIF
EKBI
WAKE-UP
(IF IN POWER-DOWN)
EWDRT
CMF
EC
EA (IE0.7)
TF1
ET1
INTERRUPT
TO CPU
TF0
ET0
002aaa451
Fig 16. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC902).
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8-bit microcontrollers with two-clock 80C51 core
BOF
EBO
RTCF
ERTC
(RTCCON.1)
WDOVF
KBIF
EKBI
WAKE-UP
(IF IN POWER-DOWN)
EWDRT
CMF
EC
EA (IE0.7)
TF1
ET1
TI & RI/RI
ES/ESR
INTERRUPT
TO CPU
TI
EST
TF0
ET0
002aaa452
Fig 17. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC903).
8.12 I/O ports
The P89LPC901 has between 3 and 6 I/O pins: P0.4, P0.5, P1.2, P1.5, P3.0, and
P3.1 The exact number of I/O pins available depends on the clock and reset options
chosen, as shown in Table 11.
Table 11:
Number of I/O pins available
Clock source
Reset option
On-chip oscillator or Watchdog oscillator
External clock input
No external reset (except during power-up)
6
External RST pin supported
5
No external reset (except during power-up)
5
External RST pin
Low/medium/high speed oscillator
(external crystal or resonator)
[1]
Number of I/O pins
(8-pin package)
supported[1]
4
No external reset (except during power-up)
4
External RST pin supported[1]
3
Required for operation above 12 MHz.
The P89LPC902 and P89LPC903 devices have either 5 or 6 I/O pins depending on
the reset pin option chosen.
8.12.1
Port configurations
All but one I/O port pin on the P89LPC901/902/903 may be configured by software to
one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51
port outputs), push-pull, open drain, and input-only. Two configuration registers for
each port select the output type for each port pin.
P1.5 (RST) can only be an input and cannot be configured.
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8.12.2
Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the
need to reconfigure the port. This is possible because when the port outputs a logic
HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the
pin is driven LOW, it is driven strongly and able to sink a fairly large current. These
features are somewhat similar to an open-drain output except that there are three
pull-up transistors in the quasi-bidirectional output that serve different purposes.
The P89LPC901/902/903 is a 3 V device, however, the pins are 5 V-tolerant (except
for XTAL1 and XTAL2). In quasi-bidirectional mode, if a user applies 5 V on the pin,
there will be a current flowing from the pin to VDD, causing extra power consumption.
Therefore, applying 5 V in quasi-bidirectional mode is discouraged.
A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
8.12.3
Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the
pull-down transistor of the port driver when the port latch contains a logic ‘0’. To be
used as a logic output, a port configured in this manner must have an external
pull-up, typically a resistor tied to VDD.
An open-drain port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
8.12.4
Input-only configuration
The input-only port configuration has no output drivers. It is a Schmitt-triggered input
that also has a glitch suppression circuit.
8.12.5
Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous
strong pull-up when the port latch contains a logic ‘1’. The push-pull mode may be
used when more source current is needed from a port output. A push-pull port pin
has a Schmitt-triggered input that also has a glitch suppression circuit.
8.12.6
Port 0 analog functions
The P89LPC901/902/903 incorporates an Analog Comparator. In order to give the
best analog function performance and to minimize power consumption, pins that are
being used for analog functions must have the digital outputs and digital inputs
disabled.
Digital outputs are disabled by putting the port output into the Input-Only (high
impedance) mode as described in Section 8.12.4 “Input-only configuration”.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On
any reset, the PT0AD bits default to ‘0’s to enable digital functions.
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8.12.7
Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different
from the LPC76x series of devices.
• After power-up all I/O pins, except P1.5, may be configured by software.
• Pin P1.5 is input only.
Every output on the P89LPC901/902/903 has been designed to sink typical LED
drive current. However, there is a maximum total output current for all ports which
must not be exceeded. Please refer to Table 13 “DC electrical characteristics” for
detailed specifications.
All ports pins that can function as an output have slew rate controlled outputs to limit
noise generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
8.13 Power monitoring functions
The P89LPC901/902/903 incorporates power monitoring functions designed to
prevent incorrect operation during initial power-up and power loss or reduction during
operation. This is accomplished with two hardware functions: Power-on Detect and
Brownout detect.
8.13.1
Brownout detection
The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor
reset, however, it may alternatively be configured to generate an interrupt.
Brownout detection may be enabled or disabled in software.
If Brownout detection is enabled, the operating voltage range for VDD is 2.7 V to 3.6 V,
and the brownout condition occurs when VDD falls below the brownout trip voltage,
VBO (see Table 13 “DC electrical characteristics”), and is negated when VDD rises
above VBO. If brownout detection is disabled, the operating voltage range for VDD is
2.4 V to 3.6 V. If the P89LPC901/902/903 device is to operate with a power supply
that can be below 2.7 V, BOE should be left in the unprogrammed state so that the
device can operate at 2.4 V, otherwise continuous brownout reset may prevent the
device from operating.
For correct activation of Brownout detect, the VDD rise and fall times must be
observed. Please see Table 13 “DC electrical characteristics” for specifications.
8.13.2
Power-on detection
The Power-on Detect has a function similar to the Brownout detect, but is designed to
work as power comes up initially, before the power supply voltage reaches a level
where Brownout detect can work. The POF flag in the RSTSRC register is set to
indicate an initial power-up condition. The POF flag will remain set until cleared by
software.
8.14 Power reduction modes
The P89LPC901/902/903 supports three different power reduction modes. These
modes are Idle mode, Power-down mode, and total Power-down mode.
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8.14.1
Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate
Idle mode.
8.14.2
Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption.
The P89LPC901/902/903 exits Power-down mode via any reset, or certain interrupts.
In Power-down mode, the power supply voltage may be reduced to the RAM
keep-alive voltage VRAM. This retains the RAM contents at the point where
Power-down mode was entered. SFR contents are not guaranteed after VDD has
been lowered to VRAM, therefore it is highly recommended to wake up the processor
via reset in this case. VDD must be raised to within the operating range before the
Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down. These include: Brownout detect,
Watchdog Timer, Comparators (note that Comparators can be powered-down
separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is
disabled unless both the RC oscillator has been selected as the system clock and the
RTC is enabled.
8.14.3
Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry
and the voltage comparators are also disabled to conserve additional power. The
internal RC oscillator is disabled unless both the RC oscillator has been selected as
the system clock and the RTC is enabled. If the internal RC oscillator is used to clock
the RTC during Power-down, there will be high power consumption. Please use an
external low frequency clock to achieve low power with the Real-Time Clock running
during Power-down.
8.15 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital
input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the
external reset input function on P1.5. When cleared, P1.5 may be used as an input
pin.
Remark: During a power-up sequence, the RPE selection is overridden and this pin
will always function as a reset input. An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset. After power-up this input will function either as an external reset
input or as a digital input as defined by the RPE bit. Only a power-up reset will
temporarily override the selection defined by RPE bit. Other sources of reset will not
override the RPE bit.
Remark: During a power cycle, VDD must fall below VPOR (see Table 13 “DC electrical
characteristics”) before power is reapplied, in order to ensure a power-on reset.
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Reset can be triggered from the following sources:
• External reset pin (during power-up or if user configured via UCFG1. This option
must be used for an oscillator frequency above 12 MHz.)
•
•
•
•
•
Power-on detect
Brownout detect
Watchdog Timer
Software reset
UART break character detect reset (P80LPC903).
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can
read this register to determine the most recent reset source. These flag bits can be
cleared in software by writing a ‘0’ to the corresponding bit. More than one flag bit
may be set:
• During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
• For any other reset, previously set flag bits that have not been cleared will remain
set.
8.16 Timers/counters 0 and 1
The P89LPC901/902/903 has two general purpose timers which are similar to the
standard 80C51 Timer 0 and Timer 1. These timers have four operating modes
(modes 0, 1, 2, and 3). Modes 0, 1, and 2 are the same for both Timers. Mode 3 is
different.
8.16.1
Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured
as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
8.16.2
Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
8.16.3
Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload.
Mode 2 operation is the same for Timer 0 and Timer 1.
8.16.4
Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When
Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.
8.16.5
Mode 6 (P89LPC901)
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.
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8.16.6
Timer overflow toggle output (P89LPC901)
Timers 0 and 1 can be configured to automatically toggle a port output whenever a
timer overflow occurs. The same device pins that are used for the T0 and T1 count
inputs are also used for the timer toggle outputs. The port outputs will be a logic 1
prior to the first timer overflow when this mode is turned on.
8.17 Real-Time clock/system timer
The P89LPC901/902/903 has a simple Real-Time clock that allows a user to continue
running an accurate timer while the rest of the device is powered-down. The
Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a
23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down
counter. When it reaches all ‘0’s, the counter will be reloaded again and the RTCF
flag will be set. The clock source for this counter can be either the CPU clock (CCLK)
or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU
clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as
its clock source. Only power-on reset will reset the Real-Time clock and its
associated SFRs to the default state.
8.18 UART (P89LPC903)
The P89LPC903 has an enhanced UART that is compatible with the conventional
80C51 UART except that Timer 2 overflow cannot be used as a baud rate source.
The P89LPC903 does include an independent Baud Rate Generator. The baud rate
can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the
independent Baud Rate Generator. In addition to the baud rate generation,
enhancements over the standard 80C51 UART include Framing Error detection,
automatic address recognition, selectable double buffering and several interrupt
options. The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit
UART, and CPU clock/32 or CPU clock/16.
8.18.1
Mode 0
Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at 1⁄16 of the CPU clock
frequency.
8.18.2
Mode 1
10 bits are transmitted (through TxD) or received (through RxD): a start bit
(logical ‘0’), 8 data bits (LSB first), and a stop bit (logical ‘1’). When data is received,
the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is
variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator
(described in Section 8.18.5 “Baud rate generator and selection”).
8.18.3
Mode 2
11 bits are transmitted (through TxD) or received (through RxD): start bit (logical ‘0’),
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical ‘1’). When
data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of ‘0’ or
‘1’. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When
data is received, the 9th data bit goes into RB8 in Special Function Register SCON,
while the stop bit is not saved. The baud rate is programmable to either 1⁄16 or 1⁄32 of
the CPU clock frequency, as determined by the SMOD1 bit in PCON.
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8.18.4
Mode 3
11 bits are transmitted (through TxD) or received (through RxD): a start bit
(logical ‘0’), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit
(logical ‘1’). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate.
The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or
the Baud Rate Generator (described in section Section 8.18.5 “Baud rate generator
and selection”).
8.18.5
Baud rate generator and selection
The P89LPC903 enhanced UART has an independent Baud Rate Generator. The
baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0
SFRs which together form a 16-bit baud rate divisor value that works in a similar
manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other
timing functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 18).
Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses CCLK.
Timer 1 Overflow
(PCLK-based)
SMOD1 = 1
¸2
SBRGS = 0
Baud Rate Modes 1 and 3
SMOD1 = 0
Baud Rate Generator
(CCLK-based)
SBRGS = 1
002aaa419
Fig 18. Baud rate sources for UART (Modes 1, 3).
8.18.6
Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0
(PCON.6) is ‘1’, framing errors can be made available in SCON.7, respectively. If
SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)
are set up when SMOD0 is ‘0’.
8.18.7
Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the
device.
8.18.8
Double buffering
The UART has a transmit double buffer that allows buffering of the next character to
be written to SBUF while the first character is being transmitted. Double buffering
allows transmission of a string of characters with only one stop bit between any two
characters, as long as the next character is written between the start bit and the stop
bit of the previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = ‘0’), the UART
is compatible with the conventional 80C51 UART. If enabled, the UART allows writing
to SnBUF while the previous data is being shifted out. Double buffering is only
allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be
disabled (DBMOD = ‘0’).
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8.18.9
Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated
when the double buffer is ready to receive new data.
8.18.10
The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as
long as TB8 is updated some time before that bit is shifted out. TB8 must not be
changed until the bit is shifted out, as indicated by the Tx interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8
will be double-buffered together with SBUF data.
8.19 Analog comparators
One analog comparator is provided on the P89LPC901. Two analog comparators are
provided on the P89LPC902 and P89LPC903 devices. Comparator operation is such
that the output is a logical one (which may be read in a register) when the positive
input is greater than the negative input (selectable from a pin or an internal reference
voltage). Otherwise the output is a zero. The comparator may be configured to cause
an interrupt when the output value changes.
The connections to the comparator are shown in Figure 19. Note: Not all possible
comparator configurations are available on all three devices. Please refer to the Logic
diagrams in Section 6 “Logic symbols” on page 12. The comparator functions to
VDD = 2.4 V.
When the comparator is first enabled, the comparator output and interrupt flag are not
guaranteed to be stable for 10 microseconds. The comparator interrupt should not be
enabled during that time, and the comparator interrupt flag must be cleared before
the interrupt is enabled in order to prevent an immediate interrupt service.
When a comparator is disabled the comparator’s output, COx, goes HIGH. If the
comparator output was LOW and then is disabled, the resulting transition of the
comparator output from a LOW to HIGH state will set the comparator flag, CMFx.
This will cause an interrupt if the comparator interrupt is enabled. The user should
therefore disable the comparator interrupt prior to disabling the comparator.
Additionally, the user should clear the comparator flag, CMFx, after disabling the
comparator.
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Comparator 1
OE1
(P0.4) CIN1A
CO1
CMP1 (P0.6)
(P0.5) CMPREF
Change Detect
VREF
CMF1
CN1
Interrupt
Change Detect
Comparator 2
EC
CMF2
(P0.2) CIN2A
CMP2 (P0.0)
CO2
OE2
002aaa453
CN2
Fig 19. Comparator input and output connections.
8.20 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to
as VREF, is 1.23 V ±10%.
8.21 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag
is set whenever the comparator output changes state. The flag may be polled by
software or may be used to generate an interrupt.
8.22 Comparator and power reduction modes
The comparators may remain enabled when Power-down or Idle mode is activated,
but the comparators are disabled automatically in Total Power-down mode.
If the comparator interrupt is enabled (except in Total Power-down mode), a change
of the comparator output state will generate an interrupt and wake up the processor. If
the comparator output to a pin is enabled, the pin should be configured in the
push-pull mode in order to obtain fast switching times while in Power-down mode.
The reason is that with the oscillator stopped, the temporary strong pull-up that
normally occurs during switching on a quasi-bidirectional port pin does not take
place.
The comparator consumes power in Power-down and Idle modes, as well as in the
normal operating mode. This fact should be taken into account when system power
consumption is an issue. To minimize power consumption, the user can disable the
comparator via PCONA.5 or put the device in Total Power-down mode.
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8.23 Keypad interrupt (KBI)
The Keypad Interrupt function is intended primarily to allow a single interrupt to be
generated when Port 0 is equal to or not equal to a certain pattern. This function can
be used for bus address recognition or keypad recognition. The user can configure
the port via SFRs for different tasks.
The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins
connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN)
is used to define a pattern that is compared to the value of Port 0. The Keypad
Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when
the condition is matched while the Keypad Interrupt function is active. An interrupt will
be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register
(KBCON) is used to define equal or not-equal for the comparison.
In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x
series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then
any key connected to Port 0 which is enabled by the KBMASK register will cause the
hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt
may be used to wake up the CPU from Idle or Power-down modes. This feature is
particularly useful in handheld, battery powered systems that need to carefully
manage power consumption yet also need to be convenient to use.
In order to set the flag and cause an interrupt, the pattern on Port 0 must be held
longer than six CCLKs.
8.24 Watchdog timer
The Watchdog timer causes a system reset when it underflows as a result of a failure
to feed the timer prior to the timer reaching its terminal count. It consists of a
programmable 12-bit prescaler, and an 8-bit down counter. The down counter is
decremented by a tap taken from the prescaler. The clock source for the prescaler is
either the PCLK or the nominal 400 kHz Watchdog oscillator. The Watchdog timer
can only be reset by a power-on reset. When the Watchdog feature is disabled, it can
be used as an interval timer and may generate an interrupt. Figure 20 shows the
Watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte
sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down,
the watchdog is disabled. The Watchdog timer has a time-out period that ranges from
a few µs to a few seconds. Please refer to the P89LPC901/902/903 User’s Manual for
more details.
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WDL (C1H)
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
Watchdog
oscillator
PCLK
÷32
8-BIT DOWN
COUNTER
PRESCALER
RESET
see note (1)
SHADOW
REGISTER
FOR WDCON
CONTROL REGISTER
WDCON (A7H)
PRE2
PRE1
PRE0
–
–
WDRUN
WDTOF
WDCLK
002aaa423
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
feed sequence.
Fig 20. Watchdog timer in Watchdog mode (WDTE = ‘1’).
8.25 Additional features
8.25.1
Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor
completely, as if an external reset or Watchdog reset had occurred. Care should be
taken when writing to AUXR1 to avoid accidental software resets.
8.25.2
Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects
one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so
that the DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of inadvertently altering other
bits in the register.
8.26 Flash program memory
8.26.1
General description
The P89LPC901/902/903 Flash memory provides in-circuit electrical erasure and
programming. The Flash can be erased, read, and written as bytes. The Sector and
Page Erase functions can erase any Flash sector (256 bytes) or page (16 bytes). The
Chip Erase operation will erase the entire program memory. In-Circuit Programming
using standard commercial programmers is available. In addition, In-Application
Programming (IAP) and byte erase allows code memory to be used for non-volatile
data storage. On-chip erase and write timing generation contribute to a user-friendly
programming interface. The P89LPC901/902/903 Flash reliably stores memory
contents even after more than 100,000 erase and program cycles. The cell is
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designed to optimize the erase and programming mechanisms. The
P89LPC901/902/903 uses VDD as the supply voltage to perform the Program/Erase
algorithms.
8.26.2
Features
•
•
•
•
•
•
•
•
8.26.3
Programming and erase over the full operating voltage range.
Byte-erase allowing code memory to be used for data storage.
Read/Programming/Erase using ICP.
Any flash program/erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the Flash for each sector.
More than 100,000 minimum erase/program cycles for each byte.
10-year minimum data retention.
Flash organization
The P89LPC901/902/903 program memory consists of four 256 byte sectors. Each
sector can be further divided into 16-byte pages. In addition to sector erase, page
erase, and byte erase, a 16-byte page register is included which allows from 1 to 16
bytes of a given page to be programmed at the same time, substantially reducing
overall programming time. In addition, erasing and reprogramming of
user-programmable configuration bytes including UCFG1, the Boot Status Bit, and
the Boot Vector is supported.
8.26.4
Flash programming and erasing
Different methods of erasing or programming of the Flash are available. The Flash
may be programmed or erased in the end-user application (IAP) under control of the
application’s firmware. Another option is to use the In-Circuit Programming (ICP)
mechanism. This ICP system provides for programming through a serial clock- serial
data interface. Third, the Flash may be programmed or erased using a commercially
available EPROM programmer which supports this device. This device does not
provide for direct verification of code memory contents. Instead this device provides a
32-bit CRC result on either a sector or the entire 1 KB of user code space.
8.26.5
In-circuit programming (ICP)
In-Circuit Programming is performed without removing the microcontroller from the
system. The In-Circuit Programming facility consists of internal hardware resources
to facilitate remote programming of the P89LPC901/902/903 through a two-wire
serial interface. The Philips In-Circuit Programming facility has made in-circuit
programming in an embedded application, using commercially available
programmers, possible with a minimum of additional expense in components and
circuit board area. The ICP function uses five pins. Only a small connector needs to
be available to interface your application to a commercial programmer in order to use
this feature. Additional details may be found in the P89LPC901/902/903 User’s
Manual.
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8.26.6
In-application programming
In-Application Programming is performed in the application under the control of the
microcontroller’s firmware. The IAP facility consists of internal hardware resources to
facilitate programming and erasing. The Philips In-Application Programming has
made in-application programming in an embedded application possible without
additional components. This is accomplished through the use of four SFRs consisting
of a control/status register, a data register, and two address registers. Additional
details may be found in the P89LPC901/902/903 User’s Manual.
8.26.7
Using flash as data storage
The Flash code memory array of this device supports individual byte erasing and
programming. Any byte in the code memory array may be read using the MOVC
instruction, provided that the sector containing the byte has not been secured (a
MOVC instruction is not allowed to read code memory contents of a secured sector).
Thus any byte in a non-secured sector may be used for non-volatile data storage.
8.26.8
User configuration bytes
Some user-configurable features of the P89LPC901/902/903 must be defined at
power-up and therefore cannot be set by the program after start of execution. These
features are configured through the use of the Flash byte UCFG1. Please see the
P89LPC901/902/903 User’s Manual for additional details.
8.26.9
User sector security bytes
There are four User Sector Security Bytes, each corresponding to one sector. Please
see the P89LPC901/902/903 User’s Manual for additional details.
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9. Limiting values
Table 12: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
Min
Max
Unit
Tamb(bias)
operating bias ambient temperature
−55
+125
°C
Tstg
Vxtal
storage temperature range
−65
+150
°C
voltage on XTAL1, XTAL2 pin to VSS,
as applicable
-
VDD + 0.5
V
Vn
voltage on any other pin to VSS
−0.5
+5.5
V
IOH(I/O)
HIGH-level output current per I/O pin
-
8
mA
IOL(I/O)
LOW-level output current per I/O pin
-
20
mA
II/O(tot)(max)
maximum total I/O current
-
120
mA
Ptot(pack)
total power dissipation per package
-
1.5
W
[1]
based on package heat
transfer, not device power
consumption
The following applies to Limiting values:
a) Stresses above those listed under Table 12 may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any conditions other than those described in Table 13 “DC electrical characteristics”, Table 14 “AC
characteristics” and Table 15 “AC characteristics (P89LPC901)” of this specification are not implied.
b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
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10. Static characteristics
Table 13: DC electrical characteristics
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, unless otherwise specified.
Symbol
IDD(oper)
IDD(idle)
Parameter
power supply current,
operating (P89LPC901)
power supply current, Idle
mode (P89LPC901)
Min
Typ[1]
Max
Unit
3.6 V; 12 MHz
[2]
-
11
18
mA
3.6 V; 18 MHz
[2]
-
14
23
mA
3.6 V; 12 MHz
[2]
-
1
4
mA
3.6 V; 18 MHz
[2]
-
1.5
5.6
mA
-
4
8
mA
Conditions
IDD(oper)
power supply current,
operating (P89LPC902,
P89LPC903)
3.6 V; 7.373 MHz
[3]
IDD(idle)
power supply current, Idle
mode (P89LPC902,
P89LPC903)
3.6 V; 7.373 MHz
[3]
-
1
3
mA
IDD(PD)
power supply current,
Power-down mode, voltage
comparators powered-down
3.6 V
[2][3]
-
-
70
µA
IDD(TPD)
power supply current, total
Power-down mode
3.6 V
[2][3]
-
1
5
µA
(dVDD/dt)r
VDD rise rate
-
-
2
mV/µs
(dVDD/dt)f
VDD fall rate
-
-
50
mV/µs
VPOR
Power-on reset detect voltage
-
-
0.2
V
VRAM
RAM keep-alive voltage
1.5
-
-
V
Vth(HL)
negative-going threshold
voltage (Schmitt trigger input)
0.22VDD
0.4VDD
-
V
Vth(LH)
positive-going threshold
voltage (Schmitt trigger input)
-
0.6VDD
0.7VDD
V
Vhys
hysteresis voltage
-
0.2VDD
-
V
VOL
LOW-level output voltage; all
ports, all modes except Hi-Z
IOL = 20 mA
-
0.6
1.0
V
IOL = 10 mA
-
0.3
0.5
V
IOL = 3.2 mA
-
0.2
0.3
V
IOH = −8 mA;
push-pull mode
VDD − 1.0
-
-
V
IOH = −3.2 mA;
push-pull mode
VDD − 0.7
VDD − 0.4
-
V
IOH = −20 µA;
quasi-bidirectional
mode
VDD − 0.3
VDD − 0.2
-
V
VOH
HIGH-level output voltage, all
ports
input/output pin capacitance
[4]
-
-
15
pF
IIL
logical 0 input current,
all ports
[5]
-
-
−80
µA
ILI
input leakage current, all ports VIN = VIL or VIH
[6]
-
-
±10
µA
−30
-
−450
µA
10
-
30
kΩ
Cig
ITL
logical 1-to-0 transition
current, all ports
RRST
internal reset pull-up resistor
VIN = 0.4 V
VIN = 2.0 V at
VDD = 3.6 V
[7][8]
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Table 13: DC electrical characteristics…continued
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VBO
brownout trip voltage with
BOV = ‘1’, BOPD = ‘0’
2.4 V < VDD < 3.6 V
2.40
-
2.70
V
VREF
bandgap reference voltage
1.11
1.23
1.34
V
TC(VREF)
bandgap temperature
coefficient
-
10
20
ppm/
°C
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.
The IDD(oper), IPD(idle) specifications are measured using an external clock with the following functions disabled: comparators, brownout
detect, and Watchdog timer (P89LPC901).
The IDD(oper), IPD(idle) specifications are measured with the following functions disabled: comparators, brownout detect, and Watchdog
timer (P89LPC902, P89LPC903).
Pin capacitance is characterized but not tested.
Measured with port in quasi-bidirectional mode.
Measured with port in high-impedance mode.
Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups)
Port pins source a transition current when used in quasi-bidirectional mode and externally driven from ‘1’ to ‘0’. This current is highest
when VIN is approximately 2 V.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14465
Product data
Rev. 05 — 17 December 2004
45 of 53
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
11. Dynamic characteristics
Table 14: AC characteristics
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, unless otherwise specified.[1]
Symbol
Parameter
fRCOSC
internal RC oscillator frequency
(nominal f = 7.3728 MHz) trimmed
to ± 1% at Tamb = 25 °C
fWDOSC
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
Conditions
Variable clock
fosc = 12 MHz
Unit
Min
Max
Min
Max
7.189
7.557
7.189
7.557
MHz
320
520
320
520
kHz
0
12
-
-
MHz
83
-
-
-
ns
Crystal oscillator (P89LPC901)
fosc
oscillator frequency
tCLCL
clock cycle
fCLKP
CLKLP active frequency
0
8
-
-
MHz
glitch rejection, P1.5/RST pin
-
50
-
50
ns
signal acceptance, P1.5/RST pin
125
-
125
-
ns
glitch rejection, any pin except
P1.5/RST
-
15
-
15
ns
signal acceptance, any pin except
P1.5/RST
50
-
50
-
ns
see Figure 22
Glitch filter
External clock (P89LPC901)
tCHCX
HIGH time
see Figure 22
33
tCLCL − tCLCX
33
-
ns
tCLCX
LOW time
see Figure 22
33
tCLCL − tCHCX
33
-
ns
tCLCH
rise time
see Figure 22
-
8
-
8
ns
tCHCL
fall time
see Figure 22
-
8
-
8
ns
Shift register (UART mode 0 - P89LPC903)
tXLXL
serial port clock cycle time
see Figure 21
16 tCLCL
-
1333
-
ns
tQVXH
output data set-up to clock rising
edge
see Figure 21
13 tCLCL
-
1083
-
ns
tXHQX
output data hold after clock rising
edge
see Figure 21
-
tCLCL + 20
-
103
ns
tXHDX
input data hold after clock rising
edge
see Figure 21
-
0
-
0
ns
tDVXH
input data valid to clock rising edge see Figure 21
150
-
150
-
ns
[1]
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14465
Product data
Rev. 05 — 17 December 2004
46 of 53
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
Table 15: AC characteristics (P89LPC901)
VDD = 3.0V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, unless otherwise specified.[1]
Symbol
Parameter
Conditions
Variable clock
fosc = 18 MHz
Min
Max
Min
Max
Unit
fRCOSC
internal RC oscillator frequency
(nominal f = 7.3728 MHz) trimmed
to ± 1% at Tamb = 25 °C
7.189
7.557
7.189
7.557
MHz
fWDOSC
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
320
520
320
520
kHz
0
18
-
-
MHz
55
-
-
-
ns
Crystal oscillator
[2]
fosc
oscillator frequency
tCLCL
clock cycle
fCLKP
CLKLP active frequency
0
8
-
-
MHz
glitch rejection, P1.5/RST pin
-
50
-
50
ns
see Figure 22
Glitch filter
signal acceptance, P1.5/RST pin
125
-
125
-
ns
glitch rejection, any pin except
P1.5/RST
-
15
-
15
ns
signal acceptance, any pin except
P1.5/RST
50
-
50
-
ns
External clock
tCHCX
HIGH time
see Figure 22
22
tCLCL − tCLCX
22
-
ns
tCLCX
LOW time
see Figure 22
22
tCLCL − tCHCX
22
-
ns
tCLCH
rise time
see Figure 22
-
5
-
5
ns
tCHCL
fall time
see Figure 22
-
5
-
5
ns
[1]
[2]
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the
minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout
detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.
tXLXL
Clock
tXHQX
tQVXH
Output Data
0
Write to SBUF
Input Data
1
2
3
4
5
6
7
Valid
Valid
Valid
Valid
Valid
Valid
tXHDX
tXHDV
Set TI
Valid
Valid
Clear RI
Set RI
002aaa425
Fig 21. Shift register mode timing.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14465
Product data
Rev. 05 — 17 December 2004
47 of 53
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
VDD - 0.5 V
0.45 V
0.2 VDD + 0.9
0.2 VDD - 0.1 V
tCHCX
tCHCL
tCLCX
tCLCH
tC
002aaa416
Fig 22. External clock timing.
12. Comparator electrical characteristics
Table 16: Comparator electrical characteristics
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, unless otherwise specified.
Symbol
Parameter
VIO
offset voltage comparator inputs
VCR
common mode range comparator inputs
CMRR
[1]
Min
Typ
Max
Unit
-
-
±20
mV
0
-
VDD − 0.3
V
-
-
−50
dB
response time
-
250
500
ns
comparator enable to output valid
-
-
10
µs
-
-
±10
µA
[1]
common mode rejection ratio
input leakage current, comparator
IIL
Conditions
0 < VIN < VDD
This parameter is characterized, but not tested in production.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14465
Product data
Rev. 05 — 17 December 2004
48 of 53
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
13. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 23. SOT96-1 (SO8).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14465
Product data
Rev. 05 — 17 December 2004
49 of 53
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
ME
seating plane
D
A2
A
A1
L
c
Z
w M
b1
e
(e 1)
b
MH
b2
5
8
pin 1 index
E
1
4
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
b2
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.14
0.53
0.38
1.07
0.89
0.36
0.23
9.8
9.2
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
1.15
inches
0.17
0.02
0.13
0.068
0.045
0.021
0.015
0.042
0.035
0.014
0.009
0.39
0.36
0.26
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.045
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT97-1
050G01
MO-001
SC-504-8
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Fig 24. SOT97-1 (DIP8).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14465
Product data
Rev. 05 — 17 December 2004
50 of 53
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
14. Revision history
Table 17:
Revision history
Rev Date
05
20041217
CPCN
Description
-
Product data (9397 750 14465)
Modifications:
•
Added 18 MHz information.
04
20031121
-
Product data (9397 750 12293); ECN 853-2434 01-A14555 of 18 November 2003
03
20030929
-
Product data (9397 750 12031); ECN 853-2434 30348 of 11 September 2003
02
20030731
-
Product data (9397 750 11801); ECN 853-2434 30152 of 28 July 2003
01
20030602
-
Preliminary data (9397 750 11494)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14465
Product data
Rev. 05 — 17 December 2004
51 of 53
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
15. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
17. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected]
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14465
Rev. 05 — 17 December 2004
52 of 53
P89LPC901/902/903
Philips Semiconductors
8-bit microcontrollers with two-clock 80C51 core
Contents
1
2
2.1
2.2
3
3.1
4
5
5.1
5.2
6
7
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.11.1
8.12
8.12.1
8.12.2
8.12.3
8.12.4
8.12.5
8.12.6
8.12.7
8.13
8.13.1
8.13.2
8.14
8.14.1
8.14.2
8.14.3
8.15
8.16
8.16.1
8.16.2
8.16.3
8.16.4
8.16.5
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Principal features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Special function registers. . . . . . . . . . . . . . . . . . . . . 14
Functional description . . . . . . . . . . . . . . . . . . . . . . . 24
Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clock definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CPU clock (OSCCLK) . . . . . . . . . . . . . . . . . . . . . . . 24
Low speed oscillator option (P89LPC901) . . . . . . . . 24
Medium speed oscillator option (P89LPC901). . . . . 24
High speed oscillator option (P89LPC901) . . . . . . . 25
Clock output (P89LPC901) . . . . . . . . . . . . . . . . . . . 25
On-chip RC oscillator option . . . . . . . . . . . . . . . . . . 25
Watchdog oscillator option . . . . . . . . . . . . . . . . . . . . 25
External clock input option (P89LPC901) . . . . . . . . 25
CPU CLock (CCLK) wake-up delay . . . . . . . . . . . . . 27
CPU CLOCK (CCLK) modification: DIVM register . . 27
Low power select . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . 27
Data RAM arrangement . . . . . . . . . . . . . . . . . . . . . . 27
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
External interrupt inputs . . . . . . . . . . . . . . . . . . . . . . 28
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Quasi-bidirectional output configuration. . . . . . . . . . 31
Open-drain output configuration. . . . . . . . . . . . . . . . 31
Input-only configuration . . . . . . . . . . . . . . . . . . . . . . 31
Push-pull output configuration . . . . . . . . . . . . . . . . . 31
Port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . 31
Additional port features . . . . . . . . . . . . . . . . . . . . . . 32
Power monitoring functions . . . . . . . . . . . . . . . . . . . 32
Brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power-on detection . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power reduction modes . . . . . . . . . . . . . . . . . . . . . . 32
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Total Power-down mode . . . . . . . . . . . . . . . . . . . . . . 33
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . . . . . 34
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Mode 6 (P89LPC901) . . . . . . . . . . . . . . . . . . . . . . . 34
© Koninklijke Philips Electronics N.V. 2004.
Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 17 December 2004
Document order number: 9397 750 14465
8.16.6
8.17
8.18
8.18.1
8.18.2
8.18.3
8.18.4
8.18.5
8.18.6
8.18.7
8.18.8
8.18.9
Timer overflow toggle output (P89LPC901) . . . . . . . 35
Real-Time clock/system timer. . . . . . . . . . . . . . . . . . 35
UART (P89LPC903) . . . . . . . . . . . . . . . . . . . . . . . . . 35
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Baud rate generator and selection . . . . . . . . . . . . . . 36
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Transmit interrupts with double buffering
enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . 37
8.18.10
The 9th bit (bit 8) in double buffering (Modes 1, 2 and
3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.19
Analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.20
Internal reference voltage . . . . . . . . . . . . . . . . . . . . . 38
8.21
Comparator interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 38
8.22
Comparator and power reduction modes . . . . . . . . . 38
8.23
Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . . . . . . 39
8.24
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.25
Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.25.1
Software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.25.2
Dual data pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.26
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . 40
8.26.1
General description. . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.26.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.26.3
Flash organization . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.26.4
Flash programming and erasing . . . . . . . . . . . . . . . . 41
8.26.5
In-circuit programming (ICP). . . . . . . . . . . . . . . . . . . 41
8.26.6
In-application programming . . . . . . . . . . . . . . . . . . . 42
8.26.7
Using flash as data storage . . . . . . . . . . . . . . . . . . . 42
8.26.8
User configuration bytes . . . . . . . . . . . . . . . . . . . . . . 42
8.26.9
User sector security bytes . . . . . . . . . . . . . . . . . . . . 42
9
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10
Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 44
11
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 46
12
Comparator electrical characteristics . . . . . . . . . . . 48
13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52