Philips Semiconductors Product specification Dual D-type flip-flop 74ABT74 QUICK REFERENCE DATA SYMBOL DESCRIPTION CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 3.0 2.5 ns 0.5 ns tPLH tPHL Propagation delay CPn to Qn, Qn tOSLH tOSHL Output to Output skew CIN Input capacitance VI = 0V or VCC 3 pF ICC Total supply current Outputs disabled; VCC = 5.5V 50 µA CL = 50pF; VCC = 5V The 74ABT74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and Q outputs on the low-to-high transition of the clock. Data must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output. LOGIC SYMBOL (IEEE/IEC) PIN CONFIGURATION RD1 1 14 VCC D0 2 13 RD1 4 & S 5 3 C1 CP0 3 12 D1 2 SD1 4 11 CP1 1 Q0 5 10 SD1 Q0 6 9 Q1 GND 7 8 Q1 10 1D 6 R S 9 11 C2 12 SF00045 13 2D 8 R PIN DESCRIPTION PIN NUMBER SYMBOL 1, 2, 3, 4, 10, 11, 12, 13 RDn, Dn, Data inputs CPn, SDn NAME AND FUNCTION SF00047 LOGIC DIAGRAM 5, 6, 8, 9 Qn, Qn Data outputs 7 GND Ground (0V) 14 VCC Positive supply voltage SD 4, 10 LOGIC SYMBOL 2 12 RD 5, 9 1, 13 Q D0 D1 3 CP0 4 SD0 1 RD0 11 CP1 10 SD1 13 RD1 CP D 6, 8 3, 11 Q 2, 12 VCC = Pin 14 GND = Pin 7 Q0 Q0 Q1 Q1 SF00048 VCC = Pin 14 GND = Pin 7 5 6 9 8 SA00359 ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA 14-Pin Plastic DIP PACKAGES –40°C to +85°C 74ABT74 N 74ABT74 N SOT27-1 14-Pin plastic SO –40°C to +85°C 74ABT74 D 74ABT74 D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +85°C 74ABT74 DB 74ABT74 DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT74 PW 74ABT74PW DH SOT402-1 1995 Sep 22 1 DWG NUMBER 853-1813 15793 Philips Semiconductors Product specification Dual D-type flip-flop 74ABT74 FUNCTION TABLE INPUTS OUTPUTS NOTES: H = High voltage level h = High voltage level one setup time prior to low-to-high clock transition L = Low voltage level l = Low voltage level one setup time prior to low-to-high clock transition NC= No change from the previous setup X = Don’t care ↑ = Low-to-high clock transition ↑ = Not low-to-high clock transition * = This setup is unstable and will change when either set or reset return to the high level. OPERATING MODE SD RD CP D Q Q L H X X H L Asynchronous set H L X X L H Asynchronous reset L L X X H H Undetermined* H H ↑ h H L Load “1” H H ↑ l L H Load “0” H H ↑ X NC NC Hold ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 40 mA –65 to 150 °C DC supply voltage IIK DC input diode current VI DC input voltage3 IOK DC output diode current VI < 0 voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC PARAMETER UNIT DC supply voltage MIN MAX 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current –15 mA IOL Low-level output current 20 mA 0 10 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range 1995 Sep 22 2.0 2 V Philips Semiconductors Product specification Dual D-type flip-flop 74ABT74 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = –40°C to +85°C Tamb = +25°C MIN TYP MAX –0.9 –1.2 MIN UNIT MAX VIK Input clamp voltage VCC = 4.5V; IIK = –18mA VOH High-level output voltage VCC = 4.5V; IOH = –15mA; VI = VIL or VIH VOL Low-level output voltage VCC = 4.5V; IOL = 20mA; VI = VIL or VIH 0.35 0.5 0.5 V Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA IOFF Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA ICEX Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA IO Output current1 VCC = 5.5V; VO = 2.5V –75 –180 –180 mA ICC Quiescent supply current VCC = 5.5V; VI = GND or VCC 2 50 50 µA Additional supply current per input pin2 VCC = 5.5V; One data input at 3.4V, other inputs at VCC or GND 0.25 500 500 µA II ∆ICC 2.5 2.9 –50 –1.2 V 2.5 –50 V NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flop or latch after applying the power. AC ELECTRICAL CHARACTERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V WAVEFORM Tamb = –40°C to +85°C VCC = +5.0V ±0.5V MIN TYP fMAX Maximum clock frequency 1 180 250 tPLH tPHL Propagation delay CPn to Qn, Qn 1 1.0 1.0 3.0 2.5 4.2 3.5 1.0 1.0 4.7 4.0 ns tPLH tPHL Propagation delay Sn, Rn to Qn, Qn 3 1.0 1.0 3.4 2.9 4.9 4.5 1.0 1.0 6.2 5.2 ns Output to Output skew An or Bn to Yn 4 0.5 0.6 0.6 ns tOSHL tOSLH1 MAX MIN UNIT MAX 150 MHz NOTE: 1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the the same direction, either HIGH–to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter guaranteed by design. AC SETUP REQUIREMENTS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V WAVEFORM Tamb = –40°C to +85°C VCC = +5.0V ±0.5V UNIT MIN TYP MIN 1 2.6 2.4 1.4 1.4 2.6 2.4 ns Hold time, high or low Dn to CPn 1 0 0 –1.4 –1.4 0 0 ns tw (H) tw (L) CPn pulse width, high or low 1 1.7 1.7 1.0 1.0 2.1 2.1 ns tw (L) SDn, RDn pulse width, low 3 2.0 1.3 2.2 ns Recovery time SDn, RDn to CPn 2 2.1 1.4 2.4 ns tsu (H) tsu (L) Setup time, high or low Dn to CPn th (H) th (L) trec 1995 Sep 22 3 Philips Semiconductors Product specification Dual D-type flip-flop 74ABT74 AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V The shaded areas indicate when the input is permitted to change for predictable output performance Dn VM tsu(L) VM VM tsu(H) th(L) VM tw(L) SDn VM VM th(H) 1/fmax CPn VM VM tw(L) tw(H) VM VM tPHL tPLH tPHL tPLH Qn tw(L) RDn VM Qn VM VM VM VM tPLH tPHL tPLH tPHL VM VM Qn VM VM Qn SF00050 Waveform 3. Propagation delay for set and reset to output, set and reset pulse width SF00049 Waveform 1. Propagation delay for data to output, data setup time and hold times, and clock width, and maximum clock frequency INPUT SDn or RDn VM OUTPUT trec CPn tPHL MIN VM OUTPUT N same part SF00051 Waveform 2. Recovery time for set or reset to clock tPLH MIN tPLH MAX tOSLH tPHL MAX tOSHL SA00381 Waveform 4. Common edge skew 1995 Sep 22 4 Philips Semiconductors Product specification Dual D-type flip-flop 74ABT74 TEST CIRCUIT AND WAVEFORMS tW 90% VCC 90% VM NEGATIVE PULSE AMP (V) VM 10% 10% 0V PULSE GENERATOR VOUT VIN D.U.T. RT CL tTLH (tR) tTHL (tF) tTLH (tR) RL tTHL (tF) 90% POSITIVE PULSE AMP (V) 90% VM VM 10% Test Circuit for Outputs 10% tW 0V VM = 1.5V Input Pulse Definition DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS FAMILY 74ABT Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SH00067 1995 Sep 22 5