INTEGRATED CIRCUITS 74F259 Latch Product specification IC15 Data Handbook 1989 Apr 11 Philips Semiconductors Product specification Latch 74F259 FEATURES PIN CONFIGURATION • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability • Output from each storage bit available • Random (addressable) data entry • Easily expandable • Common reset input • Useful as 1-of-8 active-High decoder A0 1 16 V CC A1 2 15 MR A2 3 14 E Q0 4 13 D Q1 5 12 Q7 Q2 6 11 Q6 Q3 7 10 Q5 8 9 Q4 GND DESCRIPTION SF00823 The 74F259 addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). In the addressable latch mode, data at the Data inputs is written into the addressed latches. The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states. In the store mode, all latches remain in their previous states and are unaffected by the Data or Address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held High (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode (MR=E=Low), addressed outputs will follow the level of the Data input, with all other outputs Low. In the Master Reset mode, all outputs are Low and unaffected by the Address and Data inputs. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7.5ns 31mA 74F259 ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG DWG # 16-pin plastic DIP N74F259N SOT38-4 16-pin plastic SO N74F259D SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D A0, A1, A2 E MR DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Data input 1.0/1.0 20µA/0.6mA Address inputs 1.0/1.0 20µA/0.6mA Enable input (active Low) 1.0/1.0 20µA/0.6mA Master Reset inputs (active Low) 1.0/1.0 20µA/0.6mA 50/33 1.0mA/20mA Q0 – Q7 Data outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. 1989 Apr 11 2 853–0362 06316 Philips Semiconductors Product specification Latch 74F259 LOGIC SYMBOL IEC/IEEE SYMBOL 1 0 2 8M 3 2 14 13 1 2 3 G8 13 Z9 15 D 14 A0 A1 Z10 A3 E 15 MR Q0 Q1 4 Q2 5 6 Q3 7 Q4 9 0 7 Q5 10 VCC = Pin 16 GND = Pin 8 Q6 11 Q7 12 9, 10D 10m 0R 4 9, 10D 10m 1R 9, 10D 10m 2R 9, 10D 10m 3R 5 9, 10D 10m 4R 9, 10D 10m 5R 9 9, 10D 10m 6R 11 9, 10D 10m 7R 12 SF00824 6 7 10 SF00825 FUNCTION TABLE INPUTS H L X d q OUTPUTS MR E D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 L H X X X L L d L L L L L L L L L L L L Q=d L L L L L L L L L d H L L L Q=d L L L L L L L L d • • • L H L L L Q=d L L L L L • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • L L d H H H L L L L L L L Q=d H H X X X X q0 q1 q2 q3 q4 q5 q6 q7 H L d L L L Q=d q1 q2 q3 q4 q5 q6 q7 H L d H L L q0 Q=d q2 q3 q4 q5 q6 q7 H L d L H L q0 q1 Q=d q3 q4 q5 q6 q7 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • H = = = = = OPERATING MODE Master Reset Demultiplex Demulti lex (active-High decoder when h D D=H) H) Store (do nothing) Addressable Latch L d H H H q0 q1 q2 q3 q4 q5 q6 Q=d High voltage level Low voltage level Don’t care High or Low data one setup time prior to the Low-to-High Enable transition Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared. 1989 Apr 11 3 Philips Semiconductors Product specification Latch 74F259 LOGIC DIAGRAM 12 Q7 11 Q6 10 9 Q4 7 Q3 6 D E MR Q2 13 14 15 A2 3 A1 2 A0 Q5 5 1 4 Q1 Q0 VCC = Pin 16 GND = Pin 8 SF00826 1989 Apr 11 4 Philips Semiconductors Product specification Latch 74F259 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT V VCC Supply voltage –0.5 to +7.0 VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 40 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL LIMITS UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA 70 °C Tamb Operating free-air temperature range V V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) PARAMETER SYMBOL TEST LIMITS CONDITIONS1 MIN ±10%VCC 2.5 VIH = MIN, IOL = MAX ±5%VCC 2.7 VCC = MIN, VIL = MAX, ±10%VCC VIH = MIN, IOL = MAX ±5%VCC VOH High-level output voltage VCC = MIN, VIL = MAX, VOL Low-level output voltage VIK Input clamp voltage VCC = MIN, II = IIK TYP2 UNIT MAX V 3.4 V 0.35 0.50 V 0.35 0.50 V –0.73 –1.2 V II Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –0.6 mA IOS Short-circuit output current3 VCC = MAX –150 mA ICC Supply current (total) 24 46 mA 37 75 ICCH VCC = MAX ICCL –60 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. To reduce the effect of external noise during test. 4. Not more than one output should be shorted at a time. For testing IOS, the use of High-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1989 Apr 11 5 Philips Semiconductors Product specification Latch 74F259 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER tPLH tPHL Propagation delay D to Qn tPLH tPHL Propagation delay E to Qn tPLH tPHL Propagation delay An to Qn tPHL Propagation delay MR to Qn TEST CONDITION Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG Tamb = +25°C VCC = +5V CL = 50pF, RL = 500Ω Tamb = 0°C to +70°C VCC = +5V ± 10% CL = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX 4.0 3.0 7.0 5.0 9.0 7.0 4.0 2.5 10.0 7.5 ns 4.5 3.0 8.0 5.0 10.5 7.0 4.5 3.0 12.0 8.0 ns 5.0 4.0 10.0 8.5 14.0 9.5 5.0 4.0 14.5 10.0 ns 5.0 7.0 9.0 4.5 10.0 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST Tamb = +25°C VCC = +5.0V CONDITION CL = 50pF, RL = 500Ω MIN TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL= 50pF, RL = 500Ω MIN UNIT MAX ts(H) ts(L) Setup time, High or Low D to E Waveform NO TAG 3.0 6.5 3.0 7.0 ns th(H) th(L) Hold time, High or Low D to E Waveform NO TAG 0 0 0 0 ns ts(H) ts(L) Setup time, High or Low An to E1 Waveform NO TAG 2.0 2.0 2.0 2.0 ns th(H) th(L) Hold time, High or Low An to E2 Waveform NO TAG 0 0 0 0 ns tw(L) E Pulse width, Low Waveform NO TAG 7.5 8.0 ns tw(L) MR Pulse width, Low Waveform NO TAG 3.0 3.0 ns NOTES: 1. The Address to Enable setup time is the time before the High-to-Low Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. 2. The Address to Enable hold time is the time before the Low-to-High Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. 1989 Apr 11 6 Philips Semiconductors Product specification Latch 74F259 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. D An VM VM tPHL tPLH tW(L) E VM VM tPHL Qn VM Qn tPLH VM VM VM SF00811 VM Waveform 2. Propagation Delay Address to Output SF00827 Waveform 1. Propagation Delay, Enable Input to Output, Enable Pulse Width D tW(L) VM MR VM VM ts(H) tPHL Qn VM VM E VM th(H) VM ts(L) th(L) VM VM SF00812 Waveform 3. Master Reset Pulse Width and Master Reset to Output Delay Qn Q=D Q=D SF00828 Waveform 4. Data Setup and Hold Times An VM E Address Stable VM ts th VM VM SF00814 Waveform 5. Address Setup and Hold Times 1989 Apr 11 7 Philips Semiconductors Product specification Latch 74F259 TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN tw 90% VM D.U.T. RT CL RL AMP (V) VM 10% VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% Test Circuit for Totem-Pole Outputs 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 1989 Apr 11 8 Philips Semiconductors Product specification Latch 74F259 DIP16: plastic dual in-line package; 16 leads (300 mil) 1989 Apr 11 9 SOT38-4 Philips Semiconductors Product specification Latch 74F259 SO16: plastic small outline package; 16 leads; body width 3.9 mm 1989 Apr 11 10 SOT109-1 Philips Semiconductors Product specification Latch 74F259 NOTES 1989 Apr 11 11 Philips Semiconductors Product specification Latch 74F259 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 12 Date of release: 10-98 9397-750-05109