Freescale Semiconductor Application Note Document Number: AN5187 Rev. 1.0, 9/2015 PT2000: Three Injectors with Freewheeling and DCDC 1 Introduction This application note examines an example of a three cylinder internal combustion engine (ICE) injector drive. The high-voltage is provided by a boost converter managed by the PT2000. It describes a typical hardware topology and related software example to drive three injectors managed in three banks, allowing a full overlap and a DC/DC converter in resonant mode. The PT2000 is supplied by a battery voltage between 9.0 V and 32 V. An external 5.0 V must be supplied to the VCC5 and the VCCIO pin, to internally supply the I/O buffers. In this example, the VCCP voltage is internally generated to enable the drivers. If VBAT voltage is set higher than 16 V then VCCP has to be forced externally. The boost converter topology is defined to manage DC/DC. A Pi filter prevents circuitry disturbance propagation from the boost regulation area to battery line. In this configuration, full overlap injection is possible, and to reduce power dissipation and show some capabilities of the PT2000 freewheeling low-sides are used instead of diode. Freescale analog ICs are manufactured using the SMARTMOS process, a combinational BiCMOS manufacturing flow integrating precision analog, power functions, and dense CMOS logic together on a single cost-effective die. © Freescale Semiconductor, Inc., 2015. All rights reserved. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2 Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 3 Application Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 4 Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 4.1 Current Profile Management for Injection . . . . . . . . . . . . . . .4 4.2 DC-DC Resonant Mode Management . . . . . . . . . . . . . . . . .13 5 PCB Layout Recommendations. . . . . . . . . . . . . . . . . . . . . . . . .19 5.1 Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.2 Sense Resistors Connection . . . . . . . . . . . . . . . . . . . . . . . .19 6 Application Source Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6 Application Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6.1 Injection Banks Management Source Code . . . . . . . . . . . . .20 6.2 DC-DC Management Source Code . . . . . . . . . . . . . . . . . . .25 7 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.7nF 4.7nF 4.7nF 4.7nF VPWR 100nF VBoost 4.7nF 330Ω 15mΩ 4.7nF 330Ω 4.7nF 4.7nF 4.7nF 330pF 330pF MCU ADC 330Ω 330Ω 330Ω 330Ω 100nF 100nF 4.7nF VBoost VBoost 15mΩ 330Ω FW1 BANK2 VBoost BANK1 4.7nF 4.7nF 330Ω START2 START1 START3 VSENSE_N2 OA_2 VSENSE_P2 D_LS4 G_LS4 D_LS3 G_LS3 B_HS4 G_HS4 S_HS4 B_HS3 G_HS3 S_HS3 VSENSE_N1 D_LS2 G_LS2 OA_1 VSENSE_P1 D_LS1 G_LS1 B_HS2 G_HS2 S_HS2 B_HS1 G_HS1 S_HS1 FLAG0 START6 START5 100nF VPWR 470μF DBG FLAG3 100nF 100nF 100nF 1μH 100nF Supplies 470μF 1μH 6μH 100nF DRVEN MOSI START4 To MCU IOs OA_3 D_LS6 G_LS6 D_LS5 G_LS5 B_HS6 G_HS6 S_HS6 B_HS5 G_HS5 S_HS5 VSENSE_N5 VSENSE_P5 G_LS7 D_LS7 VBOOST VSENSE_N6 VSENSE_P6 RESET To MCU SPI SCKL MC33PT2000 3 Cylinder 3 Bank START7 VBAT IRQB To MCU IOs (optional) FLAG1 VCCP INJECTOR1 INJECTOR2 FLAG2 VCC2P5 100nF FW2 CSB VCC5 VPWR MCU ADC MISO VCCIO CLK AGND DGND PGND 2 330pF MCU ADC 330pF 330Ω 4.7nF 330Ω 4.7nF 330Ω VBoost 10μH 10mΩ VPWR 4.7nF 100nF 330pF 4.7nF VPWR 4.7nF 220nF 680μF VBoost DC/DC 5.1Ω 100nF BANK3 4.7nF 4.7nF 330Ω VBoost 330Ω 15mΩ FW3 2 INJECTOR3 To MCU eTPU APPLICATION SCHEMATIC Application Schematic Figure 1. Typical Four Injector Two Bank Application Schematic AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor APPLICATION INSTRUCTIONS 3 Application Instructions This topology can be used on the KITPT2000FRDM3C evaluation board. Register settings and microcode downloads can be achieved by using the KL25Z embedded on the KITPT2000FRDM3C. This topology manages three banks of three cylinders. Each bank is individually managed by one microcore, as follows: • The bank # 1 is managed by the digital microcore Uc0Ch1 • The bank # 2 is managed by the digital microcore Uc1Ch1. • The bank # 3is managed by the digital microcore Uc0Ch2. The DCDC is managed by microcore Uc0Ch3. The following is the start-up sequence: • Apply a battery voltage between 9.0 V and 16 V. • Download the registers Channel Configuration, Main Configuration, IO Configuration, and then Diagnostic Configuration. • Download the dedicated microcode in the Logic Channel 1, Logic Channel 2, and Logic Channel 3 Data RAM. • Set to ‘1’ to the pre-flash enable bit and the en_dual_seq bit in the Flash_enable register of channel 1 (0x100), channel 2 (0x120), and channel 3 (0x140). The registers configuration and the microcodes are detailed in the following chapters. Once the DC/DC converter output has reached its nominal voltage, the injector drivers can be actuated with the STARTx pins. Each STARTx pin individually triggers each injector pin rising edge and stops actuation on the falling edge. • START1 drives INJECTOR 1 • START2 drives INJECTOR 2 • START3 drives INJECTOR 3 Boost regulation is stopped during the injection boost phase. AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor 3 SOFTWARE REQUIREMENTS 4 4.1 Software Requirements Current Profile Management for Injection The current profile is managed to generate an initial high current through the injector. This high current slew rate minimizes the opening delay. This high current is maintained during a given time to ensure injector opening, then is decreased to maintain the injector open, up to the End Of Injection (EOI). The code dedicated to the injection is loaded into the Code RAM 1. This code is executed independently by the microcores Uc0Ch1 and Uc1Ch1. Each one of the microcores generate a current profile, as described through the injector per the STARTx pin state as illustrated in Figure 2. Figure 2. Typical Peak and Hold Current Profile When a rising edge is detected on a STARTx pin, the injection starts with the injection Boost phase. This profile can be stopped at any time by detecting a falling edge on the STARTx pin. In this case, the End Of Injection phase is executed. During the Boost phase, the corresponding low-side driver is simultaneously switched on with the high-side switch connected to the VBOOST voltage. If the boost current target IBOOST is reached, the high-side driver is switched off and the current recirculates for a fixed time (tPEAK_OFF) through the diode connected to ground, then the Peak phase starts. During the Peak phase, the high-side switch connected to VBAT voltage is turned on. If the IPEAK current target is met, the high-side driver is switched off and the current recirculates through the diode connected ground for the fixed time (tPEAK_OFF). The high-side driver is then switched on again. This cycle repeats until the internal counter reaches its terminal value (tPEAK_TOT), then the Bypass phase begins. During the Bypass phase, all low-side and high-side switches are turned off. The current decays through the injector, the diode connected to ground, and the diode connected to VBOOST for a fixed time (tBYPASS). The Hold phase then starts. During the Hold phase, the low-side driver is simultaneously switched on with the high-side switch connected to the VBAT voltage. If the hold current target IHOLD is reached, the high-side driver is switched off and the current recirculates through the diode connected to ground for a fixed time (tHOLD_OFF). The high-side driver is switched on again, and the cycle repeats until the STARTx pin goes low or the internal counter reaches its terminal value (tHOLD_TOT (time out)). The End Of Injection is forced if no falling edge is detected on the STARTx pin. AN5187 Application Note Rev. 1.0 9/2015 4 Analog Integrated Circuit Device Data Freescale Semiconductor SOFTWARE REQUIREMENTS All the current thresholds and timings are accessed in the Data RAM. The typical values are in Table 1., but must be defined according to the injector used and the injection profile expected. Table 1. Example of Injection Current Profile Key Parameters (RSENSE = 15 m) Parameter Name Description Value Current threshold in Boost phase 14 A IPEAK Current threshold in Peak phase (Depends on injectors type) 6.0 A IHOLD Current threshold in Hold phase 3.0 A tPEAK_OFF Fixed time for high-side switch off in Peak phase 10 s tPEAK_TOT Fixed time for end of Peak phase 500 s Fixed time for Bypass phase 20 s tHOLD_OFF Fixed time for high-side switch off in Hold phase 10 s tHOLD_TOT Fixed time for end of Hold phase (timeout) 10 ms IBOOST tBYPASS In the present case, most of the code branches (jump) are managed according to the counters end of count and the current threshold, by the means of the wait table. The wait table rows are affected, as shown in Table 2., and are changed according to the injection phase. Table 2. Example of Wait Table Definition Phase Boost Phase Peak Phase Bypass Phase Hold Phase EOI Phase Row 1 If startx goes low then jumps to EOI phase If startx goes low, then jumps to EOI phase If startx goes low, then jumps to EOI phase If startx goes low, then jumps to EOI phase - Row 2 If the injection current reaches IBOOST then jumps to Peak phase If tPEAK_TOT is reached, then jumps to Bypass phase If tBYPASS is reached, then jumps to Hold phase If tHOLD_TOT is reached, then jumps to EOI phase - Row3 - if tPEAK_OFF is reached, jumps to Peak On phase (sub phase) - if tHOLD_OFF is reached, jumps to Hold On phase (sub phase) - Row 4 - if IPEAK is reached, jumps to Hold Off phase (sub phase) - if IHOLD is reached, jumps to Hold Off phase (sub phase) - Row 5 - - - - - A rising edge issues an injection start. A falling edge triggers the end of injection. In case of an overlap between two STARTx pins on the same bank, it is manage by the Smart Start function of the device. In this case, the first STARTx rising edge is considered. The second STARTx pin high-state is consider when the first actuation is finished. The action of the injection corresponding to the second STARTx pin is stopped when the second STARTx pin falling edge occurs. AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor 5 SOFTWARE REQUIREMENTS BANK 1 Start1 IINJECTOR1 BANK 2 Start2 IINJECTOR2 BANK 3 Start3 IINJECTOR3 t Figure 3. Actuation Driven by STARTx Pins With Possible Full Overlap 4.1.1 SPI Registers Setup The PT2000 registers are setup according their default states, unless defined by the following. 4.1.1.1 Main Configuration Registers 4.1.1.1.1 CLK Configuration Registers A 1.0 MHz CLK has to be supplied from the main MCU to the PT2000. This CLK is then multiplied by a factor to generate the PLL, which is the clock for the microcore memories. In this example, the multiplicator factor chosen is 24, meaning a PLL at 24 MHz. This factor is set by PLL_Config register (1A7h). Table 3. PLL_Config (1A7h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLL_spre PLL_fact ad_disabl or e Name Reserved Value 00000000000000 0 1 To run two microcores per channel, the Clock_Prescaler register (1A0h) must be setup with a ck_per value of 2 or 3. In this case, the main CLK (“ck”) is set to 6.0 MHz. ck = ck_sys/(ck_per +1) = 24 MHz/(3+1) = 6.0 MHz Table 4. Clock_Prescaler Register (1A0h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Name Reserved ck_per Value - 000011 1 0 AN5187 Application Note Rev. 1.0 9/2015 6 Analog Integrated Circuit Device Data Freescale Semiconductor SOFTWARE REQUIREMENTS 4.1.1.1.2 Offset Compensation CLK Registers To improve current accuracy offset compensation is enabled each time the microcore is in the idle state, which means the related start pin is low. To make this work, the CLK offset compensation must be set to a maximum of 500 kHz. As shown in CLK Configuration Registers, page 6, the PLL (“ck_sys”) is set to 24 MHz. To get a ck_ofscomp to 500 kHz. a prescaler set to 47d + 1d is needed. Table 5. Ck_ofscmp_Prescaler(1A4h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 Name Reserved ck_ofscmp_per Value 00000000 00101111 2 1 0 VCC5 VCC5 250mV Bias voltage Current sense Amp_x gain Vsense P Curx_fbk Diff AMP x Comp x Offset comp DACx (5+1bit) Vsense N DACx 8bit Figure 4. Offset Compensation Block Diagram As shown in Figure 4, a 5+1-bit DAC is use to compensate the offset. When the “stoc on” instruction runs the 8-bit DAC is automatically set to 253 mV and the 5+1 DAC for offset compensation tries to find the best value to get 250 mV. This is done during idle phase and shuts down as soon as the start pin goes high. Each new offset compensation starts based on the result of the previous offset compensation run for this current measurement channel. If the offset compensation is stopped from the digital sequencer when the analog offset compensation is not finished, the procedure is aborted, maintaining the last compensation value reached when the procedure was interrupted. A full offset compensation takes 2.0 s (500 kHz) x 31 steps = 62 s. 4.1.2 Injection Bank Management Register Setup The PT2000 registers are setup according their default states or setup automatically by the PT2000 IDE (i.e. checksum registers, code width), unless defined by the following. 4.1.2.1 IO Configuration Registers These registers configure the crossbar switch to give access to output drivers, current sense to each microcore. 4.1.2.1.1 Output Driver Access The Uc0Ch1 microcore must have access to the HS1, HS2, LS1, and LS2 pre-drivers. Table 6. Out_acc_uc0_ch1 Register (160h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Reserv c0_ch1 c0_ch1 c0_ch1 c0_ch1 c0_ch1 c0_ch1 c0_ch1 Name c0_ch1 c0_ch1 c0_ch1 c0_ch1 c0_ch1 c0_ch1 c0_ch1 c0_ch1 ed _ls8 _ls7 _ls6 _ls5 _ls4 _ls3 _ls2 _ls1 _hs7 _hs6 _hs5 _hs4 _hs3 _hs2 _hs1 Value 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 In the same way, the Uc1Ch1 must have access to the pre-drivers HS3, HS4, LS3, and LS4. AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor 7 SOFTWARE REQUIREMENTS Table 7. Out_acc_uc1_ch1 Register (161h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Reserv c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 Name c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 ed _ls8 _ls7 _ls6 _ls5 _ls4 _ls3 _ls2 _ls1 _hs7 _hs6 _hs5 _hs4 _hs3 _hs2 _hs1 Value 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 The Uc0Ch1 microcore has default access to the current sense block # 1, and to microcore Uc1Ch1 to the current sense block # 2. The corresponding registers content doesn’t need to be changed. In the same way, the Uc0Ch2 must have access to the pre-drivers HS5, HS6, LS5, and LS6. Table 8. Out_acc_uc0_ch2 Register (162h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Reserv c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 Name c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 c1_ch1 ed _ls8 _ls7 _ls6 _ls5 _ls4 _ls3 _ls2 _ls1 _hs7 _hs6 _hs5 _hs4 _hs3 _hs2 _hs1 Value 0 4.1.2.1.2 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 Current Sense Access The following registers give access to current sense block to the specified microcore. The Uc0Ch1 microcore must have access to current sense 1 and Uc1Ch1 to current sense 2. Table 9. Cur_block_access_part1 Register (166h) Bit 15 14 13 12 acc_u acc_u acc_u acc_u c1_ch c1_ch c1_ch c1_ch 1_curr Name 1_curr 1_curr 1_curr 6H_6N 5H_5N 6L 5L eg eg Value 0 0 0 0 11 acc_u c1_ch 1_curr 4 0 10 9 8 7 6 5 4 3 2 1 0 acc_u acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc c1_ch 0_ch1_ 0_ch1_ 1_ch1_ 1_ch1_ 0_ch1_ 0_ch1_ 0_ch1_ 0_ch1_ 0_ch1_ 0_ch1_ 1_curr curr6H curr5H curr2 curr1 curr6L curr5L curr4 curr3 curr2 curr1 3 _6Neg _5Neg 0 1 0 0 0 0 0 0 0 0 1 8 7 6 5 4 3 2 1 0 The Uc0Ch2 microcore must have access to current sense 3. Table 10. Cur_block_access_part2 Register (167h) Bit 15 14 13 12 acc_u acc_u acc_u acc_u c1_ch c1_ch c1_ch c1_ch 2_curr Name 2_curr 2_curr 2_curr 6H_6N 5H_5N 6L 5L eg eg Value 0 0 0 0 11 acc_u c1_ch 2_curr 4 0 10 9 acc_u acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc c1_ch 0_ch2_ 0_ch2_ 1_ch2_ 1_ch2_ 0_ch2_ 0_ch2_ 0_ch2_ 0_ch2_ 0_ch2_ 0_ch2_ 2_curr curr6H curr5H curr2 curr1 curr6L curr5L curr4 curr3 curr2 curr1 3 _6Neg _5Neg 0 0 0 0 0 0 0 0 1 0 0 AN5187 Application Note Rev. 1.0 9/2015 8 Analog Integrated Circuit Device Data Freescale Semiconductor SOFTWARE REQUIREMENTS 4.1.2.1.3 Freewheeling Access As mentioned previously, to reduce power dissipation and to show PT2000 capability, a freewheeling low-side is used instead of a diode. One of the features of the PT2000 is to control the FW low-side, automatically depending on the high-side command. Control of the freewheeling is done through microcore using the “stfw” instruction. There is no need to configure the Fw_external_request register (16Ah). High-side on VBAT is the one used as a command, this high-side has to be ON even during the boost phase, to make sure the FW low-side is OFF. The following configuration is used in this example: . Table 11. Freewheeling Link Register Freewheeling Pre-driver Output Related Pre-driver High-side LS1 HS1 LS3 HS3 LS5 HS5 Table 12. Fw_link (169h) Bit Name 15 14 Reserve Flag3_f d w_link Reset 0 13 12 11 Flag2_f w_link Flag1_f w_link Flag0_f w_link Reserved 0 0 0 00 0 10 9 8 7 6 5 4 3 2 1 0 Hs7_f Reserv Ls7_fw Ls6_fw Ls5_fw Ls4_fw Ls3_fw Ls2_fw Ls1_fw w_link ed _link _link _link _link _link _link _link 0 0 0 0 1 0 1 0 1 The time between the high-side and FW low-side (“dead time”) command is selectable by the SPI, to avoid cross conduction (refer to Table 20. High-side Output Configuration Register). stfw instruction: To automatically control the freewheeling low-side, the stfw auto instruction is used in the microcode. Shortcut 1 is considered as the high-side using freewheeling. In this case, HS1 uses LS1 as freewheeling the shortcut definition, for Uc0CH1 is: dfsct hs1 hs2 ls2; in this case ls1 switches according to the hs1 command. 4.1.2.1.4 OAx Settings (optional) For safety purposes, it is possible to send an image of the current going through the load directly to the MCU through the OAx pins. The following settings map the current sense 1 to OA1 and current sense 2 to OA2. Table 1. Oa_out1_config (197h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved oa1_g1 oa_sel1 oa1_gain oa1_en Value 000000000 0 000 00 1 Table 13. Oa_out2_config (198h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved oa2_g1 oa_sel2 oa2_gain oa2_en Value 000000000 0 000 00 1 If this feature is mandatory in the application, special care needs to be taken during the selection of the current for each bank. For example, if it needs to monitor on the OAx pins of each current sense at the same time, the following current sense needs to be selected: -Bank 1 : current sense 1 mapped to OA1 -Bank 2: current sense 2 mapped to OA2 -Bank3 : current sense 5 mapped to OA3 AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor 9 SOFTWARE REQUIREMENTS 4.1.2.2 Channel 1-2 Configuration Registers The following registers are used to configure each channel used to control injectors. 4.1.2.2.1 Startx Pin Sensitivity Registers The injectors 1, 2, and 3 are driven according to the logic level of their respective STARTx pin. A high level on STARTx triggers the activation of the corresponding injector. A low level on the STARTx pin automatically stops the actuation, whatever the injection phase. The Uc0Ch1microcore must be enabled by START1 pin, while the Uc1Ch1 microcore must be enabled by the START2 pin, and Uc0Ch2 must be enabled by START3 pin. Consequently, Start_config_reg_part1 register of the channel 1 (103h) must be setup, as shown in Table 14. . Table 14. Start_config_reg_part1 Registers (103h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 start8_ start7_ start6_ start5_ start4_ start3_ start2_ start1_ start8_ start7_ start6_ start5_ start4_ start3_ start2_ start1_ Name sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u sens_u c1 c1 c1 c1 c1 c1 c1 c1 c0 c0 c0 c0 c0 c0 c0 c0 Value 00 0 0 0 0 1 0 0 0 0 0 0 0 0 1 2 1 0 In the same way Start_config_reg_part1 register of the channel 2 (123h) must be setup, as shown in Table 15. Table 15. Start_config_reg_part1 Registers (123h) Bit Name 15 14 13 12 11 10 9 8 7 6 5 4 3 start8_ start7_ start6_ start5_ start4_ start3_ start2_ start1_ start8_ start7_ start6_ start5_ start4_ start3_ start2_ start1_ sens_ sens_ sens_ sens_ sens_ sens_ sens_ sens_ sens_ sens_ sens_ sens_ sens_ sens_ sens_ sens_ uc1 uc1 uc1 uc1 uc1 uc1 uc1 uc1 uc0 uc0 uc0 uc0 uc0 uc0 uc0 uc0 Value 00 4.1.2.2.2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Entry Point Registers Entry point registers define where each microcore starts in each channel. With the new PT2000 IDE, it is possible to specify a label as a start point and the following registers are set automatically. For example the “init0” label is the starting point of Uc0Ch1. If this feature is not used, the following register has to be set manually. In the code example, the entry point of Uc0Ch1 is 0 as the first line executed, and is the first Code RAM line of the channel 1. Table 16. Uc0_entry_point Registers (10Ah) of Channel 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 Name Reserved entry_point_address Reset 000000 0000000000 3 2 1 0 3 2 1 0 The code entry point of Uc1Ch1 is the 31h Code RAM line of the channel 1. Table 17. Uc1_entry_point Registers (10Bh) of Channel 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 Name Reserved entry_point_address Reset 000000 0000110001 The same configuration must be done for Channel2. AN5187 Application Note Rev. 1.0 9/2015 10 Analog Integrated Circuit Device Data Freescale Semiconductor SOFTWARE REQUIREMENTS Table 18. Uc0_entry_point Registers (12Ah) of Channel 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 Name Reserved entry_point_address Reset 000000 0000000000 3 2 1 0 3 2 1 0 The code entry point of Uc1Ch1 is the 2Fh Code RAM line of the channel 1. Table 19. Uc1_entry_point Registers (12Bh) of Channel 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 Name Reserved entry_point_address Reset 000000 0000110001 4.1.2.3 Diagnosis Configuration Registers The high-side and low-side drivers must be directly controlled by the microcores. Consequently, the output_routing fields of the high-side and low-side driver’s output configuration register must be set to the value 15. Dead time bits need to be set to avoid cross conduction between high-side and low-side freewheeling. tFWDLY = Tck x (Dead_time + 1) = 1/6 MHz x (3 + 1) = 668 ns Table 20. Hsx_output_config Registers (1DAh, 1DDh, 1E0h, 1E3h, 1E6h, 1ECh) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name HSx ovr HSx Vds ref reserved dead_time output_routing inv Value 0 0 000 00011 11111 0 Table 21. Lsx_output_config Registers (1C2h, 1C5h, 1C8h, 1CBh, 1CEh, 1D1h, 1D4h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name LSx_o vr Reserved output_routing inv Value 0 000000000 11111 0 VBAT G_HS1 G_LS1 FW HS1 command LS1 FW command tFWDLY tFWDLY Figure 5. Automatic Freewheeling Example AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor 11 SOFTWARE REQUIREMENTS 4.1.3 Injection Banks Management Algorithm Initialization Phase Current sense operational amplifier gain setting Load the eoinj line label Code RAM address into the register jr1 Load the idle line label Code RAM address into the register jr2 Define wait table entry # 1: Jump to End Of Injection Phase if the start signal goes low Shortcut definition Idle Phase Define wait table entry # 2: Jump to Shortcut if start1 goes high Start Offset compensation Wait for wait table entry # 2 Wait entry # 2 satisfied start pin high Driver shortcut affectation Shortcut # 1 <= HS1 (VBAT) Shortcut # 2 <= HS2 (VBOOST) Shortcut # 3 <= LS2 Stop Offset Compensation Jump to Boost Phase Wait entry # 2 satisfied Iboost reached Peak On Phase Vbat MOSFET (HS1) and LS MOSFET (LSx) turn on, Vboost MOSFET (HS2) turn off Wait for wait table entry 1, 2 or 4 to be satisfied Wait entry # 4 satisfied Ipeak reached Wait entry # 2 satisfied Wait entry # 3 satisfied Peak Phase Load the total length of the peak phase in counter 1 Load the peak current threshold in the current DAC Define wait table entry # 2: Jump to Bypass Phase when tc1 reaches end of count Define wait table entry # 3: Jump to Peak On Phase when tc2 reaches end of count Define wait table entry # 4: Jump to Peak Off Phase when current is over threshold Set flag0 to high (VFM can go out of Idle Phase) Wait entry # 1 satisfied Boost Phase Load the boost phase current threshold in the current DAC Define wait table entry # 2: Jump to Peak Phase when current is over threshold Set flag0 to low (set the VFM in Idle Phase while the Injection Boost Phase is ongoing) Vboost MOSFET (HS2), Vbat MOSFET (HS1) and LS MOSFET (LSx) turn on Start Freewheeling Automatic mode Wait for wait table entry 1 or 2 to be satisfied Peak Off Phase Load in the counter 2 the length of the peak off phase LS MOSFET (LSx) turn on, Vboost MOSFET and Vbat MOSFET (HS2) turn off Wait entry # 2 satisfied tc1 end of count Wait entry # 4 satisfied tc3 end of count Hold On Phase Vbat MOSFET (HS2) and LS MOSFET (LSx) turn on, Vboost MOSFET turn off Wait for wait table entry 1, 2 or 3 to be satisfied Wait entry # 3 satisfied tc1 end of count Hold Off Phase Load in the counter 1 the length of the hold_ off phase LS MOSFET (LSx) turn on, Vboost MOSFET and Vbat MOSFET (HS2) turn off Wait entry # 2 satisfied tc2 end of count Wait entry # 2 satisfied Wait entry # 4 satisfied Hold Phase Load the total length of the hold phase in counter 2 Load the hold current threshold in the DAC Define wait table entry # 2: Jump to End Of Injection Phase when tc2 reaches end of count Define wait table entry # 3: Jump to Hold On Phase when tc1 reaches end of count Define wait table entry # 4: Jump to Hold Off Phase when current is over threshold Wait entry # 5 satisfied Bypass Phase Load in the counter 3 the length of the bypass phase Vboost MOSFET, Vbat MOSFET (HS2) and LS MOSFET (LSx) turn off Define wait table entry # 4: Jump to hold when tc3 reaches end of count Wait for wait table entry 4 or 5 to be satisfied End Of Injection Phase Vboost MOSFET, Vbat MOSFET (HS2) and LS MOSFET (LSx) turn off Define wait table entry # 2: Jump to FW_OFF when tc1 reaches end of count Wait here until wait 2 is finished to let current recirculate in FW low side Wait entry # 2 satisfied tc1 end of count FW OFF Turn OFF automatic Freewheeling (stfw manual) Jump back to idle state Figure 6. Algorithm Example for One Injector AN5187 Application Note Rev. 1.0 9/2015 12 Analog Integrated Circuit Device Data Freescale Semiconductor SOFTWARE REQUIREMENTS Refer to Injection Banks Management Source Code 4.2 DC-DC Resonant Mode Management In Resonant mode, off switching is triggered by the sense current rising above an upper current threshold and the on switching is triggered by the low-side VDS going below 2.5 V. This mode uses a current control loop within a voltage control loop. The voltage control loop is controlled by microcode, VBOOST high and low threshold are defined in the DRAM. To use this mode on the KITPT2000FRDM3C, the capacitance CRES needs to be populated, it is not the case by default. The code dedicated to the boost converter regulation loop is loaded into the Code RAM 3. This code is executed independently by the microcore Uc0Ch3. VBAT VBOOST VSENSEN5 Il_ls7 C_Res Iboost_cap VSENSEP5 Isense5 PT2000 VDS G_LS7 C_Boost D_LS7 VBOOST AGND Figure 7. Simplified DC-DC Converter Topology for Resonant Mode At boost startup, the current through the inductor oscillates between a high current threshold and the VDS low-side, this avoid switching loss during the turn OFF. Low-side VDS goes lower than 2.5 V as soon as there is no more current in the inductance, the goal of the CRES is to reduce the switching slew rates to detect when VDS across low-side mosfet goes below 2.5 V with the fast comparator. In case the VDS is not detected (this can be the case if VBOOST-VBAT > VBAT), a timeout is used to turn the low-side ON again. When this switch is on, the current grows through the sense resistor and the low-side switch. When the switch is open, the current decays through the diode and loads the output capacitor. It increases the voltage until the VBOOST voltage reaches the VBOOST_HIGH threshold. This phase uses the asynchronous mode and the current modulation is managed by an independent circuitry enabled by the microcore. AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor 13 Tboost_filer SOFTWARE REQUIREMENTS Vboost_high Vboost Vboost_low Vbat - Vdiode Vgs_ls7 Isense5_high Isense5 VDS_2.5V threshold VDS_LS7 t Startup Phase Figure 1. Resonant Mode Startup Sequence When the VBOOST_HIGH threshold is reached, the synchronous mode is enabled. In this case, the microcore takes the direct control of the low-side switch. The low-side switch is turned off until the boost voltage goes below the VBOOST_LOW threshold. Each time the VBOOST_HIGH threshold is reached, the VBOOST_LOW threshold is setup, and the synchronous mode is activated after a tBOOST_FILTER filter time required by the voltage comparator circuitry enablement. Each time the boost voltage falls below the VBOOST_LOW threshold the VBOOST_HIGH threshold is setup, and the asynchronous mode is activated after a tBOOST_FILTER filter time. AN5187 Application Note Rev. 1.0 9/2015 14 Analog Integrated Circuit Device Data Freescale Semiconductor Tboost_filter Tboost_filter SOFTWARE REQUIREMENTS Vboost_high Vboost Vboost_low VGS_LS7 Isense4_high Isense5 Il_LS7 Iboost_cap VDS_LS7 VDS_2.5V treshold t Async_VDS Phase Sync Phase Figure 2. DCDC Voltage and Current Diagram Table 22. Example of DC-DC Converter key parameters Parameter Name Description Value VBOOST_HIGH VBOOST voltage high threshold 65.31 V VBOOST_LOW VBOOST voltage low threshold 64.69 V ISENSE5_LOW Low current threshold (only use in case VDS 2.5 V threshold not reached) 0.07 A ISENSE5_HIGH High current threshold 3.95 A In the present case, most of the code branches (jumps) are managed according to the VBOOST voltage and the flag0 state by means of the wait table. The wait table rows are affected as shown in Table 23. and are changed according to the actuation phase. Table 23. Example of Wait Table Definition for the DCDC. Phase Row 1 Async_Vds Phase (dcdc_on) Sync Phase (dcdc_off) If flag0 is low, then jump to Idle phase If flag0 is low, then jump to Idle phase If VBOOST < VBOOST_LOW, then jump to Async_Vds Phase Idle Phase - Row 2 - Row3 If VBOOST > VBOOST_HIGH, then jump to Sync phase - Row 4 - - - Row 5 - - - - To avoid regulation disturbances, the boost voltage regulation is stopped by the means of the internal flag 0 when an injection phase starts. AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor 15 SOFTWARE REQUIREMENTS 4.2.1 DC-DC Management Registers Setup The PT2000 registers are setup according their default states, unless defined by the following. 4.2.1.1 IO Configuration Registers 4.2.1.1.1 Output Driver Access The Uc0Ch3 must have access to the pre-driver LS7 only. Table 1. Out_acc_uc0_ch3 Register (164h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Acc_u Reserv c0_ch3 c0_ch3 c0_ch3 c0_ch3 c0_ch3 c0_ch3 c0_ch3 Name c0_ch3 c0_ch3 c0_ch3 c0_ch3 c0_ch3 c0_ch3 c0_ch3 c0_ch3 ed _ls8 _ls7 _ls6 _ls5 _ls4 _ls3 _ls2 _ls1 _hs7 _hs6 _hs5 _hs4 _hs3 _hs2 _hs1 Value 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Resonant mode (“async_vds) is required to set the following register (182h), to set the VDS LS7 monitoring to use the high speed comparator to detect when VDS is lower than 2.5 V, as fast as possible. Also important is to set the bit vds7_en and set the filter time properly to start the DCDC, even if the VDS_threshold is not reached. This a safety mechanism. Table 2. Vds7_dcdc_config (182h) Bit 15 14 13 12 11 Name dcdcx mode Reserved Value 00 000 10 9 8 ls7_vds_hig Cur_dcdc hspeed_en 7_fbk_sel 1 0 7 6 5 4 3 2 vds7_ to_en vds7_dcdc_timeout 1 000000011 1 0 LS7 VDS threshold needs to be set to 2.5 V to make the DCDC resonant mode efficient enough. Table 3. Vds_threshold_ls_Part 2 (170h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Name Vds thr Ls8 Vds thr Ls7 Vds thr Ls6 Vds thr Ls5 Reset 0000 0101 (2.5V threshold) 0000 0000 4.2.1.1.2 0 Current Sense Access The Uc0Ch3 must have access to the current sense feedback # 5L (for the timeout detection, if the 2.5 V VDS threshold is not reached) and 5H. Table 2. Cur_block_access_3 Register (168h) Bit 15 14 13 12 acc_u acc_u acc_u acc_u c1_ch c1_ch c1_ch c1_ch 3_curr Name 3_curr 3_curr 3_curr 6H_6N 5H_5N 6L 5L eg eg Value 0 0 0 0 11 acc_u c1_ch 3_curr 4 0 10 9 8 7 6 5 4 3 2 1 0 acc_u acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc acc_uc c1_ch 0_ch3_ 0_ch3_ 1_ch3_ 1_ch3_ 0_ch3_ 0_ch3_ 0_ch3_ 0_ch3_ 0_ch3_ 0_ch3_ 3_curr curr6H curr5H curr2 curr1 curr6L curr5L curr4 curr3 curr2 curr1 3 _6Neg _5Neg 0 0 0 0 0 1 1 0 0 0 0 AN5187 Application Note Rev. 1.0 9/2015 16 Analog Integrated Circuit Device Data Freescale Semiconductor SOFTWARE REQUIREMENTS 4.2.1.1.3 Boost DAC Access The Uc0Ch3 must have access to the Boost DAC to set the right threshold Vboost_high and Vboost_low. Table 4. Boost_dac_access (180h) Bit 15 14 13 12 11 10 Name Reserved Value 0000000000 4.2.1.1.4 9 8 7 6 5 4 3 2 1 0 uc1_ch uc0_ch uc1_ch uc0_ch uc1_ch uc0_ch 3 acc 3 acc 2 acc 2 acc 1 acc 1 acc 0 1 0 0 0 0 Boost Filter time The tBOOST_FILTER time is defined in the Boost_filter register (181h). This filter time and type can be adjusted to improve the VBOOST voltage stability. Table 5. Boost_filter (181h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 Name Reserved filter_ty pe Boost_fbk_filter Value 000 0 00000000111 4.2.1.2 3 2 1 0 Diagnosis Configuration Registers The low-side driver 7 must be directly controlled by the Uc0Ch3 microcore. Consequently, the output_routing fields of its output configuration register must be set to the value 31. Table 6. LS7_output_config (1D4h) Bit 15 Name LSx_ov r Reserved output_routing inv Reset 0 000000000 11111 0 4.2.1.3 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Channel 3 Configuration Registers Same as for Channel 1-2 entry points of each microcore must be selected for Channel 3. 4.2.1.3.1 Entry Point Registers Entry point registers are defining where each microcore starts in each channel. With the new PT2000 IDE, it is possible to specify a label as a starting point and those registers are set automatically. For example, “init0” is the starting point of Uc0Ch3. If this feature is not used, the following register has to be set manually. In the code example entry point of Uc0Ch3 is 0 as the first line executed, is the first Code RAM line of the channel 1. Table 3. Uc0_entry_point Registers (10Ah) of Channel 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 Name Reserved entry_point_address Reset 000000 0000000000 3 2 1 0 Uc1CH3 is not used in our example, but to avoid an issue if the dual sequencer is selected, the code entry point of Uc1Ch3 is set and a dummy code of at least 3 lines is added to the example. This is unusable if the bit dual microcore (140h) is not set to ‘1’. AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor 17 SOFTWARE REQUIREMENTS Table 4. Uc1_entry_point Registers (10Bh) of Channel 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 Name Reserved entry_point_address Reset 000000 10001 4.2.2 3 2 1 0 DC-DC Management Algorithm Initialization Phase Current sense operational amplifier gain setting Set LS7 in shortcut 2 to be controlled by async_vds mode Load the min current threshold in DAC 5L Load the max current threshold in DAC 5H Boost Phase Define wait table entry # 1: Jump to Idle Phase when flag0 is low (boost injection phase ongoing) Define wait table entry # 2: Jump to Asynchrous Phase when Vboost voltage is below Vboost_min Define wait table entry # 3: Jump to Synchrous Phase when Vboost voltage is above Vboost_max Wait entry # 1 satisfied Asynchronous VDS Phase Load the Vboost_max threshold in vboost_dac register Enable the Asynchronous VDS mode Wait for wait table entry 1 or 2 to be satisfied Wait entry # 2 satisfied Synchronous Phase Load the Vboost_min threshold in vboost_dac register Enable the Synchronous mode (LS7 driver off) Wait for wait table entry 1 or 3 to be satisfied Wait entry # 3 satisfied Idle Phase Enable the Synchronous mode (LS7 driver off) Jump to previous line while flag0 is low Unconditional jump to Asynchrous VDS Phase Figure 3. Algorithm Example for DCDC Refer to DC-DC Management Source Code AN5187 Application Note Rev. 1.0 9/2015 18 Analog Integrated Circuit Device Data Freescale Semiconductor PCB LAYOUT RECOMMENDATIONS 5 5.1 PCB Layout Recommendations Ground Connections The PT2000 exposed pad must be connected to the PCB ground. All the grounds (AGND, DGND, and PGND) must be ‘in star' or considering a unique ground layer, such as to minimize the introduction of offset and noise mainly in the signal return lines. 5.2 Sense Resistors Connection The sense resistor’s layout must be considered with special care, to sense the voltage as close as possible to the resistor terminations. Balanced series resistance, induced by the layout, between the sense resistor positive termination to the VSENSEPx and the sense resistor negative termination to the VSENSENx pin is recommended. The balance can be achieved by implementing similar line lengths. Figure 4. Example of Force and Sense Connection Layout It is highly recommended to place the sense resistor as close as possible to its corresponding low-side MOSFET transistor. AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor 19 APPLICATION SOURCE CODE 6 Application Source Code Download the full project, including microcode, plus register and DRAM settings, at this location http://www.freescale.com/files/analog/doc/app_note/AN5187SW.zip 6.1 Injection Banks Management Source Code ********************************************************************************* * Copyright (c) Freescale 2014 * * File Name: MC33PT2000_VFM_65V.dfi * * Current Revision: 1.0 * * Purpose: MC33PT2000 example - 1 Bank * * Description: MC33PT2000 Channel 1 controls INJ1 and INJ2 * * * * REV AUTHOR DATE DESCRIPTION OF CHANGE * * --- --------------------------------* * 1.0 b16868 2015/03/25 - initial coding * * * ********************************************************************************* ********************************************************************************* * Freescale reserves the right to make changes without further notice to any * * product herein to improve reliability, function, or design. Freescale does * * not assume any liability arising out of the application or use of any * * product, circuit, or software described herein; neither does it convey any * * license under its patent rights nor the rights of others. Freescale products * * are not designed, intended, or authorized for use as components in systems * * intended for surgical implant into the body, or other applications intended * * to support life, or for any other application in which the failure of the * * Freescale product could create a situation where personal injury or death may* * occur. Should Buyer purchase or use Freescale products for any such intended * * or unauthorized application, Buyer shall indemnify and hold Freescale and * * its officers, employees, subsidiaries, affiliates, and distributors harmless * * against all claims costs, damages, and expenses, and reasonable attorney fees* * arising out of, directly or indirectly, any claim of personal injury or * * death associated with such unintended or unauthorized use, even if such * * claim alleges that Freescale was negligent regarding the design or* * manufacture of the part. Freescale and the Freescale logo are registered * * trademarks of Freescale Ltd. * ********************************************************************************* * This microcore uc0 will control BANK1 * High SIde Vbat = hs1 * High SIde Vboost = hs2 * Low side Freewheeling = ls1 * Low side = ls2 * current sense = cur1 #include "dram1.def"; ********************************************************************************************************* * INIT PHASE ********************************************************************************************************* * ### Initialization phase ### init0: stgn gain8.68 sssc; * Set the gain of the opamp of the current measure block 1 ldjr1 eoinj0; * Load the eoinj line label Code RAM address into the register jr1 ldjr2 idle0; * Load the idle line label Code RAM address into the register jr2 cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase sto ls1 off; ********************************************************************************************************* * IDLE PHASE * ********************************************************************************************************* * ### Idle phase- the uPC loops here until start signal is present ### idle0: stoc on sssc; * Turn ON offset compensation AN5187 Application Note Rev. 1.0 9/2015 20 Analog Integrated Circuit Device Data Freescale Semiconductor APPLICATION SOURCE CODE cwer CheckStart start row2; * Define entry table for high start pin WaitLoop: wait row2; * uPC is stuck here for almost the whole idle time CheckStart: joslr inj1_start start1; * Jump to inj1 if start 1 is high jmpr WaitLoop; ********************************************************************************************************* * SHORTCUT DEFINITION * ********************************************************************************************************* * ### Shortcuts definition per the injector to be actuated ### inj1_start: dfsct hs1 hs2 ls2; * Set the 3 shortcuts: VBAT, VBOOST, LS2 stoc off sssc; * Disable Offset Compensation ********************************************************************************************************* * BOOST PHASE * ********************************************************************************************************* * ### Launch phase enable boost ### boost0: load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC cwer peak0 cur1 row2; * Jump to peak phase when current is over threshold stf low b0; * set flag0 low to force the DC-DC converter in idle mode stos on on on; * Turn VBAT off, BOOST on, LS on stfw auto; * LS1 is used as the freewheeling of hs1 stf high b1; * Test purpose wait row12; * Wait for one of the previously defined conditions ********************************************************************************************************* * PEAK PHASE * ********************************************************************************************************* * ### Peak phase continue on Vbat ### peak0: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1 load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC cwer bypass0 tc1 row2; * Jump to bypass phase when tc1 reaches end of count cwer peak_on0 tc2 row3; * Jump to peak_on when tc2 reaches end of count cwer peak_off0 cur1 row4; * Jump to peak_off when current is over threshold stf high b0; * set flag0 high to release the DC-DC converter idle mode peak_on0: stos on off on; wait row124; * Turn VBAT on, BOOST off, LS on * Wait for one of the previously defined conditions peak_off0: ldcd rst ofs keep keep Tpeak_off c2; stos off off on; wait row123; * Load in the counter 2 the length of the peak_off phase * Turn VBAT off, BOOST off, LS on ********************************************************************************************************* * BYPASS PHASE * ********************************************************************************************************* * ### Bypass phase ### bypass0: ldcd rst ofs keep keep Tbypass c3; stos off off off; cwer hold0 tc3 row4; wait row14; * * * * Load Turn Jump Wait in the counter 3 the length of the off_phase phase VBAT off, BOOST off, LS off to hold when tc3 reaches end of count for one of the previously defined conditions ********************************************************************************************************* * HOLD PHASE * ********************************************************************************************************* * ### Hold phase on Vbat ### hold0: ldcd rst _ofs keep keep Thold_tot c1; load Ihold dac_sssc _ofs; cwer eoinj0 tc1 row2; cwer hold_on0 tc2 row3; cwer hold_off0 cur1 row4; * * * * * Load Load Jump Jump Jump the length of the total hold phase in counter 2 the hold current threshold in the DAC to eoinj phase when tc1 reaches end of count to hold_on when tc2 reaches end of count to hold_off when current is over threshold AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor 21 APPLICATION SOURCE CODE hold_off0: ldcd rst _ofs keep keep Thold_off c2; stos off off on; wait row123; * Load the length of the hold_off phase in counter 1 * Turn VBAT off, BOOST off, LS on hold_on0: stos on off on; wait row124; * Turn VBAT on, BOOST off, LS on * Wait for one of the previously defined conditions ********************************************************************************************************* * END OF INJECTION PHASE * ********************************************************************************************************* * ### End of injection phase ### eoinj0: stos off off off; * Turn VBAT off, BOOST off, LS off stf high b0; * set flag0 to high to release the DC-DC converter idle mode ldcd rst _ofs keep keep FWtimeOFF c1; * Load the length of the time when FW low side will stay ON cwer FW_OFF tc1 row2; * Jump to eoinj phase when tc1 reaches end of count wait row2; * Wait until FW phase is complete FW_OFF: stfw manual; * Turn OFF FW low side, go back to manual mode jmpf jr2; * Jump back to idle phase * ### End of Channel 1 - uCore0 code ### *############################################################################################################### ################ * This microcore uc1 will control BANK2 * High SIde Vbat = hs3 * High SIde Vboost = hs4 * Low side Freewheeling = ls3 * Low side = ls4 * current sense = cur2 *############################################################################################################### ################ ********************************************************************************************************* * INIT PHASE ********************************************************************************************************* * ### Initialization phase ### init1: stgn gain8.68 sssc; * Set the gain of the opamp of the current measure block 1 ldjr1 eoinj1; * Load the eoinj line label Code RAM address into the register jr1 ldjr2 idle1; * Load the idle line label Code RAM address into the register jr2 cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase sto ls3 off; ********************************************************************************************************* * IDLE PHASE * ********************************************************************************************************* * ### Idle phase- the uPC loops here until start signal is present ### idle1: stoc on sssc; * Turn ON offset compensation cwer CheckStart1 start row2; * Define entry table for high start pin WaitLoop1: wait row2; * uPC is stuck here for almost the whole idle time CheckStart1: joslr inj2_start start2; * Jump to inj2 if start 2 is high jmpr WaitLoop1; ********************************************************************************************************* * SHORTCUT DEFINITION * ********************************************************************************************************* * ### Shortcuts definition per the injector to be actuated ### inj2_start: dfsct hs3 hs4 ls4; * Set the 3 shortcuts: VBAT, VBOOST, LS4 stoc off sssc; * Stop offset compensation AN5187 Application Note Rev. 1.0 9/2015 22 Analog Integrated Circuit Device Data Freescale Semiconductor APPLICATION SOURCE CODE ********************************************************************************************************* * BOOST PHASE * ********************************************************************************************************* * ### Launch phase enable boost ### boost1: load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC cwer peak1 cur2 row2; * Jump to peak phase when current is over threshold stf low b0; * set flag0 low to force the DC-DC converter in idle mode stos on on on; * Turn VBAT off, BOOST on, LS on stfw auto; * LS1 is used as the freewheeling of hs3 stf high b2; wait row12; * Wait for one of the previously defined conditions ********************************************************************************************************* * PEAK PHASE * ********************************************************************************************************* * ### Peak phase continue on Vbat ### peak1: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1 load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC cwer bypass1 tc1 row2; * Jump to bypass phase when tc1 reaches end of count cwer peak_on1 tc2 row3; * Jump to peak_on when tc2 reaches end of count cwer peak_off1 cur2 row4; * Jump to peak_off when current is over threshold stf high b0; * set flag0 high to release the DC-DC converter idle mode peak_off1: ldcd rst ofs keep keep Tpeak_off c2; stos off off on; wait row123; peak_on1: stos on on on; wait row124; * Load in the counter 2 the length of the peak_off phase * Turn VBAT off, BOOST off, LS on * Turn VBAT on, BOOST off, LS on * Wait for one of the previously defined conditions ********************************************************************************************************* * BYPASS PHASE * ********************************************************************************************************* * ### Bypass phase ### bypass1: ldcd rst ofs keep keep Tbypass c3; * Load in the counter 3 the length of the off_phase phase stos off off off; * Turn VBAT off, BOOST off, LS off cwer hold1 tc3 row4; * Jump to hold when tc3 reaches end of count wait row14; * Wait for one of the previously defined conditions ********************************************************************************************************* * HOLD PHASE * ********************************************************************************************************* * ### Hold phase on Vbat ### hold1: ldcd rst _ofs keep keep Thold_tot c1; load Ihold dac_sssc _ofs; cwer eoinj1 tc1 row2; cwer hold_on1 tc2 row3; cwer hold_off1 cur2 row4; * * * * * Load Load Jump Jump Jump the length of the total hold phase in counter 2 the hold current threshold in the DAC to eoinj phase when tc1 reaches end of count to hold_on when tc2 reaches end of count to hold_off when current is over threshold hold_off1: ldcd rst _ofs keep keep Thold_off c2; stos off off on; wait row123; * Load the length of the hold_off phase in counter 1 * Turn VBAT off, BOOST off, LS on hold_on1: stos on off on; wait row124; * Turn VBAT on, BOOST off, LS on * Wait for one of the previously defined conditions ********************************************************************************************************* * END OF INJECTION PHASE * ********************************************************************************************************* AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor 23 APPLICATION SOURCE CODE * ### End of injection phase ### eoinj1: stos off off off; stf high b0; ldcd rst _ofs keep keep FWtimeOFF c1; cwer FW_OFF1 tc1 row2; wait row2; FW_OFF1: stfw manual; jmpf jr2; * ### End of Channel 1 - uCore1 code ### * Turn VBAT off, BOOST off, LS off * set flag0 to high to release the DC-DC converter idle mode * Load the length of the time when FW low side will stay ON * Jump to eoinj phase when tc1 reaches end of count * Wait until FW phase is complete * Turn OFF FW low side, go back to manual mode * Jump back to idle phase AN5187 Application Note Rev. 1.0 9/2015 24 Analog Integrated Circuit Device Data Freescale Semiconductor APPLICATION SOURCE CODE 6.2 DC-DC Management Source Code *#### DCDC mode used in this case is resonant ####* *#### Some changes on the hardware needs to be done to go to resonant mode or freewheeling ####* #include "dram3.def"; * ### Initialization phase ### init0: sl56dac dac5; * DAC5 is used for DCDC stgn gain19.25 sssc; * Set the gain of the opamp of the current measure block 56 dfsct undef ls7 undef; * NEW on the PT2000 only shortcut 2 is sensitve to async_vds instruction stos keep off keep; load Iboost_L dac_sssc _ofs; * Load Isense5L just used for the timeout detection in case 2.5V VDS not reached load Iboost_H dac56h56n _ofs; * Load Isense56_high current threshold in DAC 56H stdm null; * Set the boost voltage DAC access mode cwer dcdc_idle _f0 row1; * Wait table entry for Vboost under Vboost_low threshold condition cwer dcdc_on _vb row2; * Wait table entry for Vboost under Vboost_low threshold condition cwer dcdc_off vb row3; * Wait table entry for Vboost over Vboost_high threshold condition * ### Asynchronous phase ### dcdc_on: load Vboost_H dac56h56n _ofs; * Load the upper Vboost threshold in vboost_dac register stdcctl async_vds; * Enable asynchronous mode wait row13; * Wait for one of the previously defined conditions * ### Synchronous phase ### dcdc_off: load Vboost_L dac56h56n _ofs; * Load the upper Vboost threshold in vboost_dac register stdcctl sync; * Enable synchronous mode wait row12; * Wait for one of the previously defined conditions * ### Idle phase ### dcdc_idle: stdcctl sync; * Enable synchronous mode stos keep off keep; jocr dcdc_idle _f0; * jump to previous line while flag 0 is low jmpr dcdc_on; * force the DC-DC converter on when flag 0 goes high * ### End of Channel 3 - uCore0 code ### AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor 25 REFERENCES 7 References Following are URLs where you can obtain information on Freescale products and application solutions: Document Number and Description URL PT2000 Data Sheet http://www.freescale.com/files/analog/doc/data_sheet/MC33PT2000.pdf KITPT2000FRDM6C User Guide http://cache.freescale.com/files/analog/doc/user_guide/KTPT2000FRDM6CUG.pdf PT2000SWUG Programming Guide http://cache.freescale.com/files/analog/doc/user_guide/PT2000SWUG.pdf PT2000IDEUG Developer Studio http://cache.freescale.com/files/analog/doc/user_guide/PT2000-IDEUG.pdf Freescale.com Support Pages URL Freescale.com http://www.freescale.com Product Summary Page http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=PT2000 Analog Home Page http://www.freescale.com/analog AN5187 Application Note Rev. 1.0 9/2015 26 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY 8 Revision History Revision Date 1.0 9/2015 Description • Initial release AN5187 Application Note Rev. 1.0 9/2015 Analog Integrated Circuit Device Data Freescale Semiconductor 27 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. Home Page: freescale.com There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no on the information in this document. warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. 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