Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT163652 16-Bit Registered Transceiver SCCS052 - March 1997 - Revised March 2000 Features Functional Description • Low power, pin-compatible replacement for LCX and LPT families • 5V tolerant inputs and outputs • 24 mA balanced drive outputs • Power-off disable outputs permits live insertion • Edge-rate control circuitry for reduced noise • FCT-C speed at 4.6 ns • Latch-up performance exceeds JEDEC standard no. 17 • ESD > 2000V per MIL-STD-883D, Method 3015 • Typical output skew < 250 ps • Industrial temperature range of –40˚C to +85˚C • TSSOP (19.6-mil pitch) or SSOP (25-mil pitch) • Typical Volp (ground bounce) performance exceeds Mil Std 883D • VCC = 2.7V to 3.6V The CY74FCT163652 is a 16-bit, high-speed, low-power, registered transceiver that is organized as two independent 8-bit bus transceivers with three-state D-type registers and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. OEAB and OEBA control pins are provided to control the transceiver functions. SAB and SBA control pins are provided to select either real-time or stored data transfer. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CLKAB or CLKBA), regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. The CY74FCT163652 has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The inputs and outputs were designed to be capable of being driven by 5.0V buses, allowing them to be used in mixed voltage systems as translators. The outputs are also designed with a power-off disable feature enabling them to be used in applications requiring live insertion. Logic Block Diagrams 1OEAB 2OEAB 1OEBA 2OEBA 1CLKBA 2CLKBA 1SBA 2SBA 1CLKAB 2CLKAB 1SAB 2SAB B REG B REG D D C C 2A1 1A1 A REG A REG D D 1B1 C TO 7 OTHER CHANNELS 2 B1 C TO 7 OTHER CHANNELS Copyright © 2000, Texas Instruments Incorporated CY74FCT163652 Pin Configuration SSOP/TSSOP Top View 1OEAB 1 56 1CLKAB 2 55 1OEBA 1CLKBA 1SAB 3 54 1SBA GND 4 53 1A 1 5 52 1B1 GND 1A 2 6 51 1B2 VCC 7 50 VCC 1A 3 8 49 1B3 1A 4 9 48 1B4 1A 5 10 47 1B5 GND 11 46 GND 1A 6 12 45 1B6 1A 7 13 44 1B7 1A 8 14 43 1B8 2A 1 15 42 2B1 2A 2 16 41 2B2 2A3 17 40 2B3 GND 18 39 GND 2A 4 19 38 2B4 2A 5 20 37 2B5 2A 6 21 36 2B6 V CC 22 35 VCC 2A 7 23 34 2B7 2A 8 2B8 GND 33 24 FCT16652–1 32 25 2SAB 26 31 2SBA 2CLKAB 27 30 2CLKBA 2OEAB 28 29 2OEBA GND Pin Description Name Description A Data Register A Inputs, Data Register B Outputs B Data Register B Inputs, Data Register A Outputs CLKAB, CLKBA Clock Pulse Inputs SAB, SBA Output Data Source Select Inputs OEAB, OEBA Output Enable Inputs 2 CY74FCT163652 Function Table[1] Data I/O[2] Inputs OEAB OEBA CLKAB CLKBA SAB SBA A B L L H H H or L H or L X X X X Input Input Operation or Function X H H H H or L X X[3] X X Input Input Unspecified[2] Output Store A, Hold B Store A in Both Registers L L X L H or L X X X X[3] Unspecified[2] Input Input Hold A, Store B Store B in both Registers L L L L X X X H or L X X L H Output Input Real Time B Data to A Bus Stored B Data to A Bus H H H H X H or L X X L H X X Input Output Real Time A Data to B Bus Stored A Data to B Bus H L H or L H or L H H Output Output Stored A Data to B Bus and Stored B Data to A Bus Isolation Store A and B Data Notes: 1. 2. 3. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care, = LOW-to-HIGH Transition The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Select control=L; clocks can occur simultaneously. Select control=H; clocks must be staggered to load both registers. 3 CY74FCT163652 BUS A BUS B OEAB L OEBA L CLKAB X CLKBA X SAB X BUS A SBA L OEAB H BUS B OEBA L Real-Time Transfer Bus B to BusA OEBA H X H CLKAB CLKBA X X CLKBA X SAB L SBA X Real-Time Transfer BusA to Bus B BUS A OEAB X L L CLKAB X SAB X X X BUS B BUS A SBA X X X OEAB H BUS A OEBA L Storage from A and/or B CLKAB H or L CLKBA H or L SAB H SBA H Transfer Stored Data to A and/or B Maximum Ratings[4] (Above which the useful life may be impaired. For user guidelines, not tested.) DC Output Current (Maximum Sink Current/Pin) ...........................−60 to +120 mA Storage Temperature .............................. −55°C to +125°C Power Dissipation .......................................................... 1.0W Ambient Temperature with Power Applied .......................................... −55°C to +125°C Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Supply Voltage Range ..................................... 0.5V to +4.6V Operating Range DC Input Voltage .................................................−0.5V to +7.0V DC Output Voltage ..............................................−0.5V to +7.0V Range Industrial Ambient Temperature VCC –40°C to +85°C 2.7V to 3.6V Note: 4. Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 4 CY74FCT163652 Electrical Characteristics Over the Operating Range VCC=2.7V to 3.6V Parameter Description VIH Input HIGH Voltage VIL Input LOW Voltage Test Condition All Inputs Min. Typ.[5] 2.0 [6] VH Input Hysteresis VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA IIH Input HIGH Current IIL Input LOW Current IOZH Max. Unit 5.5 V 0.8 V 100 −1.2 V VCC=Max., VI=5.5V ±1 µA VCC=Max., VI=GND ±1 µA High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=5.5V ±1 µA IOZL High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=GND ±1 µA IODL Output LOW Dynamic Current[7] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V 45 180 mA IODH Output HIGH Dynamic Current[7] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V –45 –180 mA VOH Output HIGH Voltage VCC=Min., IOH= –0.1 mA VOL Output LOW Voltage −0.7 mV VCC–0.2 VCC=3.0V, IOH= –8 mA 3.0 VCC=3.0V, IOH= –24 mA 2.0 3.0 VCC=Min., IOL= 0.1mA 0.2 VCC=Min., IOL= 24 mA IOS IOFF Short Circuit Power-Off Current[7] Disable[7] V 2.4[8] VCC=Max., VOUT=GND –60 V 0.3 0.5 –135 –240 mA ±100 µA Typ. Max. Unit VCC=0V, VOUT≤4.5V Capacitance[6] (TA = +25˚C, f = 1.0 MHz) Parameter Description Test Conditions CIN Input Capacitance VIN = 0V 4.5 6.0 pF COUT Output Capacitance VOUT = 0V 5.5 8.0 pF Notes: 5. Typical values are at VCC=3.3V, +25°C ambient. 6. This parameter is specified but not tested. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametrics tests. In any sequence of parameter tests, IOS tests should be performed last. 8. VOH=VCC–0.6V at rated current. 5 CY74FCT163652 Power Supply Characteristics Parameter Description Typ.[5] Max. Unit VIN<0.2V VIN>VCC−0.2V 0.1 10 µA Test Conditions ICC Quiescent Power Supply Current VCC=Max. ∆ICC Quiescent Power Supply Current VCC = Max. TTL Inputs HIGH VIN=VCC–0.6V[9] 2.0 30 µA ICCD Dynamic Power Supply Current[10] VCC=Max., Outputs Open OEAB=OEAB=GND One Input Toggling 50% Duty Cycle VIN=VCC or VIN=GND 50 75 µA/MHz IC Total Power Supply Current[11] VCC=Max., Outputs Open fo=10 MHz (CLKBA) 50% Duty Cycle OEAB=OEBA=GND One-Bit Toggling, f1=5 MHz 50% Duty Cycle VIN=VCC or VIN=GND 0.5 0.8 mA VIN=VCC–0.6V or VIN=GND 0.5 0.8 mA VCC=Max., Outputs Open fo=10 MHz (CLKBA) 50% Duty Cycle OEAB=OEBA=GND Sixteen Bits Toggling f1=2.5 MHz, 50% Duty Cycle VIN=VCC or VIN=GND 2.5 3.8[12] mA VIN=VCC–0.6V or VIN=GND 2.6 4.1[12] mA Notes: 9. Per TTL driven input; all other inputs at VCC or GND. 10. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 11. IC IC = ICC+∆ICCDHNT+ICCD(f0NC /2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input = Duty Cycle for TTL inputs HIGH DH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero = Number of clock inputs changing at f1 NC f1 = Input signal frequency = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 12. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 6 CY74FCT163652 Switching Characteristics Over the Operating Range VCC = 3.0V to 3.6V[13,14] CY74FCT163652A Parameter Description CY74FCT163652C Min. Max. Min. Max. Unit Fig. No.[15] tPLH tPHL Propagation Delay Bus to Bus 1.5 6.3 1.5 5.4 ns 1, 3 tPZH tPHL Output Enable Time OEAB or OEBA to Bus 1.5 9.8 1.5 7.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time OEAB or OEBA to Bus 1.5 6.3 1.5 6.3 ns 1, 7, 8 tPLH tPHL Propagation Delay Clock to Bus 1.5 6.3 1.5 5.7 ns 1, 5 tPLH tPHL Propagation Delay SBA or SAB to Bus 1.5 7.7 1.5 6.2 ns 1, 5 tSU Set-Up time HIGH or LOW Bus to Clock 2.0 — 2.0 — ns 4 tH Hold Time HIGH or LOW Bus to Clock 1.5 — 1.5 — ns 4 tW Clock Pulse Width HIGH or LOW 5.0 — 5.0 — ns 5 tSK(O) Output Skew[16] — 0.5 — 0.5 ns Ordering Information CY74FCT163652 Speed (ns) 5.4 6.3 Ordering Code Package Name Package Type CY74FCT163652CPACT Z56 56-Lead (240-Mil) TSSOP CY74FCT163652CPVC/PVCT O56 56-Lead (300-Mil) SSOP CY74FCT163652APACT Z56 56-Lead (240-Mil) TSSOP Notes: 13. Minimum limits are specified, but not tested, on propagation delays. 14. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%. 15. See “Parameter Measurement Information” in the General Information section. 16. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design. 7 Operating Range Industrial Industrial CY74FCT163652 Package Diagrams 56-Lead Shrunk Small Outline Package O56 56-Lead Thin Shrunk Small Outline Package Z56 8 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) CY74FCT163652APAC OBSOLETE TSSOP DGG 56 TBD Call TI Call TI CY74FCT163652APACT OBSOLETE TSSOP DGG 56 TBD Call TI Call TI CY74FCT163652CPAC OBSOLETE TSSOP DGG 56 TBD Call TI Call TI CY74FCT163652CPACT OBSOLETE TSSOP DGG 56 TBD Call TI Call TI CY74FCT163652CPVC OBSOLETE SSOP DL 56 TBD Call TI Call TI CY74FCT163652CPVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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