8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller ADP3198 FEATURES FUNCTIONAL BLOCK DIAGRAM VCC RT RAMPADJ 31 12 SHUNT REGULATOR 13 OSCILLATOR UVLO SHUTDOWN + GND 18 CMP – 850mV EN + 1 DAC + 150mV PWRGD + + DAC – 500mV – + CMP 19 OD SET EN RESET 30 PWM1 RESET 29 PWM2 – + CMP – + CMP – DELAY 2 TTSENSE 10 VRHOT 9 VRFAN 8 – CSREF – CURRENT BALANCING CIRCUIT 28 PWM3 RESET 2/3/4-PHASE DRIVER LOGIC 27 PWM4 RESET CROWBAR CURRENT LIMIT THERMAL THROTTLING CONTROL APPLICATIONS ILIMIT 11 DELAY 7 COMP 5 FBRTN 3 PRECISION REFERENCE – This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switching stages. + – The ADP3198 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.5 V and 1.6 V. + – SW1 24 SW2 23 SW3 22 SW4 17 CSCOMP 15 CSREF 16 CSSUM 21 IMON 4 FB 14 LLSET 6 SS IREF 20 GENERAL DESCRIPTION 1 CURRENT MEASUREMENT AND LIMIT + Desktop PC power supplies for next generation Intel® processors VRM modules 25 BOOT VOLTAGE AND SOFT START CONTROL VID DAC VIDSEL 40 ADP3198 32 33 34 35 36 37 38 39 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 06094-001 Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase ±11 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Enhanced PWM flex mode for excellent load transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly VID code changes Digitally programmable 0.5 V to 1.6 V output supports both VR10.x and VR11 specifications Programmable short-circuit protection with programmable latch-off delay Figure 1. The ADP3198 has a built-in shunt regulator that allows the part to be connected to the 12 V system supply through a series resistor. The ADP3198 is specified over the extended commercial temperature range of 0°C to 85°C and is available in a 40-lead LFCSP. The ADP3198 also includes programmable no load offset and slope functions to adjust the output voltage as a function of the load current, optimally positioning it for a system transient. The ADP3198 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed powergood output that accommodates on-the-fly output voltage changes requested by the CPU. 1 Protected by U.S. Patent Number 6,683,441; other patents pending. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADP3198 TABLE OF CONTENTS Features .............................................................................................. 1 Power-Good Monitoring........................................................... 14 Applications....................................................................................... 1 Output Crowbar ......................................................................... 14 General Description ......................................................................... 1 Output Enable and UVLO ........................................................ 14 Functional Block Diagram .............................................................. 1 Thermal Monitoring .................................................................. 14 Revision History ............................................................................... 2 Application Information................................................................ 20 Specifications..................................................................................... 3 Setting the Clock Frequency..................................................... 20 Test Circuits....................................................................................... 5 Soft Start Delay Time................................................................. 20 Absolute Maximum Ratings............................................................ 6 Current-Limit Latch-Off Delay Times .................................... 20 ESD Caution.................................................................................. 6 Inductor Selection ...................................................................... 21 Pin Configuration and Function Descriptions............................. 7 Current Sense Amplifier............................................................ 22 Typical Performance Characteristics ............................................. 9 Inductor DCR Temperature Correction ................................. 22 Theory of Operation ...................................................................... 10 Output Offset .............................................................................. 24 Start-Up Sequence...................................................................... 10 COUT Selection ............................................................................. 24 Phase Detection Sequence......................................................... 10 Power MOSFETs......................................................................... 25 Master Clock Frequency............................................................ 11 Ramp Resistor Selection............................................................ 26 Output Voltage Differential Sensing ........................................ 11 COMP Pin Ramp ....................................................................... 26 Output Current Sensing ............................................................ 11 Current-Limit Setpoint.............................................................. 26 Active Impedance Control Mode............................................. 11 Feedback Loop Compensation Design.................................... 27 Current Control Mode and Thermal Balance ........................ 11 CIN Selection and Input Current di/dt Reduction.................. 28 Voltage Control Mode................................................................ 12 Thermal Monitor Design .......................................................... 28 Current Reference ...................................................................... 12 Shunt Resistor Design................................................................ 29 Enhanced PWM Mode .............................................................. 12 Tuning the ADP3198 ................................................................. 29 Delay Timer................................................................................. 12 Layout and Component Placement ......................................... 31 Soft Start ...................................................................................... 12 Outline Dimensions ....................................................................... 32 Current-Limit, Short-Circuit, and Latch-Off Protection...... 13 Ordering Guide .......................................................................... 32 Dynamic VID.............................................................................. 13 REVISION HISTORY 8/06—Rev. 0 to Rev. A. Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 6 Changes to Start-Up Sequence Section ....................................... 10 Changes to Phase Detection Sequence Section .......................... 10 6/06—Revision 0: Initial Version Rev. A | Page 2 of 32 ADP3198 SPECIFICATIONS VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted. 1 Table 1. Parameter REFERENCE CURRENT Reference Bias Voltage Reference Bias Current ERROR AMPLIFIER Output Voltage Range 2 Accuracy Symbol Conditions Min Typ Max Unit VIREF IIREF RIREF = 100 kΩ 14.25 1.5 15 15.75 V μA 4.4 +11 V mV 1.111 −82 +1 16.5 200 V mV LSB μA μA μA MHz V/μs mV nA ms VCOMP VFB VFB(BOOT) Load Line Positioning Accuracy Differential Nonlinearity Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate LLSET Input Voltage Range LLSET Input Bias Current BOOT Voltage Hold Time VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time No CPU Detection Turn-Off Delay Time OSCILLATOR Frequency Range Frequency Variation Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Current Limit Latch-Off Delay Time IMON Output CURRENT BALANCE AMPLIFIER Common-Mode Range Input Resistance Input Current Input Current Matching CURRENT LIMIT COMPARATOR ILIMIT Bias Current IFB IFBRTN ICOMP GBW(ERR) VLLSET ILLSET tBOOT VIL(VID) VIH(VID) IIN(VID) fOSC fPHASE VRT VRAMPADJ IRAMPADJ VOS(CSA) IBIAS(CSSUM) GBW(CSA) Relative to nominal DAC output, referenced to FBRTN, LLSET = CSREF (see Figure 2) In startup CSREF − LLSET = 80 mV IFB = IIREF FB forced to VOUT – 3% COMP = FB COMP = FB Relative to CSREF 0 −11 1.089 −78 −1 13.5 1.1 −80 15 65 500 20 25 −350 −10 CDELAY = 10 nF +350 +10 2 VID(X), VIDSEL VID(X), VIDSEL 0.8 VID code change to FB change VID code change to PWM going low 400 5 0.4 V V μA ns μs 4 240 MHz kHz kHz kHz V mV μA −1 TA = 25°C, RT = 243 kΩ, 4-phase TA = 25°C, RT = 113 kΩ, 4-phase TA = 25°C, RT = 51 kΩ, 4-phase RT = 243 kΩ to GND RAMPADJ − FB CSSUM − CSREF (see Figure 3) CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF 0.25 156 1.9 −50 1 −2 −10 2.1 +50 50 +2 +10 +6 mV nA MHz V/μs V V μA ms % 17 12 +200 26 20 +5 mV kΩ μA % 10 11 μA 10 10 0 0.05 ICSCOMP tOC(DELAY) IMON CDELAY = 10 nF 10 × (CSREF − CSCOMP) > 50 mV −6 VSW(X)CM RSW(X) ISW(X) ∆ISW(X) SW(X) = 0 V SW(X) = 0 V SW(X) = 0 V −600 10 8 −5 IILIMIT IILIMIT = 2/3 × IIREF 9 Rev. A | Page 3 of 32 200 400 800 2.0 3.5 3.5 500 8 ADP3198 Parameter ILIMIT Voltage Maximum Output Voltage Current-Limit Threshold Voltage Current-Limit Setting Ratio DELAY TIMER Normal Mode Output Current Output Current in Current Limit Threshold Voltage SOFT START Output Current ENABLE INPUT Threshold Voltage Hysteresis Input Current Delay Time OD OUTPUT Output Low Voltage Output High Voltage Symbol VILIMIT Conditions RILIMIT = 121 kΩ (VILIMIT = (IILIMIT × RILIMIT)) VCL VCSREF − VCSCOMP, RILIMIT = 121 kΩ VCL/VILIMIT IDELAY IDELAY(CL) VDELAY(TH) ISS VTH(EN) VHYS(EN) IIN(EN) tDELAY(EN) Min 1.09 3 80 Typ 1.21 Max 1.33 100 82.6 125 IDELAY = IIREF IDELAY(CL) = 0.25 × IIREF 12 3.0 1.6 15 3.75 1.7 18 4.5 1.8 μA μA V During startup, ISS = IIREF 12 15 18 μA 800 80 850 100 −1 2 900 125 mV mV μA ms 160 500 mV EN > 950 mV, CDELAY = 10 nF VOL(OD) VOH(OD) 4 OD Pull Down Resistor THERMAL THROTTLING CONTROL TTSENSE Voltage Range TTSENSE Bias Current TTSENSE VRFAN Threshold Voltage TTSENSE VRHOT Threshold Voltage TTSENSE Hysteresis VRFAN Output Low Voltage VRHOT Output Low Voltage POWER-GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Low Voltage Power-Good Delay Time During Soft Start VID Code Changing VID Code Static Crowbar Trip Point Crowbar Reset Point Crowbar Delay Time VID Code Changing VID Code Static PWM OUTPUTS Output Low Voltage Output High Voltage SUPPLY VCC DC Supply Current UVLO Turn-On Current UVLO Threshold Voltage UVLO Turn-Off Voltage Internally limited VOL(VRFAN) VOL(VRHOT) IVRFAN(SINK) = −4 mA IVRHOT(SINK) = −4 mA VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) Relative to nominal DAC output Relative to nominal DAC output IPWRGD(SINK) = −4 mA 0 −133 1.06 765 −450 250 CDELAY = 10 nF 100 VCROWBAR tCROWBAR Relative to nominal DAC output Relative to FBRTN Overvoltage to PWM going low 250 395 100 VOL(PWM) VOH(PWM) VCC IVCC IPWM(SINK) = −400 μA IPWM(SOURCE) = 400 μA VSYSTEM = 12 V, RSHUNT = 340 Ω (see Figure 2) 5 V 60 kΩ −123 1.105 810 50 150 150 300 300 V μA V mV mV mV mV −500 300 150 −550 350 300 mV mV mV 350 505 ms μs ns mV mV 2 250 200 300 450 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 Guaranteed by design or bench characterization, not tested in production. Rev. A | Page 4 of 32 μs ns 160 5 500 4.0 mV V 4.65 5 5.55 25 11 V mA mA V V VSYSTEM = 13.2 V, RSHUNT = 340 Ω VCC rising VCC falling 5 −113 1.15 855 250 400 6.5 VUVLO Unit V V mV mV/V 9 4.1 ADP3198 TEST CIRCUITS 12V 680Ω 8-BIT CODE + 1µF ADP3198 12V 680Ω 680Ω 680Ω VCC 31 100nF COMP 40 EN PWRGD FBRTN FB COMP SS DELAY VRFAN VRHOT TTSENSE ADP3198 ILIMIT RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD IREF 10nF 1 10kΩ PWM1 PWM2 PWM3 PWM4 NC SW1 SW2 SW3 SW4 NC LLSET 14 ΔV 1V 06094-002 100nF 12V ADP3198 680Ω VCC 31 CSCOMP 17 39kΩ 100nF CSSUM 16 1kΩ CSREF GND 18 VOS = CSCOMP – 1V 40 06094-003 15 1V VID DAC GND ΔVFB = FBΔV = 80mV – FBΔV = 0mV Figure 2. Closed-Loop Output Voltage Accuracy 680Ω + 18 20kΩ NC = NO CONNECT – CSREF 15 100kΩ 250kΩ FB 3 Figure 3. Current Sense Amplifier VOS Rev. A | Page 5 of 32 Figure 4. Positioning Voltage 06094-004 1kΩ 10nF VIDSEL VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VCC 1.25V 4 ADP3198 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC FBRTN PWM3 to PWM4, RAMPADJ SW1 to SW4 <200 ns All Other Inputs and Outputs Storage Temperature Range Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (θJA) Lead Temperature Soldering (10 sec) Infrared (15 sec) Rating −0.3 V to +6 V −0.3 V to +0.3 V −0.3 V to VCC + 0.3 V −5 V to +25 V −10 V to +25 V −0.3 V to VCC + 0.3 V −65°C to +150°C 0°C to 85°C 125°C 39°C/W 300°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages referenced to GND. ESD CAUTION Rev. A | Page 6 of 32 ADP3198 40 39 38 37 36 35 34 33 32 31 VIDSEL VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VCC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR ADP3198 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 PWM1 PWM2 PWM3 PWM4 NC SW1 SW2 SW3 SW4 IMON NOTES 1. NC = NO CONNECT. 2. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN ELECTRICAL CONNECTION AND SHOULD BE SOLDERED TO GROUND. 06094-005 ILIMIT RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD IREF 11 12 13 14 15 16 17 18 19 20 EN 1 PWRGD 2 FBRTN 3 FB 4 COMP 5 SS 6 DELAY 7 VRFAN 8 VRHOT 9 TTSENSE 10 Figure 5. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic EN PWRGD FBRTN FB 5 6 COMP SS 7 DELAY 8 VRFAN 9 VRHOT 10 TTSENSE 11 12 ILIMIT RT 13 14 RAMPADJ LLSET 15 CSREF 16 CSSUM 17 CSCOMP 18 19 GND OD 20 IREF Description Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Power-Good Output. Open-drain output that signals when the output voltage is outside of the proper operating range. Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no load offset point. Error Amplifier Output and Compensation Point. Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start ramp-up time. Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent latchoff delay time, boot voltage hold time, EN delay time, and PWRGD delay time. VR Fan Activation Output. Open-drain output that signals when the temperature at the monitoring point connected to TTSENSE exceeds the programmed VRFAN temperature threshold. VR Hot Output. Open-drain output that signals when the temperature at the monitoring point connected to TTSENSE exceeds the programmed VRHOT temperature threshold. VR Hot Thermal Throttling Sense Input. An NTC thermistor between this pin and GND is used to remotely sense the temperature at the desired thermal monitoring point. Current-Limit Set Point. An external resistor from this pin to GND sets the current-limit threshold of the converter. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Output Load Line Programming Input. This pin can be directly connected to CSCOMP, or it can be connected to the center point of a resistor divider between CSCOMP and CSREF. Connecting LLSET to CSREF disables positioning. Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power-good and crowbar functions. This pin should be connected to the common point of the output inductors. Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the current sense amplifier and the positioning loop response time. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO threshold to signal to the Driver IC that the driver high-side and low-side outputs should go low. Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB, IDELAY, ISS, IILIMIT, and ITTSENSE. Rev. A | Page 7 of 32 ADP3198 Pin No. 21 22 to 25 Mnemonic IMON SW4 to SW1 26 27 to 30 NC PWM4 to PWM1 31 VCC 32 to 39 VID7 to VID0 40 VIDSEL Description Analog Output. Represents the total load current. Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. No Connection. Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3110A. Connecting the PWM4, and PWM3 outputs to VCC causes that phase to turn off, allowing the ADP3198 to operate as a 2-, 3-, or 4-phase controller. Supply Voltage for the Device. A 340 Ω resistor should be placed between the 12 V system supply and the VCC pin. The internal shunt regulator maintains VCC = 5 V. Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a Logic 0 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.5 V to 1.6 V (see Table 4). VID DAC Selection Pin. The logic state of this pin determines whether the internal VID DAC decodes VID0 to VID7 as extended VR10 or VR11 inputs. Rev. A | Page 8 of 32 ADP3198 TYPICAL PERFORMANCE CHARACTERISTICS 7000 6000 4000 MASTER CLOCK 3000 2000 PHASE 1 IN 4 PHASE DESIGN 1000 0 13 20 30 43 68 75 82 130 180 270 395 430 680 850 RT (kΩ) 06094-018 FREQUENCY (kHz) 5000 Figure 6. Master Clock Frequency vs. RT Rev. A | Page 9 of 32 ADP3198 THEORY OF OPERATION The ADP3198 combines a multimode, fixed frequency, PWM control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck CPU core supply power converters. The internal VID DAC is designed to interface with the Intel 8-bit VRD/VRM 11-compatible and 7-bit VRD/VRM 10×-compatible CPUs. Multiphase operation is important for producing the high currents and low voltages demanded by today’s microprocessors. Handling the high currents in a single-phase converter places high thermal demands on the components in the system, such as the inductors and MOSFETs. 5V SUPPLY VTT I/O (ADP3198 EN) • High speed response at the lowest possible switching frequency and output decoupling VDELAY(TH) (1.7V) 1V SS VBOOT (1.1V) VVID TD3 VCC_CORE VBOOT (1.1V) TD1 VVID TD4 TD2 VR READY (ADP3198 PWRGD) 50µs CPU VID INPUTS • Minimizing thermal switching losses by using lower frequency operation • Tight load line regulation and accuracy • High current output due to 4-phase operation • Reduced output ripple due to multiphase cancellation • PC board layout noise immunity • Ease of use and design due to independent component selection • Flexibility in operation for tailoring design to low cost or high performance VID INVALID TD5 VID VALID 06094-006 Balancing currents and thermals between phases 0.85V DELAY The multimode control of the ADP3198 ensures a stable, high performance topology for the following: • UVLO THRESHOLD Figure 7. System Start-Up Sequence PHASE DETECTION SEQUENCE During startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3198 operates as a 4-phase PWM controller. Connecting the PWM4 pin to VCC programs 3-phase operation and connecting the PWM4 and PWM3 pins to VCC programs 2-phase operation. START-UP SEQUENCE The ADP3198 follows the VR11 start-up sequence shown in Figure 7. After both the EN and UVLO conditions are met, the DELAY pin goes through one cycle (TD1). The first four clock cycles of TD2 are blanked from the PWM outputs and used for phase detection as explained in the Phase Detection Sequence section. Then, the soft start ramp is enabled (TD2), and the output comes up to the boot voltage of 1.1 V. The boot hold time is determined by the DELAY pin as it goes through a second cycle (TD3). During TD3, the processor VID pins settle to the required VID code. When TD3 is over, the ADP3198 soft starts either up or down to the final VID voltage (TD4). After TD4 is completed and the PWRGD masking time (equal to VID on-the-fly masking) is completed, a third ramp on the DELAY pin sets the PWRGD blanking (TD5). Prior to soft start, while EN is low, the PWM3 and PWM4 pins sink approximately 100 μA. An internal comparator checks each pin’s voltage vs. a threshold of 3 V. If the pin is tied to VCC, it is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold. PWM1 and PWM2 are low during the phase detection interval that occurs during the first four clock cycles of TD2. After this time, if the remaining PWM outputs are not pulled to VCC, the 100 μA current sink is removed, and they function as normal PWM outputs. If they are pulled to VCC, the 100 μA current source is removed, and the outputs are put into a high impedance state. The PWM outputs are logic-level devices intended for driving external gate drivers such as the ADP3110A. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can be on at the same time to allow overlapping phases. Rev. A | Page 10 of 32 ADP3198 MASTER CLOCK FREQUENCY The clock frequency of the ADP3198 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 6. To determine the frequency per phase, the clock is divided by the number of phases in use. If all phases are in use, divide by 4. If PWM4 is tied to VCC, divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and PWM4 are tied to VCC, divide by 2. OUTPUT VOLTAGE DIFFERENTIAL SENSING The ADP3198 combines differential sensing with a high accuracy VID DAC and reference, and a low offset error amplifier. This maintains a worst-case specification of ±9.5 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB pin and FBRTN pin. FB should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 65 μA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage. OUTPUT CURRENT SENSING The ADP3198 provides a dedicated current-sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current and for current-limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low-side MOSFET. This amplifier can be configured several ways, depending on the objectives of the system, as follows: • Output inductor DCR sensing without a thermistor for lowest cost • Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature • Sense resistors for highest accuracy measurements The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors, to the inverting input CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor. An additional resistor divider connected between CSREF and CSCOMP (with the midpoint connected to LLSET) can be used to set the load line required by the microprocessor. The current information is then given as CSREF − LLSET. This difference signal is used internally to offset the VID DAC for voltage positioning. The difference between CSREF and CSCOMP is then used as a differential input for the current-limit comparator. This allows the load line to be set independently of the currentlimit threshold. In the event that the current-limit threshold and load line are not independent, the resistor divider between CSREF and CSCOMP can be removed and the CSCOMP pin can be directly connected to LLSET. To disable voltage positioning entirely (that is, no load line), connect LLSET to CSREF. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors to make it extremely accurate. ACTIVE IMPEDANCE CONTROL MODE For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the LLSET pin can be scaled to equal the regulator droop impedance multiplied by the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage to tell the error amplifier where the output voltage should be. This allows enhanced feed-forward response. CURRENT CONTROL MODE AND THERMAL BALANCE The ADP3198 has individual inputs (SW1 to SW4) for each phase that are used for monitoring the current of each phase. This information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning as described in the Output Current Sensing section. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed-forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. External resistors can be placed in series with individual phases to create an intentional current imbalance if desired, such as when one phase has better cooling and can support higher currents. Resistor RSW1 through Resistor RSW4 (see Figure 10) can be used for adjusting thermal balance in this 4-phase example. It is best to have the ability to add these resistors during the initial design, therefore, ensure that placeholders are provided in the layout. Rev. A | Page 11 of 32 ADP3198 To increase the current in any given phase, enlarge RSW for that phase (make RSW = 0 for the hottest phase and do not change it during balancing). Increasing RSW to only 500 Ω makes a substantial increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first. VOLTAGE CONTROL MODE A high gain, high bandwidth, voltage mode error amplifier is used for the voltage mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in Table 4. This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with Resistor RB and is used for sensing and controlling the output voltage at this point. A current source (equal to IREF) from the FB pin flowing through RB is used for setting the no load offset voltage from the VID voltage. The no load voltage is negative with respect to the VID DAC. The main loop compensation is incorporated into the feedback network between FB and COMP. B B The IREF pin is used to set an internal current reference. This reference current sets IFB, IDELAY, ISS, ILIMIT, and ITTSENSE. A resistor to ground programs the current based on the 1.5 V output. 1.5 V R IREF Typically, RIREF is set to 100 kΩ to program IREF = 15 μA. The following currents are then equal to IFB = IREF = 15 μA IDELAY = IREF = 15 μA ISS = IREF = 15 μA ILIMIT = 2/3 (IREF) = 10 μA Enhanced PWM mode is intended to improve the transient response of the ADP3198 to a load setup. In previous generations of controllers, when a load step up occurred, the controller had to wait until the next turn-on of the PWM signal to respond to the load change. Enhanced PWM mode allows the controller to immediately respond when a load step up occurs. This allows the phases to respond more quickly when a load increase takes place. DELAY TIMER The delay times for the start-up timing sequence are set with a capacitor from the DELAY pin to ground. In UVLO, or when EN is logic low, the DELAY pin is held at ground. After the UVLO and EN signals are asserted, the first delay time (TD1 in Figure 7) is initiated. A current flows out of the DELAY pin to charge CDLY. This current is equal to IREF, which is normally 15 μA. A comparator monitors the DELAY voltage with a threshold of 1.7 V. The delay time is therefore set by the IREF current charging a capacitor from 0 V to 1.7 V. This DELAY pin is used for multiple delay timings (TD1, TD3, and TD5) during the start-up sequence. In addition, DELAY is used for timing the current-limit latch off, as explained in the Current-Limit, Short-Circuit, and Latch-Off Protection section. SOFT START CURRENT REFERENCE IREF = ENHANCED PWM MODE The soft start times for the output voltage are set with a capacitor from the SS pin to ground. After TD1 and the phase detection cycle are complete, the SS time (TD2 in Figure 7) starts. The SS pin is disconnected from GND, and the capacitor is charged up to the 1.1 V boot voltage by the SS amplifier, which has an output current equal to IREF (normally 15 μA). The voltage at the FB pin follows the ramping voltage on the SS pin, limiting the inrush current during startup. The soft start time depends on the value of the boot voltage and CSS. Once the SS voltage is within 100 mV of the boot voltage, the boot voltage delay time (TD3 in Figure 7) is started. The end of the boot voltage delay time signals the beginning of the second soft start time (TD4 in Figure 7). The SS voltage now changes from the boot voltage to the programmed VID DAC voltage (either higher or lower) using the SS amplifier with the output current equal to IREF. The voltage of the FB pin follows the ramping voltage of the SS pin, limiting the inrush current during the transition from the boot voltage to the final DAC voltage. The second soft start time depends on the boot voltage, the programmed VID DAC voltage, and CSS. Rev. A | Page 12 of 32 ADP3198 If EN is taken low or if VCC drops below UVLO, DELAY and SS are reset to ground to be ready for another soft start cycle. Figure 8 shows typical start-up waveforms for the ADP3198. 1 During startup, when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit controls the internal COMP voltage to the PWM comparators to 1.5 V. This limits the voltage drop across the low-side MOSFETs through the current balance circuitry. An inherent per-phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage. Typical overcurrent latch-off waveforms are shown in Figure 9. 2 CH2 1V CH4 10V M 1ms T 40.4% A CH1 700mV Figure 8. Typical Start-Up Waveforms (Channel 1: CSREF, Channel 2: DELAY, Channel 3: SS, and Channel 4: Phase 1 Switch Node) CURRENT-LIMIT, SHORT-CIRCUIT, AND LATCHOFF PROTECTION 1 The ADP3198 compares a programmable current-limit set point to the voltage from the output of the current-sense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During operation, the current from ILIMIT is equal to 2/3 of IREF, giving 10 μA normally. This current through the external resistor sets the ILIMIT voltage, which is internally scaled to give a current limit threshold of 82.6 mV/V. If the difference in voltage between CSREF and CSCOMP rises above the current-limit threshold, the internal current-limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. If the limit is reached and TD5 in Figure 7 has completed, a latch-off delay time starts, and the controller shuts down if the fault is not removed. The current-limit delay time shares the DELAY pin timing capacitor with the start-up sequence timing. However, during current limit, the DELAY pin current is reduced to IREF/4. A comparator monitors the DELAY voltage and shuts off the controller when the voltage reaches 1.7 V. Therefore, the current-limit latch-off delay time is set by the current of IREF/4 charging the delay capacitor from 0 V to 1.7 V. This delay is four times longer than the delay time during the start-up sequence. The current-limit delay time starts only after the TD5 is complete. If there is a current limit during startup, the ADP3198 goes through TD1 to TD5, and then starts the latchoff time. Because the controller continues to cycle the phases during the latch-off delay time, the controller returns to normal operation and the DELAY capacitor is reset to GND if the short is removed before the 1.7 V threshold is reached. 2 3 4 CH1 1V CH3 2V CH2 1V CH4 10V M 2ms T 61.8% A CH1 680mV 06094-008 CH1 1V CH3 1V 06094-007 3 4 The latch-off function can be reset by either removing and reapplying the supply voltage to the ADP3198, or by toggling the EN pin low for a short time. To disable the short-circuit latch-off function, an external resistor should be placed in parallel with CDLY. This prevents the DELAY capacitor from charging up to the 1.7 V threshold. The addition of this resistor causes a slight increase in the delay times. Figure 9. Overcurrent Latch-Off Waveforms (Channel 1: CSREF, Channel 2: DELAY, Channel 3: COMP, and Channel 4: Phase 1 Switch Node) DYNAMIC VID The ADP3198 has the ability to dynamically change the VID inputs while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID onthe-fly (OTF). A VID OTF can occur under light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. When a VID input changes state, the ADP3198 detects the change and ignores the DAC inputs for a minimum of 400 ns. This time prevents a false code due to logic skew while the eight VID inputs are changing. Additionally, the first VID change initiates the PWRGD and crowbar blanking functions for a minimum of 100 μs to prevent a false PWRGD or crowbar event. Each VID change resets the internal timer. Rev. A | Page 13 of 32 ADP3198 POWER-GOOD MONITORING OUTPUT ENABLE AND UVLO The power-good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level, when connected to a pull-up resistor, indicates that the output voltage is within the nominal limits specified based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if the VID DAC inputs are in no CPU mode, or if the EN pin is pulled low. PWRGD is blanked during a VID OTF event for a period of 200 μs to prevent false signals during the time the output is changing. For the ADP3198 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold and the EN pin must be higher than its 0.85 V threshold. This initiates a system start-up sequence. If either UVLO or EN is less than their respective thresholds, the ADP3198 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and forces PWRGD and OD signals low. The PWRGD circuitry also incorporates an initial turn-on delay time (TD5), based on the DELAY timer. Prior to the SS voltage reaching the programmed VID DAC voltage and the PWRGD masking-time finishing, the PWRGD pin is held low. Once the SS pin is within 100 mV of the programmed DAC voltage, the capacitor on the DELAY pin begins to charge. A comparator monitors the DELAY voltage and enables PWRGD when the voltage reaches 1.7 V. The PWRGD delay time is set, therefore, by a current of IREF, charging a capacitor from 0 V to 1.7 V. OUTPUT CROWBAR To protect the load and output components of the supply, the PWM outputs are driven low, which turns on the low-side MOSFETs when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 375 mV. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action current limits the input supply or blows its fuse, protecting the microprocessor from being destroyed. In the application circuit (see Figure 10), the OD pin should be connected to the OD inputs of the ADP3110A drivers. Grounding OD disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs are not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors. THERMAL MONITORING The ADP3198 includes a thermal-monitoring circuit to detect when a point on the VR has exceeded two different userdefined temperatures. The thermal-monitoring circuit requires an NTC thermistor to be placed between TTSENSE and GND. A fixed current of 8 × IREF (normally giving 123 μA) is sourced out of the TTSENSE pin and into the thermistor. The current source is internally limited to 5 V. An internal circuit compares the TTSENSE voltage to a 1.105 V and a 0.81 V threshold, and outputs an open-drain signal at the VRFAN and VRHOT outputs, respectively. Once the voltage on the TTSENSE pin drops below its respective threshold, the open-drain outputs assert high to signal the system that an overtemperature event has occurred. Because the TTSENSE voltage changes slowly with respect to time, 50 mV of hysteresis is built into these comparators. The thermal monitoring circuitry does not depend on EN and is active when UVLO is above its threshold. When UVLO is below its threshold, VRFAN and VRHOT are forced low. Rev. A | Page 14 of 32 ADP3198 Table 4.VR11 and VR10.x VID Codes for the ADP3198 OUTPUT OFF OFF 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VR11 DAC CODES: VIDSEL = HIGH VID5 VID4 VID3 VID2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Rev. A | Page 15 of 32 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VR10.x DAC CODES: VIDSEL = LOW VID3 VID2 VID1 VID0 VID5 N/A N/A 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 1 0 1 0 1 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 0 1 1 0 1 0 1 1 1 0 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 0 0 0 0 VID6 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ADP3198 OUTPUT 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 OFF OFF OFF OFF 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VR11 DAC CODES: VIDSEL = HIGH VID5 VID4 VID3 VID2 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 N/A N/A N/A N/A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Rev. A | Page 16 of 32 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VR10.x DAC CODES: VIDSEL = LOW VID3 VID2 VID1 VID0 VID5 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 1 1 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 1 0 1 0 1 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 VID6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ADP3198 OUTPUT 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 0.81250 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 0.76250 0.75625 0.75000 0.74375 0.73750 0.73125 0.72500 0.71875 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.66875 0.66250 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VR11 DAC CODES: VIDSEL = HIGH VID5 VID4 VID3 VID2 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Rev. A | Page 17 of 32 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VR10.x DAC CODES: VIDSEL = LOW VID3 VID2 VID1 VID0 VID5 0 1 1 0 1 0 1 1 1 0 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 1 1 0 0 1 1 1 0 1 0 0 1 0 1 0 0 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A VID6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ADP3198 OUTPUT 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 0.51875 0.51250 0.50625 0.50000 OFF OFF VID7 1 1 1 1 1 1 1 1 1 1 1 1 VID6 0 0 0 0 0 0 0 0 0 0 1 1 VR11 DAC CODES: VIDSEL = HIGH VID5 VID4 VID3 VID2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 VID1 0 1 1 0 0 1 1 0 0 1 1 1 VID0 1 0 1 0 1 0 1 0 1 0 0 1 Rev. A | Page 18 of 32 VID4 1 1 VR10.x DAC CODES: VIDSEL = LOW VID3 VID2 VID1 VID0 VID5 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 1 1 1 1 1 1 1 1 1 1 VID6 0 1 Figure 10. Typical 4-Phase Application Circuit Rev. A | Page 19 of 32 1 2 R3 1Ω CDLY 18nF RA CA 560pF 13.7kΩ CFB 15pF RTH1 100kΩ, 5% NTC CSS 18nF C5 1nF C6 0.1µF 1 RT 130kΩ 1% RLIM 205kΩ 1% EN PWRGD FBRTN FB COMP SS DELAY VRFAN VRHOT TTSENSE 40 C4 1µF FROM CPU + 560Ω C3 100µF (C3 OPTIONAL) R2 267kΩ 1% 12V C2 + 560Ω U1 ADP3198 C7 1nF CCS1 2nF 5% NPO RIREF 100kΩ PWM1 PWM2 PWM3 PWM4 NC SW1 SW2 SW3 SW4 IMON FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION. CONNECT NEAR EACH INDUCTOR. C8 1nF RB 1.21kΩ CB 680pF POWER GOOD VRFAN PROCHOT VTT I/O 1µF 1kΩ C1 + VIDSEL VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VCC ILIMIT RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD IREF VIN RTN 2700µF/16V/3.3A × 2 SANYO MV-WX SERIES CCS2 2.2nF 5% NPO RPH2 RPH4 93.1kΩ 93.1kΩ 1% 1% RCS2 RCS1 RPH3 35.7kΩ 82.5kΩ 93.1kΩ 1% RSW41 RSW31 RSW21 RSW1 1 RPH1 93.1kΩ 1% C22 4.7µF D5 1N4148 C18 4.7µF D4 1N4148 C14 4.7µF D3 1N4148 C10 4.7µF D2 1N4148 PGND 6 DRVL 5 VCC 4 SW 7 DRVH 8 OD IN 2 3 BST 1 C23 10nF C21 18nF U5 ADP3110A R7 2.2Ω DRVL 5 OD 3 VCC IN 4 SW 7 PGND 6 BST 2 DRVH 8 C19 10nF C17 18nF DRVL 5 PGND 6 SW 7 DRVH 8 U4 ADP3110A R6 2.2Ω VCC OD IN BST 1 4 3 2 1 C13 18nF R5 2.2Ω C15 10nF DRVL 5 4 VCC U3 ADP3110A PGND 6 SW 7 DRVH 8 3 OD 2 IN 1 BST C11 10nF C9 18nF U2 ADP3110A R4 2.2Ω Q15 NTD110N02 Q13 NTD40N03 Q11 NTD110N02 Q9 NTD40N03 Q7 NTD110N02 Q5 NTD40N03 Q3 NTD110N02 Q1 NTD40N03 C12 4.7µF C16 4.7µF C20 4.7µF C24 4.7µF Q16 NTD110N02 Q14 NTD40N03 L5 320nH/1.4mΩ Q12 NTD110N02 Q10 NTD40N03 L4 320nH/1.4mΩ Q8 NTD110N02 Q6 NTD40N03 L3 320nH/1.4mΩ Q4 NTD110N02 + C25 RTH2 100kΩ, 5% NTC 10Ω2 10Ω2 10Ω2 10Ω2 + C32 Q2 NTD40N03 560µF/4V × 8 L2 320nH/1.4mΩ SANYO SEPC SERIES 5mΩ EACH VCC(CORE) RTN VCC(CORE) 0.5V TO 1.6V 115A TDC, 130A PK VSS(SENSE) VCC(SENSE) 22µF × 18 MLCC IN SOCKET 06094-009 VIN 12V L1 370nH 18A ADP3198 ADP3198 APPLICATION INFORMATION SOFT START DELAY TIME The design parameters for a typical Intel VRD 11 compliant CPU application are as follows: The value of CSS sets the soft start time. The ramp is generated with a 15 μA internal current source. The value for CSS can be found using • Input voltage (VIN) = 12 V • VID setting voltage (VVID) = 1.300 V • Duty cycle (D) = 0.108 • Nominal output voltage at no load (VONL) = 1.285 V • Nominal output voltage at 115 A load (VOFL) = 1.170 V • Static output voltage drop based on a 1.0 mΩ load line (RO) from no load to full load (VD) = VONL − VOFL = 1.285 V − 1.170 V = 115 mV • Maximum output current (IO) = 130 A Assuming a desired TD2 time of 3 ms, CSS is 41 nF. The closest standard value for CSS is 39 nF. Although CSS also controls the time delay for TD4 (determined by the final VID voltage), the minimum specification for TD4 is 0 ns. This means that as long as the TD2 time requirement is met, TD4 is within the specification. • Maximum output current step (ΔIO) = 100 A CURRENT-LIMIT LATCH-OFF DELAY TIMES • Maximum output current slew rate (SR) = 200 A/μs • Number of phases (n) = 4 • Switching frequency per phase (fSW) = 330 kHz The start-up and current-limit delay times are determined by the capacitor connected to the DELAY pin. The first step is to set CDLY for the TD1, TD3, and TD5 delay times (see Figure 7). The DELAY ramp (IDELAY) is generated using a 15 μA internal current source. The value for CDLY can be approximated using C SS = 15 μA × C DLY = I DELAY × The ADP3198 uses a fixed frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses as well as the sizes of the inductors, the input capacitors, and output capacitors. With n = 4 for four phases, a clock frequency of 1.32 MHz sets the switching frequency (fSW) of each phase to 330 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Figure 6 shows that to achieve a 1.32 MHz oscillator frequency, the correct value for RT is 130 kΩ. Alternatively, the value for RT can be calculated using 1 n × f SW × 6 pF (2) where TD2 is the desired soft start time, and VBOOT is internally set to 1.1 V. SETTING THE CLOCK FREQUENCY RT = TD 2 V BOOT TD(x ) VDELAY (TH ) (3) where TD(x) is the desired delay time for TD1, TD3, and TD5. The DELAY threshold voltage (VDELAY(TH)) is given as 1.7 V. In this example, 2 ms is chosen for all three delay times, which meets Intel specifications. Solving for CDLY gives a value of 17.6 nF. The closest standard value for CDLY is 18 nF. When the ADP3198 enters current limit, the internal current source changes from 15 μA to 3.75 μA. This makes the latch-off delay time four times longer than the start-up delay time. Longer latch-off delay times can be achieved by placing a resistor in parallel with CDLY. (1) where 6 pF is the internal IC component values. For good initial accuracy and frequency stability, a 1% resistor is recommended. Rev. A | Page 20 of 32 ADP3198 INDUCTOR SELECTION Designing an Inductor The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs. However, using smaller inductors allows the converter to meet a specified peak-to-peak transient deviation with less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but more output capacitance is required to meet the same peak-to-peak transient deviation. Once the inductance and DCR are known, the next step is to either design an inductor or to find a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to control the accuracy of the system. Reasonable tolerances most manufacturers can meet are 15% inductance and 7% DCR at room temperature. The first decision in designing the inductor is choosing the core material. Several possibilities for providing low core loss at high frequencies include the powder cores (from Micrometals, Inc., for example, or Kool Mu® from Magnetics®) and the gapped soft ferrite cores (for example, 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. In any multiphase converter, a practical value for the peak-topeak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor. IR = VVID × (1 − D ) (4) f SW × L Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage. L≥ VVID × R O × (1 − (n × D )) (5) f SW × V RIPPLE Solving Equation 5 for an 8 mV p-p output ripple voltage yields L≥ 1.3 V × 1.0 mΩ × (1 − 0.432 ) 330 kHz × 8 mV The best choice for a core geometry is a closed-loop type such as a potentiometer core (PQ, U, or E core) or toroid. A good compromise between price and performance is a core with a toroidal shape. Many useful magnetics design references are available for quickly designing a power inductor, such as • Intusoft Magnetic Designer Software • Designing Magnetic Components for High Frequency DC to DC Converters, by William T. McLyman, Kg Magnetics, Inc., ISBN 1883107008 = 280 nH If the resulting ripple voltage is less than what is designed for, the inductor can be made smaller until the ripple value is met. This allows optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 320 nH inductor is a good starting point and gives a calculated ripple current of 11 A. The inductor should not saturate at the peak current of 35.5 A and should be able to handle the sum of the power dissipation caused by the average current of 30 A in the winding and core loss. Selecting a Standard Inductor The following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request. • Coilcraft® • Coiltronics® • Sumida Corporation® Another important factor in the inductor design is the dc resistance (DCR), which is used for measuring the phase currents. A large DCR can cause excessive power losses, though too small a value can lead to increased measurement error. A good rule is to have the DCR (RL) be about 1 to 1½ times the droop resistance (RO). This example uses an inductor with a DCR of 1.4 mΩ. Rev. A | Page 21 of 32 ADP3198 CURRENT SENSE AMPLIFIER INDUCTOR DCR TEMPERATURE CORRECTION Most designs require the regulator output voltage, measured at the CPU pins, to drop when the output current increases. The specified voltage drop corresponds to a dc output resistance (RO), also referred to as a load line. The ADP3198 has the flexibility of adjusting RO, independent of current-limit or compensation components, and it can also support CPUs that do not require a load line. When the inductor DCR is used as the sense element and copper wire is used as the source of the DCR, the user needs to compensate for temperature changes of the inductor’s winding. Fortunately, copper has a well known temperature coefficient (TC) of 0.39%/°C. PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR OR LOW-SIDE MOSFET The output current is measured by summing the voltage across each inductor and passing the signal through a low-pass filter. This summer filter is the CS amplifier configured with resistors RPH(X) (summers), and RCS and CCS (filter). The impedance gain of the regulator is set by the following equations, where RL is the DCR of the output inductors: R CSA = C CS R CS R PH ( x ) 17 (7) 1.4 mΩ RCS2 CCS2 KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES CSREF Figure 11. Temperature Compensation Circuit Values The following procedure and equations yield values to use for RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given RCS value. 1. Select an NTC based on type and value. Because the value is unknown, use a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%. 2. Based on the type of NTC, find its relative resistance value at two temperatures. The temperatures that work well are 50°C and 90°C. These resistance values are called A (RTH(50°C))/RTH(25°C)) and B (RTH(90°C))/RTH(25°C)). The relative value of the NTC is always 1 at 25°C. 3. Find the relative value of RCS required for each of these temperatures. This is based on the percentage change needed, which in this example is initially 0.39%/°C. These temperatures are called r1 (1/(1 + TC × (T1 − 25°C))) and r2 (1/(1 + TC × (T2 − 25°C))), where TC = 0.0039 for copper, T1 = 50°C, and T2 = 90°C. From this, r1 = 0.9112 and r2 = 0.7978. × 100 kΩ = 140 kΩ Next, use Equation 7 to solve for CCS. CCS = RPH3 16 RL × RCS RCSA 1.0 mΩ CCS1 CSSUM The user has the flexibility to choose either RCS or RPH(X). However, it is best to select RCS equal to 100 kΩ, and then solve for RPH(X) by rearranging Equation 6. Here, RCSA = RO = 1 mΩ because this is equal to the design load line. RPH ( x ) = RCS1 RPH2 TO VOUT SENSE 18 (6) L = R L × RCS RPH ( x ) = RPH1 ADP3198 CSCOMP × RL TO SWITCH NODES RTH 320 nH 1.4 mΩ × 100 kΩ = 2.28 nF It is best to have a dual location for CCS in the layout so that standard values can be used in parallel to get as close to the desired value. For best accuracy, CCS should be a 5% or 10% NPO capacitor. This example uses a 5% combination for CCS of two 1 nF capacitors in parallel. Recalculating RCS and RPH(X) using this capacitor combination yields 114 kΩ and 160 kΩ. The closest standard 1% value for RPH(X) is 158 kΩ. 06094-010 For designs requiring a load line, the impedance gain of the CS amplifier (RCSA) must be to be greater than or equal to the load line. All designs, whether they have a load line or not, should keep RCSA ≥ 1 mΩ. If RCS is designed to have an opposite and equal percentage change in resistance to that of the wire, it cancels the temperature variation of the inductor DCR. Due to the nonlinear nature of NTC thermistors, Resistor RCS1 and Resistor RCS2 are needed. See Figure 11 to linearize the NTC and produce the desired temperature tracking. Rev. A | Page 22 of 32 ADP3198 4. Compute the relative values for RCS1, RCS2, and RTH using rCS2 = rCS1 = rTH = ( A − B ) × r1 × r2 − A × (1 − B ) × r2 + B × (1 − A ) × r1 (8) A × (1 − B ) × r1 − B × (1 − A ) × r2 − ( A − B ) (1 − A ) 1 A − 1 − rCS2 r1 − rCS2 The two resistors RLL1 and RLL2 set up a divider between the CSCOMP pin and CSREF pin. This resistor divider is input into the LLSET pin to set the load line slope RO of the VR according to the following equation: (9) RO = 5. (14) The resistor values for RLL1 and RLL2 are limited by two factors. 1 (10) 1 1 − 1 − rCS2 rCS1 • Calculate RTH = rTH × RCS, then select the closest value of thermistor available. Also, compute a scaling factor (k) based on the ratio of the actual thermistor value used relative to the computed one. k= RLL 2 × RCSA RLL1 + RLL 2 RTH ( ACTUAL ) RLL1 + RLL 2 ≥ (11) RTH (CALCULATED ) (12) RCS2 = RCS × ((1 − k ) + (k × rCS2 )) I LIM × RCSA 50 × 10 −6 (15) Here, ILIM is the current-limit current, which is the maximum signal level that the CSA responds to. Calculate values for RCS1 and RCS2 using Equation 12 and 13. RCS1 = RCS × k × rCS1 The minimum value is based upon the loading of the CSCOMP pin. This pin’s drive capability is 500 μA and the majority of this should be allocated to the CSA feedback. If the current through RLL1 and RLL2 is limited to 10% of this (50 μA), the following limit can be placed for the minimum value for RLL1 and RLL2: • (13) In this example, RCS is calculated to be 114 kΩ. Look for an available 100 kΩ thermistor, 0603 size. One such thermistor is the Vishay NTHS0603N01N1003JR NTC thermistor with A = 0.3602 and B = 0.09174. From these values, rCS1 = 0.3795, rCS2 = 0.7195, and rTH = 1.075. The maximum value is based upon minimizing induced dc offset errors based on the bias current of the LLSET pin. To keep the induced dc error less than 1 mV, which makes this error statistically negligible, place the following limit of the parallel combination of RLL1 and RLL2: R LL1 × R LL2 1 × 10 −3 = 8.33 kΩ ≤ R LL1 + R LL2 120 × 10 −9 Solving for RTH yields 122.55 kΩ, so 100 kΩ is chosen, making k = 0.816. Next, find RCS1 and RCS2 to be 35.3 kΩ and 87.9 kΩ. Finally, choose the closest 1% resistor values, which yields a choice of 35.7 kΩ and 88.7 kΩ. (16) It is best to select the resistor values to minimize their values to reduce the noise and parasitic susceptibility of the feedback path. By combining Equation 16 with Equation 14 and selecting minimum values for the resistors, the following equations result: Load Line Setting I LIM × RO 50 μA (17) ⎞ ⎛R RLL1 = ⎜⎜ CSA − 1⎟⎟ × RLL 2 R ⎠ ⎝ O (18) R LL 2 = For load line values greater than 1 mΩ, RCSA can be set equal to RO, and the LLSET pin can be directly connected to the CSCOMP pin. When the load line value needs to be less than 1 mΩ, two additional resistors are required. Figure 12 shows the placement of these resistors. Therefore, both RLL1 and RLL2 need to be in parallel and less than 8.33 kΩ. ADP3198 CSSUM CSREF Another useful feature for some VR applications is the ability to select different load lines. Figure 12 shows an optional MOSFET switch that allows this feature. Here, design for RCSA = RO(MAX) (selected with QLL on) and then use Equation 14 to set RO = RO(MIN) (selected with QLL off). 18 17 16 RLL1 LLSET For this design, RCSA = RO = 1 mΩ. As a result, connect LLSET directly to CSCOMP; the RLL1 and RLL2 resistors are not needed. RLL2 OPTIONAL LOAD LINE SELECT SWITCH 15 QLL 06094-011 CSCOMP Figure 12. Load Line Setting Resistors Rev. A | Page 23 of 32 ADP3198 OUTPUT OFFSET The Intel specification requires that at no load the nominal output voltage of the regulator be offset to a value lower than the nominal voltage corresponding to the VID code. The offset is set by a constant current source flowing out of the FB pin (IFB) and flowing through RB. The value of RB can be found using Equation 19. B RB = RB = A lower limit is based on meeting the capacitance for load release for a given maximum load step (ΔIO) and a maximum allowable overshoot. The total amount of load release voltage is given as ΔVO = ΔIO × RO + ΔVrl, where ΔVrl is the maximum allowable overshoot voltage. B VVID − VONL I FB 1.3 V − 1.285 V 15 μA = 1.00 kΩ (19) COUT SELECTION The required output decoupling for the regulator is typically recommended by Intel for various processors and platforms. Use some simple design guidelines to determine the requirements. These guidelines are based on having both bulk capacitors and ceramic capacitors in the system. First, select the total amount of ceramic capacitance. This is based on the number and type of capacitor to be used. The best location for ceramic capacitors is inside the socket with 12 to 18, 1206 size being the physical limit. Other capacitors can be placed along the outer edge of the socket as well. To determine the minimum amount of ceramic capacitance required, start with a worst-case load step occurring right after a switching cycle has stopped. The ceramic capacitance then delivers the charge to the load while the load is ramping up and until the VR has responded with the next switching cycle. C X ( MAX ) ≤ (22) ⎛V where K = −1n ⎜⎜ ERR ⎝ VV 2 ⎞ ⎞ ⎟ ⎟ − 1⎟ − C Z ⎟ ⎟ ⎠ ⎠ ⎞ ⎟. ⎟ ⎠ To meet the conditions of these equations and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance (RO). If the CX(MIN) is larger than CX(MAX), the system cannot meet the VID on-the-fly specification and can require the use of a smaller inductor or more phases (and may have to increase the switching frequency to keep the output ripple the same). This example uses 18, 10 μF 1206 MLC capacitors (CZ = 180 μF). The VID on-the-fly step change is 450 mV in 230 μs with a settling error of 2.5 mV. The maximum allowable load release overshoot for this example is 50 mV, therefore, solving for the bulk capacitance yields ⎞ ⎛ ⎟ ⎜ ⎟ ⎜ 320 nH × 100 A C X ( MIN ) ≤ ⎜ − 180 μF ⎟ = 3.92 mF ⎛ 50 mV ⎞ ⎟ ⎜ ⎟ × 1.3 V ⎟⎟ ⎜⎜ 4 × ⎜⎜1.0 mΩ + ⎟ 100 A ⎠ ⎝ ⎠ ⎝ Equation 20 gives the designer a rough approximation for determining the minimum ceramic capacitance. Due to the complexity of the PCB parasitics and bulk capacitors, the actual amount of ceramic capacitance required can vary. 1 ⎡ 1 ⎛1 ⎞ Δ IO ⎤ ×⎢ × ⎜ − D⎟ − ⎥ RO ⎣ f SW ⎝ n ⎠ 2 SR ⎦ (21) ⎛ ⎛ V nKRO VV ⎜ L × × 1 + ⎜⎜ tV VID × ⎜ 2 2 nK RO VVID ⎜ L ⎝ VV ⎝ The closest standard 1% resistor value is 1.00 kΩ. C Z ( MIN ) ≥ ⎛ ⎞ ⎜ ⎟ ⎜ ⎟ L × Δ IO − CZ ⎟ C X ( MIN ) ≥ ⎜ ⎜ n × ⎛⎜ R + ΔVrl ⎞⎟ × V ⎟ ⎜ O ΔI ⎟ VID ⎜ ⎟ O ⎠ ⎝ ⎝ ⎠ (20) C X ( MAX ) ≤ The typical ceramic capacitors consist of multiple 10 μF or 22 μF capacitors. For this example, Equation 20 yields 180.8 μF, so eighteen, 10 μF ceramic capacitors suffice. 320 nH × 450 mV 4 × 5.22 × (1.0 mΩ )2 × 1.3 V × 2 ⎛ ⎞ ⎛ 230 μs × 1.3 V × 4 × 5.2 × 1.0 mΩ ⎞ ⎜ ⎟ ⎜ ⎟ + 1 − 1 ⎜ ⎟ − 180 μF = 43.0 mF ⎜ ⎟ 450 mV × 320 nH ⎜ ⎟ ⎝ ⎠ ⎝ ⎠ Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when the user considers the VID on-thefly voltage stepping of the output (voltage step VV in time tV with error of VERR). where K = 5.2. Rev. A | Page 24 of 32 ADP3198 Using 10, 560 μF Al-Poly capacitors with a typical ESR of 6 mΩ each yields CX = 5.6 mF with an RX = 0.6 mΩ. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using LX ≤ CZ × RO 2 × Q 2 L X ≤ 180 μF × (1 mΩ )2 × (23) 4 = 240 pH 3 where Q2 is limited to 4/3 to ensure a critically damped system. In this example, LX is approximately 240 pH for the 10, Al-Poly capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors needs to be increased, or lower ESL bulks need to be used if there is excessive undershoot during a load transient. For this multimode control technique, all ceramic designs can be used providing the conditions of Equation 20 through Equation 23 are satisfied. POWER MOSFETS For this example, the N-channel power MOSFETs have been selected for one high-side switch and two low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3110A) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With VGATE ~10 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are recommended. The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3198, currents are balanced between phases, thus, the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, Equation 24 shows the total power that is dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO): PSF ⎡⎛ I = (1 − D ) × ⎢⎜⎜ O ⎢⎣⎝ nSF 2 ⎞ 1 ⎛ n IR ⎟ + ×⎜ ⎟ 12 ⎜⎝ n SF ⎠ ⎞ ⎟ ⎟ ⎠ 2 ⎤ ⎥ × R DS (SF ) ⎥⎦ (24) Knowing the maximum output current being designed for and the maximum allowed power dissipation, the user can find the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an ambient temperature of 50°C, a safe limit for PSF is 1 W to 1.5 W at 120°C junction temperature. Thus, for this example (119 A maximum), RDS(SF) (per MOSFET) < 7.5 mΩ. This RDS(SF) is also at a junction temperature of about 120°C. As a result, users need to account for this when making this selection. This example uses two lower-side MOSFETs at 4.8 mΩ, each at 120°C. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recommended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3110A). The output impedance of the driver is approximately 2 Ω, and the typical MOSFET input gate resistances are about 1 Ω to 2 Ω. Therefore, a total gate capacitance of less than 6000 pF should be adhered to. Because two MOSFETs are in parallel, the input capacitance for each synchronous MOSFET should be limited to 3000 pF. The high-side (main) MOSFET has to be able to handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off, and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, Equation 25 provides an approximate value for the switching loss per main MOSFET, where nMF is the total number of main MOSFETs. PS ( MF ) = 2 × f SW × VCC × I O n MF × RG × n MF × C ISS n (25) where RG is the total gate resistance (2 Ω for the ADP3110A and about 1 Ω for typical high speed switching MOSFETs, making RG = 3 Ω), and CISS is the input capacitance of the main MOSFET. Adding more main MOSFETs (nMF) does not help the switching loss per MOSFET because the additional gate capacitance slows switching. Use lower gate capacitance devices to reduce switching loss. The conduction loss of the main MOSFET is given by the following, where RDS(MF) is the on resistance of the MOSFET: ⎡⎛ I PC ( MF ) = D × ⎢⎜⎜ O ⎢⎣⎝ n MF 2 ⎞ 1 ⎛ n × IR ⎟ + ×⎜ ⎟ ⎜ n 12 ⎠ ⎝ MF ⎞ ⎟ ⎟ ⎠ 2 ⎤ ⎥ × R DS ( MF ) ⎥⎦ (26) Typically, for main MOSFETs, the highest speed (low CISS) device is preferred, but these usually have higher on resistance. Select a device that meets the total power dissipation (about 1.5 W for a single D-PAK) when combining the switching and conduction losses. For this example, an NTD40N03L is selected as the main MOSFET (eight total; nMF = 8), with CISS = 584 pF (maximum) and RDS(MF) = 19 mΩ (maximum at TJ = 120°C). An NTD110N02L is selected as the synchronous MOSFET (eight total; nSF = 8), with CISS = 2710 pF (maximum) and RDS(SF) = 4.8 mΩ (maximum at TJ = 120°C). The synchronous MOSFET CISS is less than 3000 pF, satisfying this requirement. Rev. A | Page 25 of 32 ADP3198 Solving for the power dissipation per MOSFET at IO = 119 A and IR = 11 A yields 958 mW for each synchronous MOSFET and 872 mW for each main MOSFET. A guideline to follow is to limit the MOSFET power dissipation to 1 W. The values calculated in Equation 25 and Equation 26 comply with this guideline. Finally, consider the power dissipation in the driver for each phase. This is best expressed as QG for the MOSFETs and is given by Equation 27, where QGMF is the total gate charge for each main MOSFET and QGSF is the total gate charge for each synchronous MOSFET. The factor of 3 in the denominator of Equation 28 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance. COMP PIN RAMP A ramp signal on the COMP pin is due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input: VRT = ⎡f ⎤ PDRV = ⎢ SW × (n MF × QGMF + nSF × QGSF ) + I CC ⎥ × VCC (27) ⎣⎢ 2 × n ⎦⎥ Also shown is the standby dissipation factor (ICC × VCC) of the driver. For the ADP3110A, the maximum dissipation should be less than 400 mW. In this example, with ICC = 7 mA, QGMF = 5.8 nC, and QGSF = 48 nC, there is 297 mW in each driver, which is below the 400 mW dissipation limit. See the ADP3110A data sheet for more details. The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. Equation 28 is used for determining the optimum value. AR × L To select the current-limit setpoint, first find the resistor value for RLIM. The current-limit threshold for the ADP3198 is set with a constant current source flowing out of the ILIMIT pin, which sets up a voltage (VLIM) across RLIM with a gain of 82.6 mV/V (ALIM). Thus, increasing RLIM now increases the current limit. RLIM can be found using 3 × A D × R DS × C R 0.2 × 320 nH 3 × 5 × 2.4 mΩ × 5 pF = 356 kΩ R LIM = AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain. RDS is the total low-side MOSFET on resistance. CR is the internal ramp capacitor value. D MAX = D × A R × (1 − D ) × VVID R R × C R × f SW I PHMAX ≅ (29) 0.2 × (1 − 0.108 ) × 1.3 V 357 kΩ × 5 pF × 330 kHz A LIM × I ILIMIT = I LIM × RCSA × R REF 82.6 mV (31) The per-phase initial duty cycle limit and peak current during a load step are determined by The internal ramp voltage magnitude can be calculated by using VR = VCL Here, ILIM is the peak average current limit for the supply output. The peak average current is the dc current limit plus the output ripple current. In this example, choosing a dc current limit of 159 A and having a ripple current of 11 A gives an ILIM of 170 A. This results in an RLIM = 205.8 kΩ, for which 205 kΩ is chosen as the nearest 1% value. where: VR = (30) In this example, the overall ramp signal is 0.46 V. However, if the ramp size is smaller than 0.5 V, increase the ramp size to be at least 0.5 V by decreasing the ramp resistor for noise immunity. Because there is only 0.46 V initially, a ramp resistor value of 332 kΩ is chosen for this example, yielding an overall ramp of 0.51 V. (28) RR = ⎞ ⎟ ⎟ ⎠ CURRENT-LIMIT SETPOINT RAMP RESISTOR SELECTION RR = VR ⎛ 2 × (1 − n × D ) ⎜1 − ⎜ n× f ×C × R X SW O ⎝ = 394 mV The size of the internal ramp can be made larger or smaller. If it is made larger, stability and noise rejection improves, but transient degrades. Likewise, if the ramp is made smaller, transient response improves at the sacrifice of noise rejection and stability. VCOMP ( MAX ) − V BIAS V RT D MAX (VIN − VVID ) × f SW L (32) (33) For the ADP3198, the maximum COMP voltage (VCOMP(MAX)) is 4.0 V and the COMP pin bias voltage (VBIAS) is 1.1 V. In this example, the maximum duty cycle is 0.61 and the peak current is 62 A. Rev. A | Page 26 of 32 ADP3198 The limit of the peak per-phase current described earlier during the secondary current limit is determined by VCOMP (CLAMPED ) − V BIAS (34) I PHLIM ≅ A D × R DS ( MAX ) For the ADP3198, the current balancing amplifier gain (AD) is 5 and the clamped COMP pin voltage is 2 V. Using an RDS(MAX) of 2.8 mΩ (low-side on resistance at 150°C) results in a per-phase peak current limit of 64 A. This current level can be reached only with an absolute short at the output, and the current-limit latch-off function shuts down the regulator before overheating can occur. FEEDBACK LOOP COMPENSATION DESIGN Optimized compensation of the ADP3198 allows the best possible response of the regulator output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion to the load current at any load current slew rate. This ensures optimal positioning and minimizes the output decoupling. Because of the multimode feedback structure of the ADP3198, the feedback compensation must be set to make the converter output impedance work in parallel with the output decoupling to make the load look entirely resistive. Compensation is needed for several poles and zeros created by the output inductor and the decoupling capacitors (output filter). A type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equation 35 to Equation 39 are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Tuning the ADP3198 section). First, compute the time constants for all the poles and zeros in the system using Equation 35 to Equation 39. R E = n × R O + A D × R DS + R L × V RT R E = 4 × 1 mΩ + 5 × 2.4 mΩ + TA = C X × (RO − R' ) + VVID + 2 × L × (1 − n × D ) × V RT n × C X × R O × VVID 1.4 mΩ × 0.51 V 1.3 V + 2 × 320 nH × (1 − 0.432 ) × 0.51 V 4 × 5.6 mF × 1 mΩ × 1.3 V = 22.9 mΩ 240 pH 1 mΩ − 0.5 mΩ L X RO − R' × = 5.6 mF × (1 mΩ − 0.5 mΩ ) + × = 3.00 μs RO RX 1 mΩ 0.6 mΩ TB = (R X + R' − RO ) × C X = (0.6 mΩ + 0.5 mΩ − 1 mΩ ) × 5.6 mF = 560 ns C X × C Z × RO2 C X × (RO − R' ) + C Z × RO = 5.6 mF × 180 μF × (1 mΩ )2 5.6 mF × (1 mΩ − 0.5 mΩ ) + 180 μF × 1 mΩ (36) (37) ⎛ ⎛ A × RDS ⎞ 5 × 2.4 mΩ ⎞ ⎟ ⎟ 0.51 V × ⎜ 320 nH − VRT × ⎜ L − D ⎜ ⎟ ⎜ ⎟ f 2 2 330 kHz × × SW ⎝ ⎠ = 5.17 μs ⎝ ⎠= TC = VVID × RE 1.3 V × 22.9 mΩ TD = (35) (38) = 338 ns (39) where: R' is the PCB resistance from the bulk capacitors to the ceramics. RDS is the total low-side MOSFET on resistance per phase. In this example, AD is 5, VRT equals 0.51 V, R' is approximately 0.5 mΩ (assuming a 4-layer, 1 ounce motherboard), and LX is 240 pH for the 10 Al-Poly capacitors. Rev. A | Page 27 of 32 ADP3198 CIN SELECTION AND INPUT CURRENT di/dt REDUCTION The compensation values can then be solved using CA = n × R O × TA RE × RB = 4 × 1 mΩ × 3.00 μs 22.9 mΩ × 1.00 kΩ = 524 pF (40) RA = 5.17 μs TC = = 9.87 kΩ C A 524 pF (41) CB = TB 560 ns = = 560 pF R B 1.00 kΩ (42) C FB = TD 338 ns = = 34.2 pF R A 9.87 kΩ (43) In continuous inductor current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n × VOUT/VIN and an amplitude of one-nth the maximum output current. To prevent large voltage transients, a low ESR input capacitor, sized for the maximum rms current, must be used. The maximum rms capacitor current is given by I CRMS = D × I O × 1 −1 N ×D (44) These are the starting values prior to tuning the design that account for layout and other parasitic effects (see the Tuning the ADP3198 section). The final values selected after tuning are I CRMS = 0.108 × 119 A × 1 − 1 = 14.7 A 4 × 0.108 The capacitor manufacturer’s ripple-current ratings are often based on only 2000 hours of life. As a result, it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors can be placed in parallel to meet size or height requirements in the design. In this example, the input capacitor bank is formed by two 2700 μF, 16 V aluminum electrolytic capacitors and eight 4.7 μF ceramic capacitors. CA = 560 pF RA = 10.0 kΩ CB = 560 pF B CFB = 27 pF Figure 13 and Figure 14 show the typical transient response using these compensation values. To reduce the input current di/dt to a level below the recommended maximum of 0.1 A/μs, an additional small inductor (L > 370 nH at 18 A) should be inserted between the converter and the supply bus. This inductor also acts as a filter between the converter and the primary power source. 1 THERMAL MONITOR DESIGN CH1 50mV M 10µs A CH1 –36mV 06094-012 A thermistor is used on the TTSENSE input of the ADP3198 for monitoring the temperature of the VR. A constant current of 123 μA is sourced out of this pin and runs through a thermistor network such as the one shown in Figure 15. ADP3198 Figure 13. Typical Transient Response for Design Example Load Step OPTIONAL TEMPERATURE ADJUST RESISTOR 8 VRFAN 9 VRHOT 10 TTSENSE RTTSENSE 06094-014 PLACE THERMISTOR NEAR CLOSEST PHASE 1 0.1µF Figure 15. VR Thermal Monitor Circuit M 10µs A CH1 –36mV 06094-013 CH1 50mV A voltage is generated from this current through the thermistor and sensed inside the IC. When the voltage reaches 1.105 V, the VRFAN output gets set. When the voltage reaches 0.81 V, the VRHOT gets set. This corresponds to RTTSENSE values of 8.98 kΩ for VRFAN and 6.58 kΩ for VRHOT. Figure 14. Typical Transient Response for Design Example Load Release Rev. A | Page 28 of 32 ADP3198 These values correspond to a thermistor temperature of ~100°C and ~110°C when using the same type of 100 kΩ NTC thermistor used in the current sense amplifier. where: VIN(MAX) is the maximum voltage from the 12 V input supply (if the 12 V input supply is 12 V ± 5%, VIN(MAX) = 12.6 V; if the 12 V input supply is 12 V ± 10%, VIN(MAX) = 13.2 V). VCC(MIN) is the minimum VCC voltage of the ADP3198. This is specified as 4.75 V. RSHUNT is the shunt resistor value. An additional fixed resistor in parallel with the thermistor allows tuning of the trip point temperatures to match the hottest temperature in the VR, when the thermistor itself is directly sensing a proportionately lower temperature. Setting this resistor value is best accomplished with a variable resistor during thermal validation and then fixing this value for the final design. The CECC standard specification for power rating in surface mount resistors is: 0603 = 0.1 W, 0805 = 0.125 W, 1206 = 0.25 W. Additionally, a 0.1 μF capacitor should be used for filtering noise. TUNING THE ADP3198 SHUNT RESISTOR DESIGN The ADP3198 uses a shunt to generate 5 V from the 12 V supply range. A trade-off can be made between the power dissipated in the shunt resistor and the UVLO threshold. Figure 16 shows the typical resistor value needed to realize certain UVLO voltages. It also gives the maximum power dissipated in the shunt resistor for these UVLO voltages. 550 0.50 500 0.45 450 0.40 Hook up the dc load to the circuit, turn it on, and verify its operation. Also, check for jitter at no load and full load. 3. Measure the output voltage at no load (VNL). Verify that it is within tolerance. 4. Measure the output voltage at full load cold (VFLCOLD). Let the board sit for ~10 minutes at full load, and then measure the output (VFLHOT). If there is a change of more than a few mV, adjust RCS1 and RCS2 using Equation 46 and Equation 48. 350 0.30 300 0.25 250 0.20 200 0.15 8.0 8.5 9.0 9.5 10.0 10.5 PSHUNT (W) 0.35 7.5 2. RSHUNT 400 150 7.0 Build a circuit based on the compensation values computed from the design spreadsheet. DC Load Line Setting 0.10 11.0 R CS2 ( NEW ) = R CS2 (OLD ) × 06094-019 RSHUNT (Ω) PSHUNT 1. VIN (UVLO) Figure 16. Typical Shunt Resistor Value and Power Dissipation for Different UVLO Voltage (V IN ( MAX ) − VCC ( MIN ) ) Repeat Step 4 until the cold and hot voltage measurements remain the same. 6. Measure the output voltage from no load to full load using 5 A steps. Compute the load line slope for each change, and then average to get the overall load line slope (ROMEAS). 7. If ROMEAS is off from RO by more than 0.05 mΩ, use Equation 47 to adjust the RPH values. 2 R PH ( NEW ) = R PH (OLD ) × (45) R SHUNT (46) 5. The maximum power dissipated is calculated using Equation 45. PMAX = V NL − V FLCOLD V NL − V FLHOT R OMEAS RO (47) 8. Repeat Step 6 and Step 7 to check the load line. Repeat adjustments if necessary. 9. When the dc load line adjustment is complete, do not change RPH, RCS1, RCS2, or RTH for the remainder of the procedure. 10. Measure the output ripple at no load and full load with a scope, and make sure it is within specifications. RCS1( NEW ) = ( 1 RCS1(OLD ) + RTH (25° C ) ) ( RCS1(OLD ) × RTH (25° C ) + RCS1(OLD ) − RCS2 ( NEW ) × RCS1(OLD ) − RTH (25° C ) Rev. A | Page 29 of 32 )− R 1 TH ( 25° C ) (48) ADP3198 AC Load Line Setting 11. Remove the dc load from the circuit and hook up the dynamic load. VDROOP 12. Hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 μs/div. 13. Set the dynamic load for a transient step of about 40 A at 1 kHz with 50% duty cycle. VTRAN1 VTRAN2 06094-016 14. Measure the output waveform (use dc offset on scope to see the waveform). Try to use a vertical scale of 100 mV/div or finer. This waveform should look similar to Figure 17. Figure 18. Transient Setting Waveform 19. If both overshoots are larger than desired, try making the adjustments using the following suggestions: VACDRP • Make the ramp resistor larger by 25% (RRAMP) • For VTRAN1, increase CB or increase the switching frequency • For VTRAN2, increase RA and decrease CA by 25% VDCDRP 06094-015 If these adjustments do not change the response, the design is limited by the output decoupling. Check the output response every time a change is made, and check the switching nodes to ensure that the response is still stable. Figure 17. AC Load Line Waveform 15. Use the horizontal cursors to measure VACDRP and VDCDRP as shown in Figure 17. Do not measure the undershoot or overshoot that happens immediately after this step. 16. If VACDRP and VDCDRP are different by more than a few millivolts, use Equation 49 to adjust CCS. Users may need to parallel different values to get the right one because limited standard capacitor values are available. It is a good idea to have locations for two capacitors in the layout for this. C CS ( NEW ) = C CS (OLD ) × V ACDRP V DCDRP B 20. For load release (see Figure 19), if VTRANREL is larger than the allowed overshoot, there is not enough output capacitance. Either more capacitance is needed, or the inductor values need to be made smaller. When changing inductors, start the design again using a spreadsheet and this tuning procedure. (49) VTRANREL VDROOP 06094-017 17. Repeat Step 11 to Step 13 and repeat the adjustments, if necessary. Once complete, do not change CCS for the remainder of the procedure. Set the dynamic load step to maximum step size. Do not use a step size larger than needed. Verify that the output waveform is square, which means that VACDRP and VDCDRP are equal. Initial Transient Setting Figure 19. Transient Setting Waveform 18. With the dynamic load still set at the maximum step size, expand the scope time scale to either 2 μs/div or 5 μs/div. The waveform can have two overshoots and one minor undershoot (see Figure 18). Here, VDROOP is the final desired value. Because the ADP3198 turns off all of the phases (switches inductors to ground), no ripple voltage is present during load release. Therefore, the user does not have to add headroom for ripple. This allows load release VTRANREL to be larger than VTRAN1 by the amount of ripple, and still meet specifications. Rev. A | Page 30 of 32 ADP3198 If VTRAN1 and VTRANREL are less than the desired final droop, this implies that capacitors can be removed. When removing capacitors, also check the output ripple voltage to make sure it is still within specifications. LAYOUT AND COMPONENT PLACEMENT The following guidelines are recommended for optimal performance of a switching regulator in a PC system. General Recommendations For good results, a PCB with at least four layers is recommended. This provides the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 mΩ at room temperature. Whenever high currents must be routed between PCB layers, use vias liberally to create several parallel current paths, so the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3198) must cross through power circuitry, it is best to interpose a signal ground plane between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3198 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing into it. The components around the ADP3198 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB pin and CSSUM pin. The output capacitors should be connected as close as possible to the load (or connector), for example, a microprocessor core, that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop (described in the Power Circuitry Recommendations section). Power Circuitry Recommendations The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system and noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing; and it accommodates the high current demand with minimal voltage loss. When a power dissipating component, for example, a power MOSFET, is soldered to a PCB, it is recommended to liberally use the vias, both directly on the mounting pad and immediately surrounding it. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heatsink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation in the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. Signal Circuitry Recommendations The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB trace and FBRTN trace should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller. Rev. A | Page 31 of 32 ADP3198 OUTLINE DIMENSIONS 6.00 BSC SQ 0.60 MAX 0.60 MAX PIN 1 INDICATOR TOP VIEW 0.50 BSC 5.75 BCS SQ 0.50 0.40 0.30 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 31 30 40 1 4.25 4.10 SQ 3.95 EXPOSED PAD (BOTTOM VIEW) 21 20 10 11 0.25 MIN 4.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 20. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40) Dimensions shown in millimeters ORDERING GUIDE Model ADP3198JCPZ-RL 1 1 Temperature Range 0°C to 85°C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Package Option CP-40 Ordering Quantity 2,500 Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06094-0-8/06(A) T T Rev. A | Page 32 of 32