AT27C512R Features • • • • • • • • • Fast Read Access Time - 45 ns Low Power CMOS Operation 100 µA max. Standby 20 mA max. Active at 5 MHz JEDEC Standard Packages 28-Lead 600-mil PDIP 32-Lead PLCC 28-Lead TSOP and SOIC 5V ± 10% Supply High Reliability CMOS Technology 2,000V ESD Protection 200 mA Latchup Immunity Rapid Programming Algorithm - 100 µs/byte (typical) CMOS and TTL Compatible Inputs and Outputs Integrated Product Identification Code Commercial and Industrial Temperature Ranges 512K (64K x 8) OTP CMOS EPROM Description The AT27C512R is a low-power, high performance 524,288 bit one-time programmable read only memory (OTP EPROM) organized 64K by 8 bits. It requires only one 5V power supply in normal read mode operation. Any byte can be accessed in less than 45 ns, eliminating the need for speed reducing WAIT states on high performance microprocessor systems. Atmel’s scaled CMOS technology provides high speed, lower active power consumption, and significantly faster programming. Power consumption is typically only 8 mA in Active Mode and less than 10 µA in Standby. (continued) Pin Configurations Pin Name Function A0 - A15 Addresses O0 - O7 Outputs CE Chip Enable OE /VPP Output Enable/VPP NC No Connect PDIP, SOIC Top View AT27C512R PLCC Top View TSOP Top View Type 1 Note: PLCC Package Pins 1 and 17 are DON’T CONNECT. 0015H 3-135 Description (Continued) System Considerations The AT27C512R is available in a choice of industry standard JEDEC-approved one-time programmable (OTP) plastic PDIP, PLCC, SOIC, and TSOP packages. All devices feature two-line control (CE, OE) to give designers the flexibility to prevent bus contention. Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed data sheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. With 64K byte storage capability, the AT27C512R allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. Atmel’s 27C512R has additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry standard programming equipment to select the proper programming algorithms and voltages. 3-136 AT27C512R AT27C512R Absolute Maximum Ratings* Block Diagram Temperature Under Bias ................ -55°C to +125°C Storage Temperature...................... -65°C to +150°C Voltage on Any Pin with Respect to Ground......................... -2.0V to +7.0V (1) Voltage on A9 with Respect to Ground ...................... -2.0V to +14.0V (1) VPP Supply Voltage with Respect to Ground....................... -2.0V to +14.0V (1) *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V dc which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V dc which may overshoot to +7.0V for pulses of less than 20 ns. Operating Modes Mode \ Pin CE OE/VPP Ai Read VIL VIL Ai Output Disable Standby Rapid Program (2) PGM Inhibit Outputs DOUT (1) VIL VIH X VIH X (1) X High Z VIL VPP Ai DIN VIH VPP X (1) High Z High Z (3) Product Identification (4) VIL Notes: 1. X can be VIL or VIH. 2. Refer to Programming Characteristics. 3. VH = 12.0 ± 0.5V. VIL A9 = VH A0 = VIH or VIL A1 - A15 = VIL Identification Code 4. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte. 3-137 DC and AC Operating Conditions for Read Operation AT27C512R -55 -70 -90 -12 -15 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% -45 Operating Com. 0°C - 70°C Temp.(Case) Ind. -40°C - 85°C 5V ± 10% VCC Supply DC and Operating Characteristics for Read Operation Symbol Parameter Condition ILI Input Load Current ILO Min Max Units VIN = 0V to VCC ±1 µA Output Leakage Current VOUT = 0V to VCC ±5 µA ISB VCC (1) Standby Current ISB1 (CMOS), CE = VCC ± 0.3V 100 µA ISB2 (TTL), CE = 2.0 to VCC + 0.5V 1 mA ICC VCC Active Current f = 5 MHz, IOUT = 0 mA, CE = VIL 20 mA VIL Input Low Voltage -0.6 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V VOL Output Low Voltage IOL = 2.1 mA 0.4 V VOH Output High Voltage IOH = -400 µA 2.4 V Note: 1. VCC must be applied simultaneously or before OE/VPP, and removed simultaneously or after OE/VPP. AC Characteristics for Read Operation AT27C512R -45 -55 -70 -90 Max Units 120 150 ns 90 120 150 ns 30 35 35 40 ns 25 25 30 35 ns Symbol Parameter Condition Address to tACC (3) Output Delay CE = OE/VPP = VIL 45 55 70 90 CE to Output Delay OE/VPP = VIL 45 55 70 20 25 20 20 tCE (2) PP to Output tOE (2, 3) OE/V Delay Min CE = VIL PP or CE High to tDF (4, 5) OE/V Output Float, whichever occurred first Max tOH Output Hold from Address, CE or OE/VPP, whichever occurred first Notes: 2, 3, 4, 5. - see AC Waveforms for Read Operation. 3-138 AT27C512R 7 Min 7 Max Min 7 -15 -12 Max Min 0 Max Min 0 Max Min 0 ns AT27C512R AC Waveforms for Read Operation (1) Notes: 1. Timing measurement reference level is 1.5V for -45 and -55 devices. Input AC drive levels are VIL = 0.0V and VIH = 3.0V. Timing measurement reference levels for all other speed grades are VOL = 0.8V and VOH = 2.0V. Input AC drive levels are VIL = 0.45V and VIH = 2.4V. 2. OE/VPP may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE . 3. OE/VPP may be delayed up to tACC - tOE after the address is valid without impact on tACC. 4. This parameter is only sampled and is not 100% tested. 5. Output float is defined as the point when data is no longer driven. Input Test Waveforms and Measurement Levels Output Test Load For -45 and -55 devices only: tR, tF < 5 ns (10% to 90%) For -70, -90, -12, -15, and -20 devices: Note: CL = 100 pF including jig capacitance, except for the -45 and -55 devices, where CL = 30 pF. tR, tF < 20 ns (10% to 90%) Pin Capacitance (f = 1 MHz T = 25°C) CIN COUT Note: (1) Typ Max Units Conditions 4 6 pF VIN = 0V 8 12 pF VOUT = 0V 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 3-139 Programming Waveforms Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH. 2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer. DC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, OE/VPP = 13.0 ± 0.25V Symbol Parameter Test Conditions ILI Input Load Current VIN = VIL,VIH VIL Input Low Level VIH Input High Level VOL Output Low Voltage IOL = 2.1 mA VOH Output High Voltage IOH = -400 µA ICC2 VCC Supply Current (Program and Verify) IPP2 OE/VPP Current VID A9 Product Identification Voltage 3-140 AT27C512R Limits Max Units ±10 µA -0.6 0.8 V 2.0 VCC + 1 V 0.4 V Min 2.4 CE = VIL 11.5 V 25 mA 25 mA 12.5 V AT27C512R AC Programming Characteristics Rapid Programming Algorithm TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, OE/VPP = 13.0 ± 0.25V A 100 µs CE pulse width is used to program. The address is set to the first location. VCC is raised to 6.5V and OE/VPP is raised to 13.0V. Each address is first programmed with one 100 µs CE pulse without verification. Then a verification/reprogramming loop is executed for each address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is considered failed. After the byte verifies properly, the next address is selected until all have been checked. OE/VPP is then lowered to VIL and VCC to 5.0V. All bytes are read again and compared with the original data to determine if the device passes or fails. Test Condtions* (1) Symbol Parameter Limits Min Units Max Address Setup Time 2 µs tOES OE/VPP Setup Time 2 µs tOEH OE/VPP Hold Time 2 µs tDS Data Setup Time 2 µs tAH Address Hold Time 0 µs tDH Data Hold Time 2 µs tDFP CE High to Output Float Delay (2) 0 tAS tVCS VCC Setup Time tPW 130 µs 2 CE Program Pulse Width (3) ns 95 (2) 105 µs 1 µs tDV Data Valid from CE tVR OE/VPP Recovery Time 2 µs tPRT OE/VPP Pulse Rise Time During Programming 50 ns *AC Conditions of Test: Input Rise and Fall Times (10% to 90%).............. 20 ns Input Pulse Levels....................................0.45V to 2.4V Input Timing Reference Level....................0.8V to 2.0V Output Timing Reference Level.................0.8V to 2.0V Notes: 1. VCC must be applied simultaneously or before OE/VPP and removed simultaneously or after OE/VPP. 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven — see timing diagram. 3. Program Pulse width tolerance is 100 µsec ± 5%. Atmel’s 27C512R Integrated Product Identification Code Pins Codes Manufacturer Device Type A0 O7 O6 O5 O4 O3 O2 O1 O0 0 1 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 Hex Data 1E 0D 3-141 Ordering Information ICC (mA) tACC (ns) Active Standby 45 20 55 70 90 120 150 Ordering Code Package Operation Range 0.1 AT27C512R-45JC AT27C512R-45PC AT27C512R-45RC AT27C512R-45TC 32J 28P6 28R 28T Commercial (0°C to 70°C) 20 0.1 AT27C512R-45JI AT27C512R-45PI AT27C512R-45RI AT27C512R-45TI 32J 28P6 28R 28T Industrial (-40°C to 85°C) 20 0.1 AT27C512R-55JC AT27C512R-55PC AT27C512R-55RC AT27C512R-55TC 32J 28P6 28R 28T Commercial (0°C to 70°C) 20 0.1 AT27C512R-55JI AT27C512R-55PI AT27C512R-55RI AT27C512R-55TI 32J 28P6 28R 28T Industrial (-40°C to 85°C) 20 0.1 AT27C512R-70JC AT27C512R-70PC AT27C512R-70RC AT27C512R-70TC 32J 28P6 28R 28T Commercial (0°C to 70°C) 20 0.1 AT27C512R-70JI AT27C512R-70PI AT27C512R-70RI AT27C512R-70TI 32J 28P6 28R 28T Industrial (-40°C to 85°C) 20 0.1 AT27C512R-90JC AT27C512R-90PC AT27C512R-90RC AT27C512R-90TC 32J 28P6 28R 28T Commercial (0°C to 70°C) 20 0.1 AT27C512R-90JI AT27C512R-90PI AT27C512R-90RI AT27C512R-90TI 32J 28P6 28R 28T Industrial (-40°C to 85°C) 20 0.1 AT27C512R-12JC AT27C512R-12PC AT27C512R-12RC AT27C512R-12TC 32J 28P6 28R 28T Commercial (0°C to 70°C) 20 0.1 AT27C512R-12JI AT27C512R-12PI AT27C512R-12RI AT27C512R-12TI 32J 28P6 28R 28T Industrial (-40°C to 85°C) 20 0.1 AT27C512R-15JC AT27C512R-15PC AT27C512R-15RC AT27C512R-15TC 32J 28P6 28R 28T Commercial (0°C to 70°C) (continued) 3-142 AT27C512R AT27C512R Ordering Information (Continued) ICC (mA) tACC (ns) Active Standby 150 20 0.1 Ordering Code Package AT27C512R-15JI AT27C512R-15PI AT27C512R-15RI AT27C512R-15TI 32J 28P6 28R 28T Operation Range Industrial (-40°C to 85°C) Package Type 32J 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 28P6 28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28R 28 Lead, 0.330" Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28 Lead, Thin Small Outline Package (TSOP) 3-143