Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 133 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 128K Bytes of In-System Self-programmable Flash program memory – 4K Bytes EEPROM – 4K Bytes Internal SRAM – Write/Erase cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – Up to 64K Bytes Optional External Memory Space – Programming Lock for Software Security – SPI Interface for In-System Programming JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and Capture Mode – Real Time Counter with Separate Oscillator – Two 8-bit PWM Channels – 6 PWM Channels with Programmable Resolution from 2 to 16 Bits – Output Compare Modulator – 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x – Byte-oriented Two-wire Serial Interface – Dual Programmable Serial USARTs – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby – Software Selectable Clock Frequency – ATmega103 Compatibility Mode Selected by a Fuse – Global Pull-up Disable I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF Operating Voltages – 2.7 - 5.5V Speed Grades – 0 - 16 MHz 8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATmega128A Summary Rev. 8151GS–AVR–07/10 ATmega128A 1. Pin Configurations Pinout ATmega128A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2(ALE) PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) PG1(RD) PG0(WR) (OC2/OC1C) PB7 TOSC2/PG3 TOSC1/PG4 RESET VCC GND XTAL2 XTAL1 (SCL/INT0) PD0 (SDA/INT1) PD1 (RXD1/INT2) PD2 (TXD1/INT3) PD3 (ICP1) PD4 (XCK1) PD5 (T1) PD6 (T2) PD7 PEN RXD0/(PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (ICP3/INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) Figure 1-1. Note: The Pinout figure applies to both TQFP and MLF packages. The bottom pad under the QFN/MLF package should be soldered to ground. 2. Overview The ATmega128A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega128A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 19 8151GS–AVR–07/10 ATmega128A Block Diagram PF0 - PF7 PA0 - PA7 PC0 - PC7 RESET Block Diagram XTAL2 Figure 2-1. XTAL1 2.1 VCC GND PORTA DRIVERS PORTF DRIVERS DATA DIR. REG. PORTF DATA REGISTER PORTF PORTC DRIVERS DATA DIR. REG. PORTA DATA REGISTER PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC CALIB. OSC INTERNAL OSCILLATOR ADC AGND AREF OSCILLATOR PROGRAM COUNTER STACK POINTER WATCHDOG TIMER ON-CHIP DEBUG PROGRAM FLASH SRAM MCU CONTROL REGISTER BOUNDARYSCAN INSTRUCTION REGISTER JTAG TAP OSCILLATOR TIMING AND CONTROL TIMER/ COUNTERS GENERAL PURPOSE REGISTERS X PEN PROGRAMMING LOGIC INSTRUCTION DECODER CONTROL LINES Z INTERRUPT UNIT ALU EEPROM Y STATUS REGISTER SPI + - ANALOG COMPARATOR USART0 DATA REGISTER PORTE DATA DIR. REG. PORTE PORTE DRIVERS PE0 - PE7 DATA REGISTER PORTB DATA DIR. REG. PORTB PORTB DRIVERS PB0 - PB7 USART1 DATA REGISTER PORTD TWO-WIRE SERIAL INTERFACE DATA DIR. REG. PORTD DATA REG. PORTG DATA DIR. REG. PORTG PORTD DRIVERS PORTG DRIVERS PD0 - PD7 PG0 - PG4 19 8151GS–AVR–07/10 ATmega128A The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega128A provides the following features: 128K bytes of In-System Programmable Flash with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128A is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega128A AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 ATmega103 and ATmega128A Compatibility The ATmega128A is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O locations present in ATmega103 have the same location in ATmega128A. Most additional I/O locations are added in an Extended I/O space starting from $60 to $FF, (i.e., in the ATmega103 internal RAM space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the increased number of interrupt vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility mode can be selected by programming the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the Extended Interrupt vectors are removed. 19 8151GS–AVR–07/10 ATmega128A The ATmega128A is 100% pin compatible with ATmega103, and can replace the ATmega103 on current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega128A” describes what the user should be aware of replacing the ATmega103 by an ATmega128A. 2.2.1 ATmega103 Compatibility Mode By programming the M103C fuse, the ATmega128 will be compatible with the ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. However, some new features in ATmega128 are not available in this compatibility mode, these features are listed below: • One USART instead of two, Asynchronous mode only. Only the eight least significant bits of the Baud Rate Register is available. • One 16 bits Timer/Counter with two compare registers instead of two 16-bit Timer/Counters with three compare registers. • Two-wire serial interface is not supported. • Port C is output only. • Port G serves alternate functions only (not a general I/O port). • Port F serves as digital input only in addition to analog input to the ADC. • Boot Loader capabilities is not supported. • It is not possible to adjust the frequency of the internal calibrated RC Oscillator. • The External Memory Interface can not release any Address pins for general I/O, neither configure different wait-states to different External Memory Address sections. • In addition, there are some other minor differences to make it more compatible to ATmega103: • Only EXTRF and PORF exists in MCUCSR. • Timed sequence not required for Watchdog Time-out change. • External Interrupt pins 3 - 0 serve as level interrupt only. • USART has no FIFO buffer, so data overrun comes earlier. Unused I/O bits in ATmega103 should be written to 0 to ensure same operation in ATmega128. 2.3 2.3.1 Pin Descriptions VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7:PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega128A as listed on page 73. 19 8151GS–AVR–07/10 ATmega128A 2.3.4 Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega128A as listed on page 74. 2.3.5 Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega128A as listed on page 76. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated when a reset condition becomes active. Note: 2.3.6 The ATmega128A is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is disabled. Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega128A as listed on page 78. 2.3.7 Port E (PE7:PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega128A as listed on page 81. 2.3.8 Port F (PF7:PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the 19 8151GS–AVR–07/10 ATmega128A JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. The TDO pin is tri-stated unless TAP states that shift out data are entered. Port F also serves the functions of the JTAG interface. In ATmega103 compatibility mode, Port F is an input Port only. 2.3.9 Port G (PG4:PG0) Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features. The port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. In ATmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as input to the 32 kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. PG3 and PG4 are oscillator pins. 2.3.10 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in “System and Reset Characteristics” on page 324. Shorter pulses are not guaranteed to generate a reset. 2.3.11 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.12 XTAL2 Output from the inverting Oscillator amplifier. 2.3.13 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.14 AREF AREF is the analog reference pin for the A/D Converter. 2.3.15 PEN PEN is a programming enable pin for the SPI Serial Programming mode, and is internally pulled high . By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode. PEN has no function during normal operation. 19 8151GS–AVR–07/10 ATmega128A 3. Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. ATmega128A/L rev. A - M characterization is found in the ATmega128A Appendix B. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 19 8151GS–AVR–07/10 ATmega128A 5. Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ($FF) Reserved – – – – – – – – : ($9E) Reserved – – – – – – – – Reserved – – – – – – – – ($9D) UCSR1C – UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 195 ($9C) UDR1 ($9B) UCSR1A RXC1 TXC1 UDRE1 ($9A) UCSR1B RXCIE1 TXCIE1 UDRIE1 ($99) UBRR1L ($98) ($97) UBRR1H – – – – Reserved – – – – ($96) Reserved – – – – – – – – ($95) ($94) UCSR0C – UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 Reserved – – – – – – – – ($93) Reserved – – – – – – – – ($92) Reserved – – – – – – – – ($91) Reserved – – – – – – – – ($90) ($8F) UBRR0H – – – – Reserved – – – – – – – – USART1 I/O Data Register Page 192 FE1 DOR1 UPE1 U2X1 MPCM1 193 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 194 USART1 Baud Rate Register Low 197 USART1 Baud Rate Register High – – – 197 – USART0 Baud Rate Register High 195 197 ($8E) Reserved – – – – – – – – ($8D) Reserved – – – – – – – – ($8C) TCCR3C FOC3A FOC3B FOC3C – – – – – 138 ($8B) TCCR3A COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 134 ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 137 ($8A) TCCR3B ($89) TCNT3H Timer/Counter3 – Counter Register High Byte 139 ($88) TCNT3L Timer/Counter3 – Counter Register Low Byte 139 ($87) OCR3AH Timer/Counter3 – Output Compare Register A High Byte 140 ($86) OCR3AL Timer/Counter3 – Output Compare Register A Low Byte 140 ($85) OCR3BH Timer/Counter3 – Output Compare Register B High Byte 140 ($84) OCR3BL Timer/Counter3 – Output Compare Register B Low Byte 140 ($83) OCR3CH Timer/Counter3 – Output Compare Register C High Byte 140 ($82) OCR3CL Timer/Counter3 – Output Compare Register C Low Byte 140 ($81) ICR3H Timer/Counter3 – Input Capture Register High Byte 141 ($80) ($7F) ICR3L Timer/Counter3 – Input Capture Register Low Byte Reserved – – – – – – 141 – – ($7E) Reserved – – – – – – – – ($7D) ETIMSK – – TICIE3 OCIE3A OCIE3B TOIE3 OCIE3C OCIE1C 142 ($7C) ($7B) ETIFR – – ICF3 OCF3A OCF3B TOV3 OCF3C OCF1C 143 Reserved – – – – – – – – ($7A) TCCR1C FOC1A FOC1B FOC1C – – – – – ($79) OCR1CH Timer/Counter1 – Output Compare Register C High Byte 140 ($78) ($77) OCR1CL Timer/Counter1 – Output Compare Register C Low Byte 140 Reserved – – – – – – – – ($76) Reserved – – – – – – – – ($75) Reserved – – – – – – – – ($74) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 226 ($73) TWDR ($72) TWAR TWA6 TWA5 TWA4 TWS7 TWS6 TWS5 Two-wire Serial Interface Data Register 228 TWA3 TWA2 TWA1 TWA0 TWGCE 229 TWS4 TWS3 – TWPS1 TWPS0 228 ($71) TWSR ($70) TWBR Two-wire Serial Interface Bit Rate Register ($6F) ($6E) OSCCAL Oscillator Calibration Register Reserved 138 226 44 – – – – – – – ($6D) XMCRA – SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ($6C) XMCRB XMBK – – – – XMM2 XMM1 – 34 XMM0 35 ($6B) Reserved – – – – – – – – ($6A) ($69) EICRA ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 Reserved – – – – – – – – ($68) SPMCSR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN ($67) Reserved – – – – – – – – ($66) Reserved – – – – – – – – ($65) PORTG – – – PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 89 ($64) DDRG – – – DDG4 DDG3 DDG2 DDG1 DDG0 89 ($63) PING – – – PING4 PING3 PING2 PING1 PING0 89 90 289 19 8151GS–AVR–07/10 ATmega128A 5. Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ($62) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 Page 89 ($61) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 89 ($60) Reserved – – – – – – – – $3F ($5F) SREG I T H S V N Z C 10 $3E ($5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 13 $3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 13 $3C ($5C) XDIV XDIVEN XDIV6 XDIV5 XDIV4 XDIV3 XDIV2 XDIV1 XDIV0 38 $3B ($5B) RAMPZ – – – – – – – RAMPZ0 14 $3A ($5A) EICRB ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 91 $39 ($59) EIMSK INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 92 $38 ($58) EIFR INTF7 INTF6 INTF5 INTF4 INTF3 INTF INTF1 INTF0 92 $37 ($57) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 110, 141, 162 $36 ($56) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 110, 143, 162 $35 ($55) MCUCR SRE SRW10 SE SM1 SM0 SM2 IVSEL IVCE 33, 50, 63 $34 ($54) MCUCSR JTD – – JTRF WDRF BORF EXTRF PORF 56, 257 $33 ($53) TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 $32 ($52) TCNT0 $31 ($51) OCR0 $30 ($50) ASSR – – – – AS0 TCN0UB OCR0UB TCR0UB Timer/Counter0 (8 Bit) 106 109 Timer/Counter0 Output Compare Register 109 109 $2F ($4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 134 $2E ($4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 137 $2D ($4D) TCNT1H Timer/Counter1 – Counter Register High Byte $2C ($4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 139 $2B ($4B) OCR1AH Timer/Counter1 – Output Compare Register A High Byte 139 139 $2A ($4A) OCR1AL Timer/Counter1 – Output Compare Register A Low Byte 139 $29 ($49) OCR1BH Timer/Counter1 – Output Compare Register B High Byte 139 $28 ($48) OCR1BL Timer/Counter1 – Output Compare Register B Low Byte 139 $27 ($47) ICR1H Timer/Counter1 – Input Capture Register High Byte 140 $26 ($46) ICR1L $25 ($45) TCCR2 Timer/Counter1 – Input Capture Register Low Byte $24 ($44) TCNT2 Timer/Counter2 (8 Bit) $23 ($43) OCR2 Timer/Counter2 Output Compare Register $22 ($42) OCDR $21 ($41) $20 ($40) FOC2 WGM20 COM21 COM20 IDRD/OCDR7 OCDR6 OCDR5 OCDR4 WDTCR – – – SFIOR TSM – – – – – WGM21 CS22 140 CS21 CS20 159 161 162 OCDR3 OCDR2 OCDR1 WDCE WDE WDP2 WDP1 WDP0 57 – ACME PUD PSR0 PSR321 86, 111, 146, 231 – OCDR0 EEPROM Address Register High 276 $1F ($3F) EEARH $1E ($3E) EEARL EEPROM Address Register Low Byte 30 30 $1D ($3D) EEDR EEPROM Data Register 30 $1C ($3C) EECR – – – – EERIE EEMWE EEWE EERE $1B ($3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 30 87 $1A ($3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 87 $19 ($39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 87 $18 ($38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 87 $17 ($37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 87 $16 ($36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 87 $15 ($35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 87 $14 ($34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 87 $13 ($33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 88 $12 ($32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 88 $11 ($31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 88 $10 ($30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 88 – – – – SPI2X 173 MSTR CPOL CPHA SPR1 SPR0 $0F ($2F) SPDR $0E ($2E) SPSR SPIF WCOL – SPI Data Register 173 $0D ($2D) SPCR SPIE SPE DORD $0C ($2C) UDR0 $0B ($2B) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 193 $0A ($2A) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 194 $09 ($29) UBRR0L $08 ($28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 231 $07 ($27) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 245 $06 ($26) ADCSRA ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 247 $05 ($25) ADCH ADC Data Register High Byte 248 $04 ($24) ADCL ADC Data Register Low byte 248 $03 ($23) PORTE USART0 I/O Data Register USART0 Baud Rate Register Low PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 171 192 197 PORTE2 PORTE1 PORTE0 88 19 8151GS–AVR–07/10 ATmega128A 5. Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $02 ($22) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 88 $01 ($21) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 88 $00 ($20) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 89 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 19 8151GS–AVR–07/10 ATmega128A 6. Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 1 COM Rd One’s Complement Rd ← $FF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← $00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← $FF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 Z,C 2 Z,C 2 Z,C 2 2 FMULS Rd, Rr Fractional Multiply Signed FMULSU Rd, Rr Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS RJMP k IJMP Relative Jump PC ← PC + k + 1 None Indirect Jump to (Z) PC ← Z None 2 JMP k Direct Jump PC ← k None 3 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 Indirect Call to (Z) PC ← Z None 3 Direct Subroutine Call PC ← k None 4 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 ICALL CALL k CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 1 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 19 8151GS–AVR–07/10 ATmega128A 6. Instruction Set Summary (Continued) BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None Mnemonics Operands Description Operation Flags 1/2 1/2 #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 Rd ← Rr Rd+1:Rd ← Rr+1:Rr None 1 None 1 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate Rd ← K None LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 Load Program Memory R0 ← (Z) None 3 LPM LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 3 Extended Load Program Memory R0 ← (RAMPZ:Z) None ELPM Rd, Z Extended Load Program Memory Rd ← (RAMPZ:Z) None 3 ELPM Rd, Z+ Extended Load Program Memory and Post-Inc Rd ← (RAMPZ:Z), RAMPZ:Z ← RAMPZ:Z+1 None 3 Store Program Memory (Z) ← R1:R0 None - IN Rd, P In Port Rd ← P None 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 ELPM SPM BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0:6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3:0)←Rd(7:4),Rd(7:4)←Rd(3:0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C←1 C 1 CLC Clear Carry C←0 C 1 SEN Set Negative Flag N←1 N 1 CLN Clear Negative Flag N←0 N 1 SEZ Set Zero Flag Z←1 Z 1 CLZ Clear Zero Flag Z←0 Z 1 SEI Global Interrupt Enable I←1 I 1 CLI Global Interrupt Disable I←0 I 1 19 8151GS–AVR–07/10 ATmega128A 6. Instruction Set Summary (Continued) SES Set Signed Test Flag S←1 S CLS Clear Signed Test Flag S←0 S Description Operation Flags SEV Set Twos Complement Overflow. V←1 V 1 CLV Clear Twos Complement Overflow V←0 V 1 SET Set T in SREG T←1 T 1 CLT Clear T in SREG T←0 T 1 SEH CLH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG H←1 H←0 H H 1 1 Mnemonics Operands 1 1 #Clocks MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/timer) For On-chip Debug Only None None 1 N/A 19 8151GS–AVR–07/10 ATmega128A 7. Ordering Information 7.1 ATmega128A Speed (MHz) 16 Notes: Power Supply 2.7 - 5.5V Ordering Code(2) Package(1) ATmega128A-AU ATmega128A-AUR(3) ATmega128A-MU ATmega128A-MUR(3) 64A 64A 64M1 64M1 Operation Range Industrial (-40oC to 85oC) 1. The device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Tape & Reel Package Type 64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 19 8151GS–AVR–07/10 ATmega128A 8. Packaging Information 8.1 64A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e NOTE Note 2 Note 2 0.80 TYP 10/5/2001 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 64A B 19 8151GS–AVR–07/10 ATmega128A 8.2 64M1 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A K 0.08 C L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B K Option C b e Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 b 0.18 0.25 0.30 D 8.90 9.00 9.10 D2 5.20 5.40 5.60 E 8.90 9.00 9.10 E2 5.20 5.40 5.60 e NOTE 0.50 BSC L 0.35 0.40 0.45 K 1.25 1.40 1.55 5/25/06 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 64M1 REV. G 19 8151GS–AVR–07/10 ATmega128A 9. Errata The revision letter in this section refers to the revision of the ATmega128A device. 9.1 ATmega128A Rev. U • • • • • • • Wrong value for Version in the JTAG Device Identification Register First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer Stabilizing time needed when changing XDIV Register Stabilizing time needed when changing OSCCAL Register IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable the Analog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 3. Stabilizing time needed when changing XDIV Register After increasing the source clock frequency more than 2% with settings in the XDIV register, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The NOP instruction will always be executed correctly also right after a frequency change. Thus, the next 8 instructions after the change should be NOP instructions. To ensure this, follow this procedure: 1.Clear the I bit in the SREG Register. 2.Set the new pre-scaling factor in XDIV register. 3.Execute 8 NOP instructions 4.Set the I bit in SREG This will ensure that all subsequent instructions will execute correctly. Assembly Code Example: CLI OUT ; clear global interrupt enable XDIV, temp ; set new prescale value NOP ; no operation NOP ; no operation NOP ; no operation 19 8151GS–AVR–07/10 ATmega128A NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation SEI ; set global interrupt enable 4. Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL register, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The behavior follows errata number 3., and the same Fix / Workaround is applicable on this errata. 5. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround – If ATmega128A is the only device in the scan chain, the problem is not visible. – Select the Device ID Register of the ATmega128A by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega128A while reading the Device ID Registers of preceding devices of the boundary scan chain. – If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega128A must be the fist device in the chain. 6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR. 19 8151GS–AVR–07/10 ATmega128A 10. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 10.1 Rev. 8151G – 07/10 1. 10.2 10.3 10.4 10.5 Rev. 8151F – 06/10 1. Inserted cross reference in “Minimizing Power Consumption” on page 48 2. Updated Technical Terminology according to Atmel standard 3. Note 6 and Note 7 below “Two-wire Serial Bus Requirements” on page 325 have been removed 4. The text in “Bit 6 – TXCIEn: TX Complete Interrupt Enable” on page 194 has been corrected by adding an “n” Rev. 8151E – 02/10 1. Updated “Receiving Frames with 9 Data Bits” on page 185. The C code updated. 2. Updated “Packaging Information” on page 373. 3. Updated “Performing Page Erase by SPM” on page 283. Rev. 8151D – 07/09 1. Updated “Errata” on page 376. 2. Updated the last page with Atmel’s new addresses. Rev. 8151C – 05/09 1. 10.6 Updated the table note of Table 27-3 on page 324. The test is performed using BODLEVEL=0 and BODLEVEL=1 Updated “Errata” on page 375. ATmega128A Rev. U. Rev. 8151B – 03/09 1. Updated view of “Typical Characteristics” on page 337 view. 2. Editorial updates. 19 8151GS–AVR–07/10 10.7 Rev. 8151A– 08/08 1. Initial revision. (Based on the ATmega128/L datasheet 2467R-AVR-06/08) Changes done compared to the ATmega128/L datasheet 2467R-AVR-06/08: - Updated “Stack Pointer” on page 13 description. - “Power Management and Sleep Modes” on page 46 is reorganized. - All Electrical characteristics is moved to “Electrical Characteristics” on page 321. - Output Low Voltage (VOL) and Reset Pull-up Resistor (RRST) limits updated in “DC Characteristics” on page 321. - Register descriptions are moved to sub sections at the end of each chapter. - New graphs in “Typical Characteristics” on page 338. - New “Ordering Information” on page 373. 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