REVISIONS LTR DESCRIPTION DATE APPROVED A Table I, input offset voltage test, delete 9 mV and substitute 8 mV. Table I, input offset current test, delete 20 nA and substitute 2 nA. Table I, input bias current test, delete 50 nA and substitute 20 nA. Table I, slew rate at unity gain test, delete 5 V/µs and substitute 8 V/µs. - ro 12-12-04 C. SAFFLE Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA 12-01-19 TITLE MICROCIRCUIT, LINEAR, LOW NOISE JFET INPUT OPERATIONAL AMPLIFIER, MONOLITHIC SILICON APPROVED BY CHARLES F. SAFFLE SIZE A REV AMSC N/A DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil/ CODE IDENT. NO. DWG NO. V62/12604 16236 A PAGE 1 OF 10 5962-V029-13 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low noise junction field effect transistor (JFET) input operational amplifier microcircuit, with an operating temperature range of -40°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12604 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 TL072-EP Circuit function Low noise JFET input operational amplifier 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 8 JEDEC PUB 95 Package style MS-012-AA Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12604 PAGE 2 1.3 Absolute maximum ratings. 1/ Supply voltage: +VCC ...................................................................................................................... 18 V 2/ -VCC ....................................................................................................................... 18 V 2/ Differential input voltage (VID) .................................................................................... ±30 V 3/ Input voltage (VI) ........................................................................................................ Duration of output short circuit ................................................................................... Operating virtual Junction temperature (TJ) ............................................................... Storage temperature range (TSTG) .............................................................................. Thermal resistance, junction to ambient (θJA) ............................................................ ±15 V 2/ 4/ Unlimited 5/ +150°C -65°C to +150°C 97.5°C/W 6/ 7/ Thermal resistance, junction to ambient (θJC) ............................................................ 38.3°C/W 7/ 1.4 Recommended operating conditions. 8/ Supply voltage range (±VCC) ..................................................................................... ±15 V Operating free-air temperature range (TA) ................................................................. -40°C to +125°C _____ 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltage values, except differential voltages, are with respect to the midpoint between +VCC and -VCC. 3/ Differential voltages are at +IN, with respect to -IN. 4/ The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. 5/ The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded. 6/ Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA )/ θJA. Operating at the absolute maximum TJ of +150°C can affect reliability. 7/ The package thermal impedance is calculated in accordance with JESD 51-7. 8/ Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12604 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 – EIA/JEDEC 51-7 – Registered and Standard Outlines for Semiconductor Devices High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Unity gain amplifier. The unity gain amplifier shall be as shown in figure 3. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12604 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ ±VCC = ±15 V, unless otherwise specified Temperature, TA 3/ Device type Limits Min Unit Max Electrical characteristics section Input offset voltage VIO VO = 0, RS = 50 Ω 01 +25°C 6 8 -40°C to +125°C Temperature coefficient of input offset voltage αVIO VO = 0, RS = 50 Ω Input offset current IIO VO = 0 -40°C to +125°C 01 +25°C 01 18 typical IIB 01 +25°C VO = 0 -40°C to +125°C Common mode input voltage range VICR Maximum peak output voltage swing VOM pA 2 nA 200 pA 20 nA +25°C 01 ±11 V RL = 10 kΩ +25°C 01 ±12 V RL ≥ 10 kΩ -40°C to +125°C ±12 ±10 RL ≥ 2 kΩ Large signal differential voltage amplification AVD µV / °C 100 -40°C to +125°C Input bias current mV VO = ±10 V, RL ≥ 2 kΩ 01 +25°C 35 V/ mV 15 -40°C to +125°C Unity gain bandwidth B1 +25°C 01 Input resistance ri +25°C 01 10 Common mode rejection ratio CMRR +25°C 01 80 dB Supply voltage rejection ratio (∆±VCC / ∆VIO) kSVR +25°C 01 80 dB Supply current (each amplifier) ICC VO = 0, no load +25°C 01 Crosstalk attenuation VO1 / AVD = 100 +25°C 01 VIC = VICRmin, 3 typical 12 MHz Ω typical VO = 0, RS = 50 Ω VCC = ±9 V to ±15 V, VO = 0, RS = 50 Ω 2.5 120 typical mA dB VO2 See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12604 PAGE 5 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions ±VCC = ±15 V Temperature, TA Device type Limits Min Unit Max Operating characteristics section Slew rate at unity gain SR VI = 10 V, RL = 2 kΩ, +25°C 01 8 +25°C 01 0.1 typical µs 20 typical % 18 typical nV / V/µs CL = 100 pF, see figure 3 Rise time overshoot factor tr VI = 20 V, RL = 2 kΩ, CL = 100 pF, see figure 3 Equivalent input noise voltage Vn f = 1 kHz, RS = 20 Ω 01 +25°C Hz f = 10 Hz to 10 kHz, RS = 20 Ω Equivalent input noise current In Total harmonic distortion THD f = 1 kHz, RS = 20 Ω 01 +25°C 4 typical µV 0.01 typical pA / Hz 01 +25°C VIrms = 6 V, AVD = 1, 0.003 typical % RL ≥ 2 kΩ, RS ≤ 1 kΩ, f = 1 kHz 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Input bias currents of an field effect transistor (FET) input operational amplifier are normal junction reverse currents, which are temperature sensitive. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as possible. 3/ All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12604 PAGE 6 Case X FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12604 PAGE 7 Case X Dimensions Inches Symbol Millimeters Min Max Min Max A --- 0.069 --- 1.75 A1 0.004 0.010 0.10 0.25 b 0.012 0.020 0.31 0.51 c 0.005 0.010 0.13 0.25 D 0.189 0.197 4.80 5.00 E 0.150 0.157 3.80 4.00 E1 0.228 0.244 5.80 6.20 e 0.050 BSC L 0.016 n 1.27 BSC 0.050 0.40 8 1.27 8 NOTES: 1. Controlling dimensions are inch, millimeter dimensions are given for reference only. 2. For dimension D, body length does not include mold flash, protrusion, or gate burrs. Mold flash, protrusion, or gate burrs shall not exceed 0.006 inch (0.15 mm) each side. 3. For dimension E, body width does not include interlead flash. Interlead flash shall not exceed 0.017 inch (0.43 mm) each side. 4. Falls with JEDEC MS-012 variation AA. FIGURE 1. Case outline – Continued. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12604 PAGE 8 Device type 01 Case outline X Terminal number Terminal symbol 1 OUT1 2 -IN1 3 +IN1 4 -VCC 5 +IN2 6 -IN2 7 OUT2 8 +VCC FIGURE 2. Terminal connections. FIGURE 3. Unity gain amplifier. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12604 PAGE 9 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ 2/ Device manufacturer CAGE code Top side marking Vendor part number V62/12604-01XE 01295 TL072Q TL072QDREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ For the most current package and ordering information, see the package option addendum at the end of the manufacturer’s data sheet. CAGE code 01295 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12604 PAGE 10