ATMEL AT27C2048-90JI

Features
• Fast Read Access Time – 55 ns
• Low Power CMOS Operation
•
•
•
•
•
•
•
•
– 100 µA Maximum Standby
– 35 mA Maximum Active at 5 MHz
JEDEC Standard Packages
– 40-lead PDIP
– 44-lead PLCC
– 40-lead VSOP
Direct Upgrade from 512-Kbit and 1-Mbit (AT27C516 and AT27C1024) EPROMs
5V ± 10% Power Supply
High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Rapid Programming Algorithm – 50 µs/Word (Typical)
CMOS and TTL Compatible Inputs and Outputs
Integrated Product Identification Code
Industrial Temperature Range
2-Megabit
(128K x 16)
OTP EPROM
AT27C2048
1. Description
The AT27C2048 is a low-power, high-performance 2,097,152-bit one-time programmable read-only memory (OTP EPROM) organized 128K by 16 bits. It requires a
single 5V power supply in normal read mode operation. Any word can be accessed in
less than 55 ns, eliminating the need for speed-reducing WAIT states. The by-16
organization makes this part ideal for high-performance 16 and 32 bit microprocessor
systems.
In read mode, the AT27C2048 typically consumes 15 mA. Standby mode supply current is typically less than 10 µA.
The AT27C2048 is available in industry-standard JEDEC-approved one-time programmable (OTP) plastic PDIP, PLCC, and VSOP packages. The device features
two-line control (CE, OE) to eliminate bus contention in high-speed systems.
With high density 128K word storage capability, the AT27C2048 allows firmware to be
stored reliably and to be accessed by the system without the delays of mass storage
media.
Atmel’s AT27C2048 has additional features that ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program
the part and guarantees reliable programming. Programming time is typically only
50 µs/word. The Integrated Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry-standard programming
equipment to select the proper programming algorithms and voltages.
0632F–EPROM–12/07
2. Pin Configurations
2.2
A0 - A16
Addresses
O0 - O15
Outputs
CE
Chip Enable
OE
Output Enable
PGM
Program Strobe
NC
No Connect
Don’t Connect
2.1
40-lead PDIP Top View
VPP
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
PGM
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
2.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
O0
O1
O2
O3
O4
O5
O6
O7
GND
44-lead PLCC Top View
O13
O14
O15
CE
VPP
DC
VCC
PGM
A16
A15
A14
Both GND pins must be connected.
2
A9
A10
A11
A12
A13
A14
A15
A16
PGM
VCC
VPP
CE
O15
O14
O13
O12
O11
O10
O9
O8
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
O3
O2
O1
O0
OE
DC
A0
A1
A2
A3
A4
DC
Note:
40-lead VSOP (Type 1) Top View
6
5
4
3
2
1
44
43
42
41
40
Function
18
19
20
21
22
23
24
25
26
27
28
Pin Name
Note:
Note: PLCC package pins 1 and 23 are Don’t Connect.
AT27C2048
0632F–EPROM–12/07
AT27C2048
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient
voltage excursions. Unless accommodated by the system design, these transients may exceed
datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency,
low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor
should be connected between the VCC and Ground terminals of the device, as close to the
device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards
with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as
possible to the point where the power supply is connected to the array.
4. Block Diagram
VCC
GND
VPP
OE
CE
A0 - A17
ADDRESS
INPUTS
DATA OUTPUTS
O0 - O15
OE, CE AND
PROGRAM LOGIC
OUTPUT
BUFFERS
Y DECODER
Y-GATING
CELL MATRIX
X DECODER
IDENTIFICATION
5. Absolute Maximum Ratings*
Temperature Under Bias............................... -55° C to +125° C
Storage Temperature .................................... -65° C to +150° C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on A9 with
Respect to Ground ......................................-2.0V to +14.0V(1)
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
VPP Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Note:
1. Maximum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns.
3
0632F–EPROM–12/07
6. Operating Modes
Mode/Pin
CE
OE
PGM
Ai
VPP
Outputs
Read
VIL
VIL
X(1)
Ai
X(1)
DOUT
Output Disable
X
VIH
X
X
X
High Z
(5)
Standby
VIH
X
X
X
X
High Z
Rapid Program(2)
VIL
VIH
VIL
Ai
VPP
DIN
PGM Verify
VIL
VIL
VIH
Ai
VPP
DOUT
PGM Inhibit
VIH
X
X
X
VPP
High Z
VCC
Identification Code
Product Identification(4)
Notes:
VH(3)
VIL
VIL
A9 =
A0 = VIH or VIL
A1 - A16 = VIL
X
1. X can be VIL or VIH.
2. Refer to the Programming characteristics.
3. VH = 12.0 ± 0.5V.
4. Two identifier words may be selected. All Ai inputs are held low (VIL), except A9, which is set to VH, and A0, which is toggled
low (VIL) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word.
5. Standby VCC current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB.
7. DC and AC Operating Conditions for Read Operation
AT27C2048
Industrial Operating Temperature (Case)
VCC Power Supply
-55
-90
-40° C - 85° C
-40° C - 85° C
5V ± 10%
5V ± 10%
8. DC and Operating Characteristics for Read Operation
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
IPP1
(2)
ISB
Max
Units
VIN = 0V to VCC
±1
µA
Output Leakage Current
VOUT = 0V to VCC
±5
µA
VPP(1)
VPP = VCC
10
µA
ISB1 (CMOS)
CE = VCC ± 0.3V
100
µA
ISB2 (TTL)
CE = 2.0 to VCC + 0.5V
1
mA
f = 5 MHz, IOUT = 0 mA, CE = VIL
35
mA
Read/Standby Current
VCC(1) Standby Current
Min
ICC
VCC Active Current
VIL
Input Low Voltage
-0.6
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.4
V
VOH
Output High Voltage
IOH = -400 µA
Notes:
2.4
V
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
4
AT27C2048
0632F–EPROM–12/07
AT27C2048
9. AC Characteristics for Read Operation
AT27C2048
-55
Symbol
Parameter
Condition
tACC(3)
Address to Output Delay
CE = OE
= VIL
tCE(2)
CE to Output Delay
tOE(2)(3)
OE to Output Delay
tDF(4)(5)
OE or CE High to Output Float, Whichever Occurred First
tOH(4)
Output Hold from Address, CE or OE, Whichever
Occurred First
Note:
Min
-90
Max
Max
Units
55
90
ns
OE = VIL
55
90
ns
CE = VIL
20
35
ns
20
20
ns
7
Min
0
ns
2, 3, 4, 5. See the AC Waveforms for Read Operation diagram.
10. AC Waveforms for Read Operation(1)
Notes:
1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
5
0632F–EPROM–12/07
11. Input Test Waveforms and Measurement Levels
For -55 devices only:
tR, tF < 5 ns (10% to 90%)
For -90 devices:
tR, tF < 20 ns (10% to 90%)
12. Output Test Load
Note:
CL = 100 pF including jig capacitance, except for the -55 devices, where CL = 30 pF.
13. Pin Capacitance
Symbol
Typ
Max
Units
Conditions
CIN
4
10
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
6
Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
AT27C2048
0632F–EPROM–12/07
AT27C2048
14. Programming Waveforms(1)
Notes:
1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the AT27C2048, a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage
transients.
15. DC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits
Symbol
Parameter
Test Conditions
ILI
Input Load Current
VIN = VIL, VIH
VIL
Input Low Level
VIH
Input High Level
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -400 µA
ICC2
VCC Supply Current (Program and Verify)
IPP2
VPP Supply Current
VID
A9 Product Identification Voltage
Min
Max
Units
±10
µA
-0.6
0.8
V
2.0
VCC + 0.5
V
0.4
V
2.4
CE = VIL
11.5
V
50
mA
30
mA
12.5
V
7
0632F–EPROM–12/07
16. AC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits
Test Conditions(1)
Symbol
Parameter
tAS
Address Setup Time
tOES
OE Setup Time
tDS
Data Setup Time
tAH
Address Hold Time
Input Rise and Fall Times
(10% to 90%) 20 ns
Input Pulse Levels
Data Hold Time
tDH
tDFP
OE High to Output Float Delay
tVPS
VPP Setup Time
tVCS
VCC Setup Time
tPW
PGM Program Pulse Width(3)
tOE
Data Valid from OE
tPRT
VPP Pulse Rise Time During
Programming
Notes:
Min
0.45V to 2.4V
(2)
Max
2
µs
2
µs
2
µs
0
µs
2
µs
0
Input Timing Reference Level
0.8V to 2.0V
130
ns
2
µs
2
µs
47.5
Output Timing Reference Level
0.8V to 2.0V
Units
52.5
µs
150
ns
50
ns
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven –
see timing diagram.
3. Program Pulse width tolerance is 50 µsec ± 5%.
17. Atmel’s 27C2048 Intergrated Product Identification Code
Pins
Codes
A0
O15-O8
O7
O6
O5
O4
O3
O2
O1
O0
Hex Data
Manufacturer
0
0
0
0
0
1
1
1
1
0
001E
Device Type
1
0
1
1
1
1
0
1
1
1
00F7
8
AT27C2048
0632F–EPROM–12/07
AT27C2048
18. Rapid Programming Algorithm
A 50 µs CE pulse width is used to program. The address is set to the first location. VCC is raised
to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 50 µs CE pulse
without verification. Then a verification/reprogramming loop is executed for each address. In the
event a word fails to pass verification, up to 10 successive 50 µs pulses are applied with a verification after each pulse. If the word fails to verify after 10 pulses have been applied, the part is
considered failed. After the word verifies properly, the next address is selected until all have
been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All words are read again and compared with the original data to determine if the device passes or fails.
9
0632F–EPROM–12/07
19. Ordering Information
19.1
Standard Package
ICC (mA)
tACC
(ns)
Active
Standby
55
35
90
35
Note:
19.2
Ordering Code
Package
0.1
AT27C2048-55JI
AT27C2048-55PI
AT27C2048-55VI
44J
40P6
40V(1)
Industrial
(-40° C to 85° C)
0.1
AT27C2048-90JI
AT27C2048-90PI
AT27C2048-90VI
44J
40P6
40V(1)
Industrial
(-40° C to 85° C)
Not recommended for new designs. Use Green package option.
Green Package (Pb/Halide-free)
ICC (mA)
tACC
(ns)
Active
Standby
55
35
90
35
Note:
Operation Range
Ordering Code
Package
Operation Range
0.1
AT27C2048-55JU
AT27C2048-55PU
44J
40P6
Industrial
(-40° C to 85° C)
0.1
AT27C2048-90JU
AT27C2048-90PU
44J
40P6
Industrial
(-40° C to 85° C)
1. The 40-lead VSOP package is not recommended for new designs.
Package Type
44J
44-lead, Plastic J-leaded Chip Carrier (PLCC)
40P6
40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
40V
40-lead, Plastic Thin Small Outline Package (VSOP)
10
AT27C2048
0632F–EPROM–12/07
AT27C2048
20. Packaging Information
20.1
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
17.399
–
17.653
D1
16.510
–
16.662
E
17.399
–
17.653
E1
16.510
–
16.662
D2/E2
14.986
–
16.002
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
44J
B
11
0632F–EPROM–12/07
20.2
40P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
0º ~ 15º
C
COMMON DIMENSIONS
(Unit of Measure = mm)
REF
MIN
NOM
MAX
A
–
–
4.826
A1
0.381
–
–
D
52.070
–
52.578
E
15.240
–
15.875
E1
13.462
–
13.970
B
0.356
–
0.559
B1
1.041
–
1.651
L
3.048
–
3.556
C
0.203
–
0.381
eB
15.494
–
17.526
SYMBOL
eB
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
e
NOTE
Note 2
Note 2
2.540 TYP
09/28/01
R
12
2325 Orchard Parkway
San Jose, CA 95131
TITLE
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
40P6
REV.
B
AT27C2048
0632F–EPROM–12/07
AT27C2048
20.3
40V – VSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
13.80
14.00
14.20
D1
12.30
12.40
12.50
Note 2
E
9.90
10.00
10.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation CA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
40V, 40-lead (10 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP)
DRAWING NO.
REV.
40V
B
13
0632F–EPROM–12/07
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International
Atmel Corporation
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USA
Tel: 1(408) 441-0311
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0632F–EPROM–12/07