ATMEL ATA6660

Features
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Usable for Automotive 12 V/24 V and Industrial Applications
Maximum High-speed Data Transmissions up to 1 MBaud
Fully Compatible with ISO 11898
Controlled Slew Rate
Standby Mode
TXD Input Compatible to 3.3 V
Short-circuit Protection
Overtemperature Protection
High Voltage Bus Lines Protection, -40 V to +40 V
High Speed Differential Receiver Stage with a Wide Common Mode Range,
-10 V to +10 V, for High Electromagnetic Immunity (EMI)
• Fully Controlled Bus Lines, CANH and CANL to Minimize
Electromagnetic Emissions (EME)
• High ESD Protection at CANH, CANL HBM 8 kV, MM 300 V
High-speed
CAN
Transceiver
ATA6660
Description
The ATA6660 is a monolithic circuit based on the Atmel’s Smart Power BCD60-III
technology. It is especially designed for high speed CAN-Controller (CAN-C) differential mode data transmission between CAN-Controllers and the physical differential bus
lines.
Figure 1. Block Diagram
3 VCC
1 TXD
TXD input stage
Overtemperature
and Short circuit
protection
Driver
7 CANH
8 RS
Constant slope/
standby
4 RXD
Receiver
6 CANL
5 VREF
Reference
Voltage
0.5*VCC
2 GND
Rev. 4582B–BCD–03/03
1
Pin Configuration
Figure 2. Pinning SO8
TXD
GND
VCC
RXD
1
2
3
4
8
7
6
5
RS
CANH
CANL
VREF
Pin Description
Pin
Symbol
1
TXD
Function
Transmit data input
2
GND
Ground
3
VCC
Supply voltage
4
RXD
Receive data output
5
VREF
Reference voltage output
6
CANL
Low level CAN voltage input/output
7
CANH
High level CAN voltage input/output
8
RS
Switch standby mode/normal mode
Functional
Description
The ATA6660 is a monolithic circuit based on Atmel’s Smart Power BCD60-III technology. It is especially designed for high-speed differential mode data transmission in harsh
environments like automotive and industrial applications. Baudrate can be adjusted up
to 1 Mbaud. The ATA6660 is fully compatible to the ISO11898, the developed standard
for high speed CAN-C (Controller Area Network) communication.
Voltage Protection and
ESD
High voltage protection circuitry on both line pins, CANH (Pin 7) and CANL (Pin 6), allow
bus line voltages in the range of -40 V to +40 V. ESD protection circuitry on line pins
allow HBM = 8 kV, MM = 300 V. The implemented high voltage protection on bus line
output/input pins (7/6) makes the ATA6660 suitable for 12 V automotive applications as
well as 24 V automotive applications.
Slope Control
A fixed slope is adjusted to prevent unsymmetrical transients on bus lines causing EMC
problems. Controlled bus lines, both CANH and CANL signal, will reduce radio frequency interference to a minimum. In well designed bus configurations the filter design
costs can be reduced dramatically.
Overcurrent Protection
In the case of a line shorts, like CANH to GND, CANL to VCC, integrated short current
limitation allows a maximum current of ICANH_SC or ICANL_SC. If junction temperature rises
above 165°C an internal overtemperature protection circuitry shuts down both output
stages, the receiver will stay activated.
2
ATA6660
4582B–BCD–03/03
ATA6660
Standby Mode
The ATA6660 can be switched to standby mode by forcing the voltage
VRS > 0.87 ´ VCC. In standby mode the supply current will reduce dramatically, supply
current during standby mode is typical 600 µA (IVCC_stby). Transmitting data function will
not be supported, but the oppertunity will remain to receive data. A high-speed comparator is listening for activities on the bus. A dominant bus signal will force the output RXD
to a low level in typical tdRXDL = 400 ns. If the RS pin is not connected, causing through a
broken connection to the controller, the ATA6660 will switch to standby mode
automatically.
High-speed Receiver
In normal mode a fast receiver circuitry combined with a resistor network is able to
detect differential bus line voltages Vrec_th > 0.9 V as dominant bit, differential bus line
voltages Vrec_th < 0.5 V as recessive bit.
The wide receiver common mode range, -10 V to +10 V, combined with a symmetrical
differential receiver stage offers high immunity against electromagnetic interference. A
typical hysteresis of 70 mV is implemented. Dominant differential bus voltages forces
RXD output (Pin 4) to low level, recessive differential bus voltages to high level.
TXD Input
The input stage Pin 1 (TXD) is compatible for 3.3 V output levels from new controller
families. Pull-up resistance (25 kW) forces the IC to recessive mode, if TXD-Pin is not
connected. TXD low signal drives the transmitter into dominant state.
Transmitter
A integrated complex compensation technique allows stable data transmission up to
1 MBaud. Low level on TXD input forces bus line voltages CANH to 3.5 V, CANL to
1.5 V with a termination resistor of 60 W. In the case of a line short circuit, like CANH to
GND, CANL to VCC, integrated short current limitation circuitry allows a maximum current of 150 mA. If junction temperature rises above typical 163 ° C an internal
overtemperature protection shuts down both output stages, the receive mode will stay
activated.
Split Termination
Concept
With a modified bus termination (see Figure 5) a reduction of emission and a higher
immunity of the bus system can be achieved. The one 120 W resistor at the bus line end
nodes is split into two resistors of equal value, i.e., two resistors of 60 W. The resistors
for the stub nodes is recommended with two resistors of 1,3 kW. (for example 8 stub
nodes and 2 bus end nodes) Notice: The bus load of all the termination resistors has to
stay within the range of 50 W to 65 W.
The common mode signal at the centre tap of the termination is connected to ground via
a capacitor of e.g., Csplit = 10 nF to 100 nF. A seperate ground lead to the ground pin of
the module connector is recommended.
3
4582B–BCD–03/03
Absolute Maximum Ratings
Parameters
Symbol
Min.
Max.
Unit
VCC
-0.3
+6
V
VTXD, VREF, VRS,
VRXD
-0.3
VCC +0.3
V
-40.0
+40.0
V
Supply voltage
DC voltage at Pins 1, 4, 5 and 8
DC voltage at Pins 6 and 7
Conditions
VCANH, VCANL
0 V < VCC < 5.25 V;
no time limit
Transient voltage at Pins 6 and 7
-150
+100
V
Storage temperature
TStg
-55
+150
°C
Operating ambient temperature
Tamb
-40
+125
°C
ESD classification
All pins
HBM ESD S.5.1
MM JEDEC A115A
±3000
±200
V
V
ESD classification
Pin 6, 7 versus
Pin 2
HBM 1.5 kW, 100 pF
MM 0W, 200 pF
±8000
±300
V
V
Thermal Resistance
Parameters
Thermal resistance from junction to ambient
Symbol
Value
Unit
RthJA
160
K/W
Truth Table
VCC
TXD
RS
CANH
CANL
Bus State
RXD
4.75 V to 5.25 V
0
< 0.3 ´ VCC
3.5 V
1.5 V
Dominant
0
4.75 V to 5.25 V
1 (or floating)
< 0.3 ´ VCC
0.5 ´ VCC
0.5 ´ VCC
Recessive
1
4.75 V to 5.25 V
X
> 0.87 ´ VCC
0.5 ´ VCC
0.5 ´ VCC
Recessive
1
RS (Pin 8) Functionality
Slope Control
Mode
Voltage and Current Levels
VRS > 0.87 ´ VCC
Standby
IRS < | 10 µA |
VRS < 0.3 ´ VCC
Constant slope control
IRS £ 500 µA
4
ATA6660
4582B–BCD–03/03
ATA6660
Electrical Characteristics
VCC = 4.75 V to 5.25 V; Tamb = -40°C to +125°C; RBus = 60 Ω; unless otherwise specified
All voltages referenced to ground (Pin 2); positive input current.
No.
1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Supply Current
1.1
Supply current
dominant
VTXD = 0 V
VRS = 0 V
3
Ivcc_dom
45
60
mA
A
1.2
Supply current
recessive
VTXD = 5 V
VRS = 0 V
3
Ivcc_rec
10
15
mA
A
1.3
Supply current standby
VRS = 5 V
3
Ivcc_stby
600
980
µA
A
2
Transmitter Data Input TXD
2.1
HIGH level input
voltage
VTXD = 5 V
VRS = 0 V
1
VTXDH
2
VCC+0.3
V
A
2.2
LOW level input
voltage
VTXD = 0 V
VRS = 0 V
1
VTXDL
-0.3
+1
V
A
2.3
HIGH level input
current
VTXD = VCC
1
IIH
-1
0
µA
A
2.4
LOW level input
voltage
VTXD = 0 V
1
IIL
-500
-50
µA
A
3
Receiver Data Output RXD
3.1
High level output
voltage
IRXD = -100 µA
4
VRXDH
0.8 ´ VCC
VCC
V
A
3.2
Low level output
voltage
IRXD = 1 mA
4
VRXDL
0
0.2 ´ VCC
V
A
Short current at RXD
VTXD = 5 V
VRXD = 0 V
4
IRXDs1
-3
-1
mA
A
Short current at RXD
VTXD = 0 V
VRXD = 5 V
4
IRXDs2
2
6
mA
A
3.3
3.4
4
Reference Output Voltage VREF
4.1
Reference output
voltage normal mode
VRS = 0 V;
-50 µA < I5 < 50 µA
5
Vref_no
0.45 VCC
-
0.55 VCC
V
A
4.2
Reference output
voltage standby mode
VRS = 5 V;
-5µA < I5 < 5 µA
5
Vref_stby
0.4 ´ VCC
-
0.6 VCC
V
A
2.5
3.0
V
A
+5
mA
A
5
DC Bus Transmitter CANH; CANL
Recessive bus
voltage
VTXD = VCC; no load
6, 7
VCANH;
VCANL
2.0
IO(CANH)(reces)
IO(CANL)(reces)
-40 V < VCANH;
VCANL < 40 V;
0 V < VCC < 5.25 V
6, 7
IO_reces
-5
5.3
CANH output voltage
dominant
VTXD = 0 V
6, 7
VCANH
2.8
3.5
4.5
V
A
5.4
CANL output voltage
dominant
VTXD = 0 V
6, 7
VCANL
0.5
1.5
2.0
V
A
5.1
5.2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
5
4582B–BCD–03/03
Electrical Characteristics (Continued)
VCC = 4.75 V to 5.25 V; Tamb = -40°C to +125°C; RBus = 60 Ω; unless otherwise specified
All voltages referenced to ground (Pin 2); positive input current.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Differential bus output
voltage
(VCANH – VCANL)
VTXD = 0 V;
RL = 45 W to 60 W;
VCC = 4.9 V
6, 7
Vdiffdom
1.5
2
3.0
V
A
5.5
5.6
VTXD = VCC; no load
6, 7
Vdiffrec
-500
+50
mV
A
5.7
Short-circuit CANH
current
VCANH = -10 V
TXD = 0 V
6, 7
ICANH_SC
-35
-100
mA
A
5.8
Short-circuit CANL
current
VCANL = 18 V
TXD = 0 V
6, 7
ICANL_SC
50
-
150
mA
A
6
DC Bus Receiver CANH; CANL
Differential receiver
threshold voltage
normal mode
-10 V < VCANH < +10
V
-10 V < VCANL <
+10 V
6, 7
Vrec_th
0.5
0.7
0.9
V
A
Differential receiver
threshold voltage
stand-by mode
VRS = VCC
6, 7
Vrec_th_stby
0.5
0.7
0.9
V
A
6.2
6.3
Differential input
hysteresis
6, 7
Vdiff(hys)
mV
A
CANH and CANL
common mode input
resistance
6, 7
Ri
5
15
25
kW
A
6.4
6.5
Differential input
resistance
6, 7
Rdiff
10
30
100
kW
A
6, 7
Ri_m
-3
+3
%
A
6.6
Matching between
CANH and CANL
common mode input
resistance
6.7
CANH, CANL input
capacitance
6, 7
Ci
20
pF
D
6.8
Differential input
capacitance
6, 7
Cdiff
10
pF
D
6, 7
ILI(CANH);
ILI(CANL)
250
µA
A
6.1
6.9
CANH, CANL input
leakage input current
7
Thermal Shut-down
VCC = 0 V
VCANH = 3.5 V
VCANL = 1.5 V
70
Shut-down junction
temperature for
CANH/CANL
TJ(SD)
150
163
175
°C
B
7.1
Switch on junction
temperature for
CANH/CANL
TJ(SD)
140
154
165
°C
B
7.2
7.3
Temperature
hysteresis
THys
K
B
10
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
6
ATA6660
4582B–BCD–03/03
ATA6660
Electrical Characteristics (Continued)
VCC = 4.75 V to 5.25 V; Tamb = -40°C to +125°C; RBus = 60 Ω; unless otherwise specified
All voltages referenced to ground (Pin 2); positive input current.
No.
8
Parameters
Test Conditions
VRS = 0 V
8.2
Delay TXD to bus
inactive
VRS = 0 V
8.3
Delay TXD to RXD,
recessive to dominant
VRS = 0 V
8.4
Delay TXD to RXD,
dominant to recessive
VRS = 0 V
8.5
Difference between
Delay TXD to RXD
dominant to Delay
recessive
tdiff = td_activ(TXD-RXD)
- td_inactiv(TXD-RXD)
9
Symbol
Min.
Typ.
Max.
Unit
Type*
120
180
ns
A
50
100
ns
A
200
420
ns
A
180
460
ns
A
80
ns
A
450
ns
A
2
µs
A
0.3 ´ VCC
V
A
Timing Characteristics Normal Mode , VRS ≤ 0.3 ´VCC (see Figure 3)
Delay TXD to bus
active
8.1
Pin
td(TXDBUS_ON)
td(TXDBUS_OFF)
6, 7
td_activ(TXDRXD)
td_inactiv(TXDRXD)
tdiff
-280
4
tdRxDL
-
6, 7
Twake_up
Timing Characteristics Stand-by Mode VRS ≥ 0.87 ´ VCC
9.1
Bus dominant to RXD
low in stand-by mode
VRS = VCC
300
TXD = 0 V
VRS from 0 V to VCC
9.2
Wake up time after
stand-by mode (time
delay between standby to normal mode
and to bus dominant)
10.1
Standby/Normal Mode Selecteable via RS (Pin 8)
10.1
Input voltage for
normal mode
VRS = VCC
8
VRS
-
10.2
Input current for
normal mode
VRS = 0 V
8
IRS
-700
µA
A
10.3
Input voltage for
stand-by mode
8
Vstby
0.87 ´
VCC
V
A
-
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
7
4582B–BCD–03/03
Figure 3. Timing Diagrams
HIGH
TXD
LOW
dominant
CANH
CANH
CANL
dominant
CANL
dominant
(bus activ)
0.9V
Vdiff
0.5V
recessive
(bus inactive)
HIGH
0.7VCC
RXD
0.3VCC
LOW
td (TXD_bus_on)
td (TXD_bus_off)
t d_activ(TXD_RXD)
8
t d_inactiv (TXD_RXD)
ATA6660
4582B–BCD–03/03
ATA6660
Figure 4. Test Circuit for Timing Characteristics
TXD
GND
RXD
C=47µF
C=100nF
8
2
7
ATA6660
VCC
+ 5V
1
3
6
4
5
RS
CANH
CANL
RL=62
CL=100pF
Vref
C=15pF
Figure 5. Bus Application with Split Termination Concept
bus line
end node
RS
7
CANH
6
CANL
5
+ 5V
2
GND
8
1
TXD
CAN
Controller
Vref
ATA6660
3
VCC
4
RXD
CSPLIT =10nF
RL=60
RL=60
bus line
stub node
RL=1,3k
C=15pF
C=47µF
C=100nF
RL=1,3k
7
CANH
6
CANL
5
4
C=100nF
RS
Vref
ATA6660
RXD
C=47µF
8
VCC
3
+ 5V
2
GND
1
TXD
CAN
Controller
C=15pF
CSPLIT =10nF
RL=60
RL=60
CSPLIT =10nF
bus line
end node
9
4582B–BCD–03/03
Ordering Information
Extended Type Number
Package
ATA6660
Remarks
SO8
–
Package Information
Package SO8
Dimensions in mm
5.2
4.8
5.00
4.85
3.7
1.4
0.25
0.10
0.4
1.27
6.15
5.85
3.81
8
0.2
3.8
5
technical drawings
according to DIN
specifications
1
10
4
ATA6660
4582B–BCD–03/03
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Printed on recycled paper.
4582B–BCD–03/03
xM