ATMEL TSS461C

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Fully Compliant to VAN Specification ISO/11519-3
Handles All Specified Module Types
Handles All Specified Message Types
Handles Retransmission of Frames on Contention and Errors
3 Separate Line Inputs with Automatic Diagnosis and Selection
1 Mbit/s Maximum Transfer Rate
Normal or Pulsed (Optical and Radio Mode) Coding
Intel®, NEC®, Texas Instruments® and Motorola® Compatible 8-bit Microprocessor
Interface
Multiplexed Address and Data Bus
Idle and Sleep Modes
128 Bytes of General-purpose RAM
DMA Capabilities for Message Handling
14 Identifier Registers with All Bits Individually Maskable
6-source Maskable Interrupt, Including an Interrupt-on-reset to Detect Glitches on the
Reset Pin
Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and
Buffered Clock Output
Single +5V Power Supply
0.8 µm CMOS Technology
SO24 Package
VAN Data Link
Controller
TSS461C
Description
Cost optimization in car manufacturing is of extreme importance today. Solutions to
this problem often implies the use of more advanced and intelligent electronic circuits.
The TSS461C is a circuit which allows the transfer of all the status information needed
in a car or truck over a single low-cost wire pair, that minimizes the electrical wire
usage.
It can be used to interconnect powerful functions (ABS, dashboard, power train control) and to control and interface car body electronics (lights, wipers, power window,
etc.).
The TSS461C is fully compliant with the ISO Standard 11519-3. This standard supports a wide range of applications such as low-cost remote-control switches. Typically
it is used for lamp control; complex, highly-autonomous, distributed systems like
engine controls, which require fast and secure data transfers.
The TSS461C is a microprocessor-interfaced line controller for mid-to-high complexity
bus-masters and listeners like injection/ignition control calculators, dashboard controllers and car stereo or mobile telephone CPUs.
The microprocessor interface consists of a 256-bytes of RAM and a register area
divided into 11 control registers, 14 channel register sets and 128 bytes of general
purpose RAM, used as a message storage area, and a 6-source maskable interrupt.
The circuit operates in RAM using DMA techniques, controlled by the channel and
control registers. This allows virtually any microprocessor to interface with ease to the
TSS461C, and to use the free RAM as a scratch pad.
Messages are encoded in enhanced Manchester code, and an optional pulsed code
for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS461C
analyzes the messages received or transmitted according to 6 different criteria including some higher level checks.
In addition, the bus interface has three separate inputs with automatic source diagnosis and selection, that allows for multibus listening or the automatic selection of the
most reliable source at any time if several line receivers are connected to the same
bus.
4193G–AUTO–12/04
1
Block Diagram
AD[7:0]
ALE
RESET TEST
INT
VCC GND
Address and Data Bus
Multiplexing logic
control bus
data bus
Status and
control
registers
address bus
status bus
128 bytes
Message
buffer
RAM
Protocol controller
state machine and
ID registers
Data serializer and
deserializer
Clock generator and
line synchronization
logic
XTAL1 XTAL2
2
CKOUT
Reception logic
Source diagnosis
and selection logic
CRC generator
and checker
Transmission logic
TxD
RxD0 RxD1 RxD2
TSS461C
4193G–AUTO–12/04
TSS461C
Pin Configuration
TOP VIEW
24 Pin SOP
AD4
1
24
AD3
AD5
2
23
AD2
AD6
3
22
AD1
AD7
4
21
AD0
VCC
5
20
VSS
INT
6
19
RESET
ALE
7
18
TXD
(E) CS
8
17
RXD0
XTAL1
9
16
RXD2
XTAL2
10
15
RXD1
Test/VSS
11
14
WR (R/W)
CKOUT
12
13
RD (VSS)
Note:
1. The names in parenthesis refer to the functionalities in Motorola mode.
I/O Type
Pin Name
Pin Number
Pin Function
I/O TTL
AD0
21
AD1
22
AD2
23
Multiplexed address and
data bus. The address is
latched on the falling
address of ALE.
AD3
24
AD4
1
AD5
2
AD6
3
AD7
4
ALE
7
Address Latch Enable
RD (VSS)
13
Read Command
WR (R/W)
14
Write Command
CS(E)
8
Chip Select (active high)
INT
6
Interrupt
RESET
19
Asynchronous general
reset glitch filtered
(12 ns)
I Trigger TTL
Open-drain
I Trigger CMOS Pull-down
3
4193G–AUTO–12/04
I/O Type
Pin Name
Pin Number
RXD0
17
RXD1
15
RXD2
16
TXD
18
VAN bus Output
I
XTAL1
9
0
Crystal oscillator or clock
input pins
XTAL2
10
CKOUT
12
Buffered clockout output
enabled if no reset
Ground
TEST/VSS
11
Oscillator Ground
Power
VCC
5
+5V Power Supply
Ground
VSS
20
I CMOS Pull-down
3-state
0
4
Pin Function
VAN bus Inputs
TSS461C
4193G–AUTO–12/04
TSS461C
Operation
The TSS461C is a microprocessor-controlled line controller for the VAN bus. It can interface to virtually any microprocessor, but the I/O signals of the circuit have been
optimized to use with the TSC51/TSC251 series of microcontrollers.
It features a multiplexed address and data bus, controlled by an address strobe pin ALE
and separated read RD and write WR command pins. The address is latched on the falling edge of ALE.
The circuit also features one single interrupt pin. This pin can be treated as level or edge
sensitive, For example, if there is a pending interrupt inside the circuit when another
interrupt is reset, the INT pin will emit a high pulse with the same pulse width as the
internal write strobe (typically 20 ns).
Figure 1. Typical Application
VAN Bus
General I/O
Remaining Pins
GND
XTAL1
P3.6/WR
WR
P3.7/RD
RD
XTAL2
TXD
GND
Differential
DATA
33 pF
C1
DATA
TSS461C
Series
Microcontroller
+
RXD0
ALE
ALE
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
RESET XTAL1 INT
VCC
VAN
DLC
RXD1
RXD2
DATA
+
-
CS
INT CKOUT RESET
DATA
VREF
+
VAN Line Driver
& Receivers
5
4193G–AUTO–12/04
Microprocessor
Interface
The processor controls the TSS461C by reading and writing the internal registers of the
circuit. These registers appear to the processor as regular memory locations.
Interface Modes
The TSS461C must be plugged in an Intel or Motorola environment with an 8-bit
address/data bus multiplexed.
Table 1. Access Mode Logic
CS (E)
RD
WR (R/W)
Operation Mode
No operation
0
1
0
0
Write Operation in Motorola mode
1
0
1
Read operation in both modes
1
1
0
Write operation in Intel mode
1
1
1
No operation
In Intel environment, access operations need CS active, a read one with RD active, a
write one with WR active. If TSS461C is the single peripheral in the processor space,
CS can be wired to VCC.
In Motorola environment, the RD pin is wired to VSS and the access operations are
driven by CS (E). Contrary to Intel mode, CS (E) must never be wired to VCC even if the
TSS461C is alone.
To switch on-the-fly from one mode to the other, CS must be inactive.
Intel Mode
The Intel mode interface consists of 13 pins. 8 pins are the multiplexed address and
data bus, and the rest are the address strobe, the read and write commands, the chip
select and the interrupt request pins.
To access the memory locations in Intel mode, the processor must first assert a valid
address on the multiplexed address and data bus and drive the address strobe pin high.
When the required setup time has passed, the processor must drive the address strobe
low, and keep the address valid for the required hold time.
The processor must then either assert the data to be written on the address and data
bus, if a write is intended, or float the data bus for a read. The next step is to drive either
the write or read command pins low, according to the function required, and at the same
time drive the chip select pin high.
The TSS461C access cycle is then terminated by driving the chip select and command
pins low.
Note:
6
that the chip select pin may be driven high for the entire access cycle, and may also
remain high during and after the termination of the cycle.
TSS461C
4193G–AUTO–12/04
TSS461C
Figure 2. Intel Read and Write Cycles
ALE
AD[7:0]
ADDRESS
DATA TO BE
WRITTEN
ADDRESS
DATA
READ
RD
WR
CS
WRITE CYCLE
Motorola Mode
READ CYCLE
In Motorola mode, the WR pin becomes the R/W command, the RD pin must be connected to ground and the CS pin becomes the E strobe. There is no separate chip select
input. For example, if some external decoder is used, this decoder should not drive the
E input high unless the processors E output is high as well.
See Figure 3 for the Motorola read and write cycles. The main difference between Intel
and Motorola mode is that the timing in Intel mode is referenced to the command signals
(RD and WR), but in Motorola mode the reference is the E signal.
Figure 3. Motorola Read and Write Cycles
ALE
AD[7:0]
ADDRESS
DATA TO BE
WRITTEN
ADDRESS
DATA
READ
VSS (RD)
R/W (WR)
E (CS)
WRITE CYCLE
Interrupts
READ CYCLE
If an event occurs in the TSS461C that needs the attention of the processor, this will be
signalled on the active low, open-drain interrupt request pin. The events that create this
request are controlled by the internal registers.
Every time the microprocessor accesses any of the interrupt registers (addresses 0x08
to 0x0B), the INT pin will be released momentarily. This enables the TSS461C to work
with processors that either have edge or level sensitive interrupt inputs.
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4193G–AUTO–12/04
Reset
The reset is applied asynchronously regarding XTAL clock. It can be done either by the
RESET pin or by software. The RESET pin is a CMOS trigger input with a pull-down
resistor (110 kΩ). An external 1 µF capacitor to VCC provides to RESET pin an efficient
behavior.
The software reset is made through the GRES command bit of the Command Register
(0x03).
The two resets are ored, filtered and gauged. Then the internal reset, always asserted
asynchronously, enables the internal oscillator. Then it waits for eight clock periods for
the oscillator stability.
The different blocks of the TSS461C need to be turned on synchronously. So the
release of the internal reset is synchronous and a loose clock can let the TSS461C in
permanent reset after applying Reset.
8
TSS461C
4193G–AUTO–12/04
TSS461C
Oscillator
An oscillator is integrated in the TSS461C, and consists of an inverting amplifier which
the input is XTAL1 and the output XTAL2.
A parallel resonance quartz crystal or ceramic resonator must be connected to these
pins. As shown in Figure 1, two capacitors have to be connected from the crystal pins to
ground. The values of C1 depend on the frequency chosen and can be selected using
the graphic given in Figure 33.
If the oscillator is not used, then a clock signal must be fed to the circuit via the XTAL1
input.
Note, that this pin will behave as a CMOS level compatible Schmitt trigger input. In this
case, the XTAL2 output should be left unconnected. The oscillator also features a buffered clock output pin CKOUT. The signal on this pin is directly buffered from the XTAL1
input, without inversion.
There is one more pin used for the oscillator. The TEST/VSS pin is in fact its ground,
and unless this pin is firmly connected to ground, with decoupling capacitors, the oscillator will not operate correctly.
The test mode itself, i.e., when the TEST/VSS pin is held high, is only intended for factory use, and the functionality of this mode is not specified in any way.
Furthermore, it is subject to change without notice, the only exception is for incoming
inspection tests using the test program.
The clock signal is then fed to the clock generator generate all the necessary timing signals for the operation of the circuit. The clock generator is controlled by a 4-bit code
called the clock divider.
FXTAL1
F TSCLK = -----------------n × 16
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4193G–AUTO–12/04
Table 2. Clock Divider
8 MHz
10
6 MHz
4 MHz
2 MHz
Clock
Divider
Divide by
KTS/s
Kbits/s
KTS/s
Kbits/s
KTS/s
Kbits/s
KTS/s
Kbits/s
0000
1
500
400
375
300
250
200
125
100
0001
2
250
200
187.50
150
125
100
62.50
50
0010
4
125
100
93.75
75
62.50
50
31.25
25
0011
8
62.5
50
46.875+
37.5
31.25
25
15.625
12.5
0100
16
31.25
25
23.438
18.75
15.625
12.5
7.813
6.25
0101
32
15.625
12.5
11.718
9.375
7.813
6.25
3.906
3.125
0110
64
7.813
6.25
5.859
4.688
3.906
3.125
1.953
1.562
0111
128
3.906
3.125
500
400
1.953
1.562
166.666
133.333
1000
1.5
333.333
266.666
250
200
166.666
133.333
83.333
66.666
1001
3
166.666
133.333
125
100
83.333
66.666
41.666
33.333
1010
6
83.333
66.666
62.50
50
41.666
33.333
20.833
16.666
1011
12
41.666
33.333
31.25
25
20.833
16.666
10.416
8.333
1100
24
20.833
16.666
15.625
12.50
10.416
8.333
5.208
4.166
1101
48
10.416
8.333
7.813
6.25
5.208
4.166
2.604
2.083
1110
96
5.208
4.166
3.906
3.125
2.604
2.083
1.302
1.042
1111
192
2.604
2.083
1.953
1.5625
1.302
1.042
0.651
0.521
TSS461C
4193G–AUTO–12/04
TSS461C
VAN Protocol
Line Interface
There are three line inputs and one line output available on the TSS461C. The three
inputs are either programmed by software or automatically selected by a diagnosis
system.
The diagnosis system continuously monitors the data received through the three inputs,
and compares them and the selected bitrate. It then chooses the most reliable input
according to the results.
The data on the line is encoded according to the VAN standard ISO/11519-3. This
means that the TSS461C is using a two-level signal having a recessive (1) and a dominant (0) state. Furthermore, due to the simple medium used, all data transmitted on the
bus is also received simultaneously.
Consequently, the VAN protocol is a CSMA/CD (Carrier Sense Multiple Access/Collision Detection) protocol, allowing for continuous bitwise arbitration of the bus, and nondestructive (for the higher priority message) collision detection.
Figure 4. CSMA/CD Arbitration
Arbitration field
Node a: TxD
R
D
Node b: TxD
R
D
Node c: TxD
R
D
On Bus: DATA
2
Node a loses the arbitration
Node a releases the bus
3
1
Node b wins the arbitration
Node c loses the arbitration
Node c releases the bus
R
D
R: Recessive Level
D: Dominant Level
In addition to the VAN specification there is also a pulsed coding of the dominant and
recessive states. This mode is intended to be used with an optical or radio link. In this
mode, the dominant state for the transmitter is a low pulse, (2x prescaled clocks at the
beginning of the bit) and the recessive state is just a high level. When receiving in this
mode, it is not the state of the signal which is decoded, but the edges. Also, reception is
imposed on the RxD0 input, and the diagnosis system does not operate correctly.
In addition, in this mode there is an internal loopback in the circuit since optical transceivers are not able to receive the signal that they transmit.
11
4193G–AUTO–12/04
In Figure 5 the pulsed waveforms are shown. In Figure 8 through Figure 14 the low
"timeslots" (i.e. blocks of 16 prescaled clocks) should be replaced by the dominant
waveform showed in Figure 5, to obtain the correct representations for pulsed coding.
Figure 5. State Encoding
VAN BUS
SEQUENCE
NORMAL OR PULSED RECESSIVE ST ATE
VAN BUS
SEQUENCE
NORMAL DOMINANT STATE
VAN BUS
SEQUENCE
PUSED DOMINANT STATE
NUMBER OF
PRESCALED
CLOCKS
VAN Frame
0
2
4
6
8
10
14
12
16
Figure 6. VAN Bus Frame
SOF
Identifier
Field
Command
EXT
RAK
R/W
RTR
Data
Field
Frame
Check
Sum
EOD
ACK
EOF
The VAN bus supports three different module (unit) types:
1. The Autonomous module, which is a bus master. It can transmit Start Of Frame
(SOF) sequences, it can initiate data transfers and can receive messages.
2. The Synchronous access module. It cannot transmit SOF sequences, but it can
initiate data transfers and can receive messages.
3. The Slave module, which can only transmit using an in-frame mechanism and
can receive messages.
Figure 7. Hierarchical Access Methods
Autonomous
Rank 0
SOF
ID
COM
DATA
FCS
EOD ACK
EOF
COM
DATA
FCS
EOD ACK
EOF
DATA
FCS
EOD ACK
EOF
Synchronous
Rank 1
ID
Rank 16
12
RTR
Slave
TSS461C
4193G–AUTO–12/04
TSS461C
Figure 6 shows a normal VAN bus frame. It is initiated with a Start of Frame (SOF)
sequence shown in Figure 8. The SOF can only be transmitted by an autonomous module. During the preamble, the TSS461C will synchronize its bit rate clock to the data
received.
Figure 8. Framing Sequences
VAN BUS
START
SYNC
PREAMBLE
SEQUENCE
START OF FRAME
VAN BUS
END OF
DATA
ACK
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
0
16
32
48
END OF FRAME
64
80
96
112 128 144
160 176 192
When the complete SOF sequence has been transmitted or received, the circuit will
start the transmission or reception of the identifier field.
All data on the VAN bus, including the identifier and Frame Check Sum (FCS), are
transmitted using enhanced Manchester code.
In enhanced Manchester code, three NRZ bits are transmitted first followed by one
Manchester bit, then three more NRZ bits followed by one Manchester bit and so on.
Since the high state is recessive and the low state is dominant, the bus arbitration can
be done. If a module wants access to the bus, it must first listen to the bus during one
full End of Frame (EOF) and one full Inter Frame Spacing (IFS) period, to determine
whether the bus is free or not (i.e., no dominant states received).
Figure 9. Data Encoding
VAN BUS
SEQUENCE
NRZ 0
VAN BUS
SEQUENCE
NRZ 1
MANCHESTER 0
VAN BUS
SEQUENCE
MANCHESTER 1
NUMBER OF
PRESCALED
CLOCKS
0
8
16
24
32
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4193G–AUTO–12/04
The IFS is defined to be a minimum of 64 prescaled clocks periods. The TSS461C,
accepts an IFS of zero prescaled clocks for the reception only of a SOF sequence.
Once the bus is free, the module must now, if it is an autonomous module emits a SOF
sequence or, if it is a synchronous access module, wait until it detects a preamble
sequence.
Until this point there can be several modules transmitting on the bus, and there is no
possibility of knowing if this is the case or not. Therefore, the first field in which arbitration can be performed is the identifier field. Since the logical zeroes on the bus are
dominant, and all data is transmitted with the most significant bit (MSB) first, the first
module to transmit a logical zero on the bus will be the prioritized module, i.e., the message that is tagged with the lowest identifier will have priority over the other messages.
However it is possible that two messages transmitted on the bus will have the same
identifier. The TSS461C therefore, continues the arbitration of the bus throughout the
whole frame. In addition, if the identifier in transmission has been programmed for
reception as well, it transmits and receives messages simultaneously, right up till the
Frame Check Sequence (FCS). Only then, if the TSS461C has transmitted the whole
message. It discards the message received. Arbitration loss in the FCS field is considered as a CRC error during transmission.
This feature is called full data field arbitration, and it enables the user to extend the identifier. For instance, it can be used to transmit the emitting modules address in the first
bytes of the data field, thus enabling the identifier to specify the contents of the frame
and the data field to specify the source of the information.
The identifier field of the VAN bus frame is always 12 bits long, and it is always followed
by the 4-bit command field:
•
The first bit of the command is the extension bit (EXT). This bit is defined by the
user on transmission and is received and retained by the TSS461C. To conform with
the standard, it should be set to 1 (recessive) by the user, else the frame is ignored
without any IT generation.
•
The second bit is the request ACKnowledge bit (RAK). If this bit is a logical one, the
receiving module must acknowledge the transfer with an in-frame
acknowledgement in the ACK field. If it is set to logical zero, then the ACK field must
contain an acknowledge absent sequence.
•
The third bit is the Read/Write bit (R/W). This bit indicates the direction of the data in
a frame.
•
–
If set to zero it is a "write" message, i.e. data transmitted by one module to
be received by another module.
–
If it is set to one it implies a "read" message, i.e., a request that another
module should transmit data to be received by the one that requested the
data (reply request message).
Last in the command field is the Remote Transmission Request bit (RTR). This bit is
a logical zero if the frame contains data and a logical one if the frame does not
contain data. In order to conform with the standard a received frame included the
combination R/W. RTR = 01 is ignored without any IT generation.
All the bits in the command field are automatically handled by the TSS461C, so the user
doesn’t need to be concerned for encoding and decoding these bits. The command bits
transmitted on the VAN bus are calculated from the current status of the active
message.
14
TSS461C
4193G–AUTO–12/04
TSS461C
After the command field comes the data field. This is just a sequence of bytes transmitted, MSB first. In the VAN standard, the maximum message length is set to 28 bytes,
but the TSS461C handles messages up to 30 bytes.
The next field is the FCS field. This field is a 15-bit CRC checksum defined by the following generator polynomial g(x) of order 15:
g(x) = x15 + x11 + x10 + x9 + x8 + x7 + x4 + x3 + x2 + 1
The division is done with a rest initialized to 0x7FFF, and an inversion of the CRC bits is
performed before transmission.
However, since the CRC is calculated automatically from the identifier, command and
data fields by the TSS461C, the user should not be concerned with the circuit. When the
frame check sequence has been transmitted, the transmitting module must transmit an
End Of Data (EOD) sequence, followed by the ACKnowledge field (ACK) and the End of
Frame sequence (EOF) to terminate the transfer.
Figure 10. Acknowledge Sequences
VAN BUS
SEQUENCE
POSITIVE ACKNOWLEDGE
VAN BUS
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
Frame Examples
ABSENT ACKNOWLEDGE
0
8
16
24
32
The frames transmitted on the VAN bus are generated by several modules, each supplying different parts of the message. Figure 11 through Figure 14 show the four frame
types specified in the VAN standard, and what module is generating the different fields.
•
The most straightforward frame is the normal data frame in Figure 11. Like all other
frames it is initiated with a SOF sequence. This sequence is generated by a bus
master (not shown in the figure).
•
During this frame, there is basically only one module transmitting with the exception
of the acknowledgement, generated by the receiving module if requested in the
RAK bit.
•
The reply request frame with immediate reply in Figure 12 is the only frame in which
a slave module can transmit data by filling it into the appropriate field.
•
The difference for the frame on the bus is that the R/W bit has changed state
compared to the normal frame.
•
This is a highly interactive frame where a bus master generates the SOF and the
initiator generates the identifier, the three first bits of the command, and the
acknowledge. The RTR bit, the data field, the frame check, the EOD and the EOF
are all generated by the replying module.
•
The reply request frame with deferred reply in Figure 13 is the same frame as the
reply request frame with immediate reply. But since the requested module does not
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4193G–AUTO–12/04
generate the RTR bit, the requesting module will continue with the frame check, the
EOD and the EOF.
•
During this frame, the requested module will only generate the acknowledge, and
only if this was requested by the initiator through the RAK bit.
•
Finally, the deferred reply frame in Figure 14, which is sent when a module has
prepared a reply for a reply request that has been received earlier.
This frame is similar to the normal data frame with the exception being the R/W bit
that has changed state.
Figure 11. Normal Data Frame
EOD
ACK
DATA
CRC
EOD
ACK
EOF
CRC
ACK
EOF
CRC
EOF
RECEIVING
Module
FRAME
on Bus
EOF
ACK
IDENTIFIER
CRC
EOD
SOF
DATA
ACK
IDENTIFIER
EOD
SOF
EXT
RAK
R/W
RTR
(*)
TRANSMITTING
Module
EXT
RAK
R/W
RTR
(*)
With Acknowlegment
EXT : Recessive from Transmitter
RAK: Recessive for acknowledge from Transmitter
R/W : Dominant from Transmitter
RTR : Dominant from Transmitter – (*) Manchester bit
ACK : Positive from Receiver because RAK is Recessive
SOF
IDENTIFIER
EXT
RAK
R/W
RTR
(*)
TRANSMITTING
Module
DATA
SOF
IDENTIFIER
EXT
RAK
R/W
RTR
(*)
Without Acknowlegment
DATA
RECEIVING
Module
FRAME
on Bus
EXT :
RAK:
R/W :
RTR :
ACK :
16
Recessive from Transmitter
Dominant for no acknowledge from Transmitter
Dominant from Transmitter
Dominant from T ransmitter – (*) Manchester bit
Absent from Transmitter and from Receiver because RAK is Dominant
TSS461C
4193G–AUTO–12/04
TSS461C
CRC
EOD
ACK
EOF
DATA
CRC
ACK
EOF
REQUESTED
Module
FRAME
on Bus
SOF
EXT :
RAK :
R/W :
RTR :
ACK :
IDENTIFIER
ACK
DATA
EOD
IDENTIFIER
RTR
(*)
SOF
EXT
RAK
R/W
RTR
(*)
REQUESTING
Module
EXT
RAK
R/W
RTR
(*)
Figure 12. Reply Request Frame with Immediate Reply
Recessive from Requestor
Recessive for acknowledge from Requestor
Recessive from Requestor
Recessive from Requestor and Dominant from Requestee (*) Manchester bit
Absent from Requestee and Positive from Requestor because RAK is Recessive
ACK
CRC
REQUESTED
Module
FRAME
on Bus
EOF
ACK
IDENTIFIER
ACK
SOF
CRC
EOD
IDENTIFIER
EOD
SOF
EXT
RAK
R/W
RTR
(*)
REQUESTING
Module
EXT
RAK
R/W
RTR
(*)
Figure 13. Reply Request Frame with Deferred Reply
EXT :
RAK :
R/W :
RTR :
ACK :
EOF
Recessive from Requestor
Recessive for acknowledge from Requestor
Recessive from Requestor
Recessive from Requestor – (*) Manchester bit
Absent from Requestor and Positive from Requestee because RAK is Recessive
17
4193G–AUTO–12/04
ACK
DATA
CRC
EOF
ACK
IDENTIFIER
CRC
EOD
SOF
DATA
ACK
IDENTIFIER
EOD
SOF
EXT
RAK
R/W
RTR
(*)
REPLYING
module
EXT
RAK
R/W
RTR
(*)
Figure 14. Deferred Reply Frame
RECEIVING
module
FRAME
EOF
on bus
EXT
RAK
R/W
RTR
ACK
18
:
:
:
:
Recessive from Replyer
Recessive for acknowledge from Replyer
Recessive from Replyer
Dominant from Replyer - (*) Manchester bit
: Absent from Replyer and Positive from Receiver because RAK is Recessive
TSS461C
4193G–AUTO–12/04
TSS461C
Diagnosis System
The purpose of the diagnosis system is to detect any short or open circuits on either the
DATA or DATA lines and to permit, if it is possible, to carry the communications on the
non-defective line.
The diagnosis system is based on the assumption that three separate line receivers are
connected to the VAN bus (see Figure 3):
•
One of the line receivers is connected in differential mode, sensing both DATA and
DATA signals, and is connected to the RxD0 input.
•
The other two line receivers are operating in single wire mode and are sensing only
one of the two VAN bus signals:
–
The line receiver sensing DATA is connected to RxD1
–
The line receiver sensing DATA is connected to RxD2
The diagnosis system analyzes and compares the data sent over both VAN lines. So,
the diagnosis system executes a digital filtering and transition analyses. In order to perform its investigation, three internal signals are generated, RI (Return to Idle), SDC
(Synchronous Diagnosis Clock) and TIP (Transmission In Progress).
One of four operating modes can be chosen to manage the results of the diagnosis
system.
Diagnosis States
If the diagnosis system finds a failure on any of the VAN bus signals, it changes from
nominal to degraded mode, and connects the line receiver not coupled to the failing signal to the reception logic.
When the diagnosis system finds that the failing signal is working again, it returns to
nominal mode and re-connects the differential line receiver to the reception logic.
A major error occurs when both the VAN bus signals fail.
Figure 15. Diagnosis States
Nominal
Major
Error
Degraded
Data
Degraded
Data
- Failure during the frame.
- Default of transitions on the valid input between 2 consecutive SDC rising edges.
- Protocol fault
- In specified selection mode, every RI pulse when an EOF is detected or through an active SDC.
- In automatic selection mode and SDC active, no failure sampled by 2 consecutive SDC rising edges.
- General reset.
19
4193G–AUTO–12/04
Status bits give permanent information on the diagnosis performed, whatever the programmed operating mode. This is encoded over three bits: Sa, Sb and Sc. Sa and Sb
bits indicate the four possible states of the VAN bus.
Table 3. Status Bits Sa and Sb
Sa
Sb
0
0
0
1
1
Notes:
1
0
1
Communication
Mode
Nominal
Fault
No fault on VAN bus
Status
Differential communication DATA and DATA
Mode
Degraded on DATA
Fault
Fault on DATA
Status
Communication on DATA
Mode
Degraded on DATA
Fault
Fault on DATA
Status
Communication on DATA
Mode
Major error
Fault
Fault on DATA and DATA
Status
No communication on DATA and DATA (attempt to
communicate alternatively on DATA then DATA every
SDC period.
1. Sc bit sets to 1 as soon as one of the three inputs (RXD2, RXD1, RXD0) differs from
the others in the input comparison analysis performed by the diagnosis system, S2 is
set.
2. The only way to reset this status bit is through the RI signal or a general reset.
Internal Operations
Digital Filtering
If several spurious pulses occur during one bit, the diagnosis for defective conductor
may occur. To avoid such errors, digital filters are implemented.
Filtering operation is based on sampling of the comparator output signals. A transition is
taken into account only if it is observed over five samples (1/16th of timeslot).
Transition Analyses
20
These analyses are continuously done on the effective edges on comparators after digital filtering.
•
Asynchronous diagnosis:
The asynchronous diagnosis is done by comparing the number of edges on DATA
and DATA.
If four edges are detected on one input and no edges on the other during the same
period, the second input is considered faulty and the diagnosis mode will change to
one of the degraded modes.
•
Synchronous diagnosis:
The synchronous diagnosis counts the number of edges on the data input
connected to the reception logic during one SDC period.
TSS461C
4193G–AUTO–12/04
TSS461C
If there are less than four edges during one SDC period, the diagnosis mode will
change to the major error mode.
•
Transmission diagnosis:
The transmission compares RxD1 and RxD2 inputs (through the input comparators
and the filters) with the data transmitted on TxD output.
At a time when the transmission logic generates a dominant (recessive transition),
the inputs can give different values. Taking into account the filtering delay, the bus
line seen as dominant is assumed to be correct, the other one, recessive, is
considered faulty. The diagnosis mode is changed to reflect that.
•
Protocol fault:
The protocol fault is detected by counting the number of consecutive dominant
timeslots.
If eight consecutive timeslots are dominant, the diagnosis mode will change to the
major error mode.
Generation of Internal
Signals
RI Signal (Return to Idle)
This signal is used to return to nominal mode in the three specified selection modes (see
Section “Diagnosis States” and Section “Programming Modes”). The RI signal is disabled in automatic selection mode.
The RI signal is a pulse generated when an EOF is detected. So, at the end of each
frame, regarding the diagnosis status bit Sa, Sb & Sc, the user can select its own
choice.
SDC Signal (Synchronous
Diagnosis Clock)
This time base is used by diagnosis system in automatic selection mode (see
Section “Programming Modes”) when no event is recorded on the bus.
The SDC is generated either by a special SDC divider connected to the timeslot clock,
or manually. The SDC clock period must be longer compared to the timeslot duration.
A typical SDC period should be greater than the maximum frame length appearing on
the VAN network.
TIP Signal (Transmission in
Progress)
This signal must be enabled to allow the transmission diagnosis (see Section “Transition
Analyses”).
The TIP turns on synchronously at the beginning of the transmission:
•
For asynchronous bus access, the beginning of SOF;
•
For synchronous bus access, the beginning of the identifier field; and
•
For a request of in frame reply, the RTR bit of the command field.
The TIP turns off synchronously at the end of the transmission:
•
after EOF;
•
after a losing of arbitration or a code violation detection; and
•
for a requester of in frame reply, when the arbitration is lost on RTR the bit.
This signal is not generated when the transmission logic only sends an ACK.
21
4193G–AUTO–12/04
Programming Modes
Four programming modes determine how to use the three different inputs and the diagnosis system.
•
3 specified selection modes
•
1 automatic selection mode
Table 4. Programming Modes
22
Ma
Mb
Operating Mode
0
0
Differential communication
0
1
Degraded communication on RxD2 (DATA)
1
0
Degraded communication on RxD1 (DATA)
1
1
Automatic selection according to the diagnosis status
TSS461C
4193G–AUTO–12/04
TSS461C
Registers
The TSS461C memory map consists of three different areas, the Control & Status registers, the Channel Registers and the Message Data (or Mailbox).
Mapping
Figure 16. Memory Map
0x78 to 0x7F (r/w)
Channel
13
Channel 13
0x70 to 0x77 (r/w)
Channel 12
0x68 to 0x6F (r/w)
Channel 11
0x60 to 0x67 (r/w)
Channel 10
0x58 to 0x5F (r/w)
Channel 9
0x50 to 0x57 (r/w)
Channel 8
0x48 to 0x4F (r/w)
Channel 7
0x40 to 0x47 (r/w)
Channel 6
0x38 to 0x3F (r/w)
Channel 5
0x30 to 0x37 (r/w)
Channel 4
0x28 to 0x2F (r/w)
Channel 3
0x20 to 0x27 (r/w)
Channel 2
0x18 to 0x1F (r/w)
Channel 1
0x10 to 0x17 (r/w)
Channel 0
0x0C to 0x0F
0x0B (w)
0x0A (r/w)
0x09 (r)
0x08
0x07 (r)
0x06 (r)
0x05 (r)
Reserved
Interrupt Reset
Interrupt Enable (0x80)
Interrupt Status (0x80)
Reserved
Last Error Status (0x00)
Last Message Status (0x00)
Transmit Status (0x00)
Line Status (0bx01xxx00)
0x04 (r)
Command (0x00)
0x03 (w)
Diagnosis
Control (0x00)
0x02 (r/w)
Transmit
Control
(0x02)
0x01 (r/w)
Line
Control
(0x00)
0x00 (r/w)
Register
Notes:
Data Byte 127
0xFF
0x7F (r/w)
0x7E (r/w)
ID_Mask [3..0]
ID_Mask [11..4]
0x7C & 0x7D
Reserved
Reserved
0x7B (r/w) Message Length + Status
0x7A (r/w) DRAK + Message Address
0x79 (r/w)
ID_TAG (lsb) + COM
0x78 (r/w)
ID_TAG (msb)
Channel 13 Registers
0x17 (r/w)
0x17 (r/w)
ID_Mask [3..0]
0x16 (r/w)
ID_Mask
[11..4]
ID_Mask [11..4]
0x14 & 0x15
Reserved
0x13 (r/w) Message Length + Status
0x12 (r/w) DRAK + Message Address
0x11 (r/w) ID_TAG [3..0] + COM
0x10 (r/w)
ID_TAG [11..4]
Channel 0 Registers
0x8C
0x8B
0x8A
0x89
Data Byte 12
Data Byte 11
Data Byte 10
Data Byte 9
0x88
0x87
0x86
0x85
Data Byte 8
Data Byte 7
Data Byte 6
Data Byte 5
0x84
0x83
Data Byte 4
Data Byte 3
Data Byte 2
Data Byte 1
Data Byte 0
0x82
0x81
0x80
Message
1. All the non-specified addresses between 0x00 and 0x7F are considered as absent.
2. (r) means read-only register.
(w) means write-only register.
(r/w) means read/write register.
3. Value after RESET is found after register name. If no value is given, the register is not initialized at RESET.
23
4193G–AUTO–12/04
Control and Status
Registers
Line Control Register (0x00)
CD[3:0] Clock Divider
7
6
5
4
3
2
1
0
MR3
MR2
MR1
MR0
VER2
VER1
VER0
MT
•
Read/write register.
•
Default value after reset: 0y00
•
reserved: Bit 2, this bit cannot be set by the user; a 0 must always be written to this
bit.
They control the VAN Bus rate through a Baud Rate generator according to the following formula:
FXTAL1
F TSCLK = -----------------n × 16
PC Pulsed CodeOne
The TSS461C will transmit and receive data using the pulsed coding mode (i.e optical
or radio link mode). The use of this mode implies communication via the RXD0 input
and the non-functionality of the diagnosis system.
Zero: (Default at Reset). The TSS461C will transmit and receive data using the
Enhanced Manchester code (RXD0, RXD1, RXD2).
IVTX
Invert TXD output.
IVRX
Invert RXD inputs.The user can invert the logical levels used on either the TXD output or
the RXD inputs in order to adapt to different line drivers and receivers.
One: A one on either of these bits will invert the respective signals.
Zero: (Default at Reset). The TSS461C will set TXD to recessive state in Idle mode and
consider the bus free (recessive states on RXD inputs).
Transmit Control Register
(0x01)
24
7
6
5
4
3
2
1
0
MR3
MR2
MR1
MR0
VER2
VER1
VER0
MT
•
Read/Write register
•
Default value after reset: 0x02
TSS461C
4193G–AUTO–12/04
TSS461C
MR[3:0]: Maximum Retries
These bits allow the user to control the amount of retries the circuit will perform if any
errors occurred during transmission.
Table 5. Retries
Note:
VER[2:0]: DLC Version After
Reset
MR [3:0]
Max Number of Retries
Max Number of Transmits
0000
0
1
0001
1
2
0010
2
3
0011
3
4
0100
4
5
0101
5
6
0110
6
7
0111
7
8
1000
8
9
1001
9
10
1010
10
11
1011
11
12
1100
12
13
1101
13
14
1110
14
15
1111
15
16+
Bus contention is not regarded as an error and an infinite number of transmission
attempts will be performed if bus contention occurs continuously.
•
000: TSS461A & B
•
001: TSS461C and TSS461C
These bits cannot be set by user; 001 must always be written to these bits.
MT: Module Type
The three different module types are supported (see Section “VAN Frame”):
One: The TSS461C is an autonomous module (Rank 0), an synchronous access module (Rank 1) or a slave module (Rank 16).
Zero: The TSS461C is an synchronous access module (Rank 1) or a slave module
(Rank 16).
Diagnosis Control Register
(0x02)
7
6
5
4
3
2
1
0
SDC3
SDC2
SDC1
SDC0
Ma
Mb
ETIP
ESDC
•
Read/Write register
•
Default value after reset: 0x00
25
4193G–AUTO–12/04
The diagnosis is discussed in detail in Section “Diagnosis States”.
SDC [3:0]: SDC Divider
•
In its four high order bits the user can program the SDC rate SDC [3:0]
•
In its two medium order bits the diagnosis system mode is controlled: M1, M0
•
In the two low order bits, the user controls if the SDC and TIP are to be generated
automatically ETIP, ESDC
The input clock is the times lot clock.
Table 6. System Diagnosis Clock Divider
Ma, Mb: Operating Mode
Command Bits
ETIP: Enable Transmission In
Progress
26
SDC Divider SDC [3:0]
Divide By
0000
64
0001
128
0010
256
0011
512
0100
1024
0101
2048
0110
4096
0111
8192
1000
16384
1001
32768
1010
65536
1011
131072
1100
262144
1101
524288
1110
1048576
1111
2097152
Table 7. Diagnosis System Command Bits
Ma
Mb
0
0
Forces the Communication on RxD0 (differential)
0
1
Forces the Communication on RxD2 (DATA)
1
0
Forces the Communication on RxD1 (DATA)
1
1
Automatic selection
One: Enable TIP generation
Zero: Disable TIP generation.
TSS461C
4193G–AUTO–12/04
TSS461C
•
ESDC: Enable System
Diagnosis Clock
The Transmission In Progress (TIP) tells the diagnostic system to enable
transmission diagnosis.
One: Enable SDC divider.
Zero: Disable SDC divider.
•
The Synchronous Diagnosis Clock (SDC) controls the cycle time of the
synchronous diagnosis.
Command Register (0x03)
GRES: General Reset
7
6
5
4
3
2
1
0
GRES
SLEEP
IDLE
ACTI
REAR
0
0
MSDC
•
Write only register.
•
Reserved: Bit 1, 2. These bits cannot be set by the user; a zero must always be
written to these bit.
•
If the circuit is operating at low bit rates, there might be a considerable delay
between the writing of this register and the performing of the actual command (worst
case 6 timeslots). The user must verify, by reading the Line Status Register (0x04),
that the commands have been performed.
The Reset circuit command bit performs, if set, exactly as if the external reset pin was
asserted. This command bit has its own auto-reset circuitry.
One: Reset active
Zero: Reset inactive
SLEEP: Sleep Command
If the user sets the Sleep bit, the circuit will enter sleep mode. When the circuit is in
sleep mode, all non-user registers are setup to minimize power consumption and the
oscillator is stopped. To exit from this mode, the user must set either the idle or activate
commands.
One: Sleep active
Zero: Sleep inactive
27
4193G–AUTO–12/04
IDLE: Idle Command
If the user sets the Idle bit, the circuit will enter idle mode. In idle mode the oscillator will
operate, but the TSS461C will not transmit or receive anything on the bus, and the TXD
output will be in three-state
One: Idle active
Zero: Idle inactive
ACTI: Activate Command
The Activate command will put the circuit in the active mode, i.e it will transmit
and
receive normally on the bus. When the circuit is in activate mode the TXD three-state
output is enabled.
One: Activate active
Zero: Activate inactive
REAR: Re-Arbitrate Command
This command will, after the current attempt, reset the retry counter and re-arbitrate the
messages to be transmitted in order to find the highest priority message to transmit.
One: Re-arbitrate active
Zero: Re-arbitrate inactive
MSDC: Manual System
Diagnosis Clock
Rather than using the SDC divider described in Section “Diagnosis Control Register
(0x02)”, the user can use the manual SDC command to generate a SDC pulse for the
diagnosis system.
This MSDC pulse should be high at least two timeslot clock.
Line Status Register (0x04)
7
6
5
4
3
2
1
0
x
SPG
IDG
Sc
Sb
Sa
TXG
RXG
Read only register.
•
Default value after reset: 0bx01xxx00.
•
This register reports the operation mode of the TSS461C in the Sleep an Idle bits
(Command Register located at address 0y03) as well as the diagnosis system
status bits S2 to S0 discussed in Section “Diagnosis System”.
SPG: Sleeping
IDG: Idling
Default mode at reset
Sa, Sb and Sc
Diagnosis system status bits
•
28
Sa and Sb
TSS461C
4193G–AUTO–12/04
TSS461C
Table 8. Diagnosis System Status Bits
•
Sb
Sa
Communication Indication
0
0
Nominal mode, differential communication
0
1
Degraded over DATA, fault on DATA
1
0
Degraded over DATA, fault on DATA
1
1
Major error, fault on DATA and DATA
Sc: As soon as one of the three inputs (RXD2, RXD1, RXD0) differs from the others
in the input comparison analysis perform by the diagnosis system, S2 is set.
The only way to reset this status bit is through the RI signal or a general reset.
TXG: Transmitting
If this status bit is active, it indicates that the TSS461C has chosen an identifier to transmit, and it will continue to make transmission attempts for this message until it succeeds
or the retry count is exceeded.
RXG: Receiving
The receiving indicates that there is activity on the bus.
Note:
For safe modification of active channel registers both bits should be inactive (except
"abort" command).
Transmission Status Register
(0x05)
7
6
5
4
3
2
1
0
NRT3
NRT2
NRT1
NRT0
IDT3
IDT2
IDT1
IDT0
•
Read only register.
•
Default value after reset: 0x00.
•
The transmission Status register contains the number of retries made up-to-date,
according to Table 3, and the channel currently in transmission.
NRT [3:0]: Number of Retries
Done in Transmission
IDT [3:0]: Channel Number
Currently in Transmission
Last Message Status Register
(0x06)
7
6
5
4
3
2
1
0
NRTR3
NRTR2
NRTR1
NRTR0
IDTR3
IDTR2
IDTR1
IDTR0
•
Read only register.
•
Default value after reset: 0x00.
•
This register is the same as the transmission status register. It contains the last
identifier number that was successfully transmitted, received or exceeded its retry
count.
If it was a successful transmission, the number of retries performed can be seen in
this register as well.
29
4193G–AUTO–12/04
NRTR [3:0]:
Number of retries done successfully in transmission. In case of reception NRTR[3:0] is
undefined.
IDTR [3:0]:
Channel number that was successfully transmitted, received or exceeded its retry count.
Last Error Status Register
(0x07)
BOC: Buffer Occupied
BOV: Buffer Overflow
7
6
5
4
3
2
1
0
x
BOC
BOV
x
FCSE
ACKE
CV
FV
•
Read only register.
•
Default value after reset: 0×00.
•
The Last Error Status Register contains the error code for the last transmission or
reception attempt. It is updated after each attempt, i.e. several error codes can be
reported during one single transmission (with several retries).
•
When one channel configured in “Reply request” mode has its “received” bit set
when it attempts to transmit its request.
•
BOC with the link capability between two channels sharing the same received buffer
is set when one channel has already set its “received” bit in its “Message length and
status Channel register” and a receive is attempted on the other one.
BOV indicates that the buffer length setup in the Channel Status Register was shorter
than the number of bytes received plus 1, therefore, some data got lost.
One: BOV active
Zero: BOV inactive
FCSE: Framing Check
Sequence Error
ACKE: Acknowledge Error
FCSE indicates a mismatch between the FCS received and the FCS calculated
One: FCSE active
Zero: FCSE inactive
ACKE indicates a physical violation or collision on ACK field of the frame when the
TSS463 is produced.
One: ACKE active
Zero: ACKE inactive
30
TSS461C
4193G–AUTO–12/04
TSS461C
Figure 17. ACKE Status Bit
DLC: Producer
EOD field
ACK field
Expected
ACKE = 0
RAK = 0
Received
ACKE = 1
Received
ACKE = 1
Received
ACKE = 1
RAK* = 1
*RAK: bit of the frame COMMAND field
EOD field
CV: Code Violation
ACK field
Expected
ACKE = 0
Received
ACKE = 1
Received
ACKE = 1
Received
ACKE = 1
CV indicates:
•
either a Manchester code violation (2 identical TS on Manchester bit), or a physical
violation (transmitted bit “dominant”, received bit “recessive”), on fields ID, COM,
DATA and CRC, or
•
a physical violation or collision on field “preamble” and the “recessive” bit of the “Star
Sync” field.
One: CV active
Zero: CV inactive
31
4193G–AUTO–12/04
FV: Frame Violation
FV indicates a physical violation or collision on ACK field of the frame when the TSS463
is consumed.
One: FV active
Zero: FV inactive
Figure 18. FV Status Bit
DLC: Consumer
EOD Field
ACK Field
Expected
FV = 0
Received
FV = 1
Received
FV = 1
Received
FV = 1
EOD Field
ACK Field
Expected
FV = 0
Received
FV = 1
Received
FV = 1
Received
FV = 1
Interrupt Status Register
(0x09)
7
6
5
4
3
2
1
0
RST
0
0
TE
TOK
RE
ROK
RNOK
•
Read only register.
•
Default value after reset: 0×80
RST: Reset interrupt
RE indicates that the circuit has detected a valid reset command via the RESET pin or
the reset command bit GRES. This interrupt cannot be disabled, since its enable bit is
set when a reset is detected.
TE: Transmit Error Status Flag
(or Exceeded Retry)
This flag is set only when the Max number of transmission (1 + MR [3:0]) is reached with
error of transmission.
Figure 19. Exceeded Retry with MR[3.0] = 3
1st TX
32
2nd TX
3rd TX
set TE
set CHER
set CHTx
TSS461C
4193G–AUTO–12/04
TSS461C
TOK: Transmit OK Status Flag
One: Status flag activated
Zero: No status flag.
RE: Receive Error Status Flag
One: Status flag activated
Zero: No status flag.
ROK: Receive “with RAK
(RAK=1)” OK Status Flag
One: Status flag activated
Zero: No status flag.
RNOK: Receive “with no RAK
(RAK=0)” OK Status Flag
One: Status flag activated
Zero: No status flag.
Interrupt Enable Register
(0x0A)
7
6
5
4
3
2
1
0
1
0
0
TEE
TOKE
REE
ROKE
RNOKE
•
Read/write register
•
Default value reset: 0x80
Note:
On reset the Reset Interrupt Enable bit is set to 1 instead of 0, as the general rule.
TEE: Transmit Error Enable
One: IT enabled.
Zero: IT disabled.
TOKE: Transmission OK Enable
One: IT enabled.
Zero: IT disabled.
REE: Reception Error Enable
One: IT enabled.
Zero: IT disabled.
ROKE: Reception “with RAK”
OK Enable
One: IT enabled.
Zero: IT disabled.
RNOKE: Reception “with no
RAK” OK Enable
One: IT enabled.
Zero: IT disabled.
Interrupt Reset Register
(0x0B)
7
6
5
4
3
2
1
0
RSTR
0
0
TER
TOKR
RER
ROKR
RNOKR
•
Write only register.
•
Reserved bit: 5 and 6. This bit cannot be set by user; a zero must always be written
to this bit.
33
4193G–AUTO–12/04
RSTR: Reset Interrupt Reset
One: Status flag reset
Zero: Status flag unchanged
TER: Transmit Error Status Flag
Reset
One: Status flag reset
Zero: Status flag unchanged
TOKR: Transmit OK Status Flag
Reset
One: Status flag reset
Zero: Status flag unchanged
RER: Receive Error Status Flag
Reset
One: Status flag reset
Zero: Status flag unchanged
ROKR: Receive “with RAK” OK
Status Flag Reset
One: Status flag reset
Zero: Status flag unchanged
RNOKR: Receive “with no RAK”
OK Status Flag Reset
One: Status flag reset
Zero: Status flag unchanged
6 TS
Set RXG
1 to 2 TS
Reset RXG, TXG
4 TS
Set TXG
BUS
ID+COM+DATA+CRC
ACK
SOF
EOD
Figure 20. Update of the Status Register
INT
Line Status Register (0x04)
4 TS
Write “IT Status Register”
Write “Last Error Register”
Write “Last Message Register”
Write “Message Status”
Channel Registers
Write “Message Length & Status Register”
There is a total of 14 channel register sets, each occupying 8 bytes for addressing simplicity, integrated into the circuit. Each set contains two 2 x 8-bit registers for the
indentifier tag, indentifier mask and command fields plus two 1 x 8-bit registers for DMA
pointers and message status.
The base_address of each set is: (0x10 + [0x08 * channel_number]).
When the TSS461C is reset either via the external reset pin or the general reset command, the channel registers are not affected. For example, on power-up of the circuit, all
the channel registers start with random values.
Due to this fact, the user should take care to initialize all the channel registers before
exiting from idle mode. The easiest way to disable a channel register is to set the
received and transmitted bits to 1 in the Message Length & Status Register.
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TSS461C
4193G–AUTO–12/04
TSS461C
Table 9. Channel Register Sets Map
Channel Number
From
To
Channel Number
From
To
6
0x40
0x47
13
0x78
0x7F
5
0x38
0x3F
12
0x70
0x77
4
0x30
0x37
11
0x68
0x6F
3
0x28
0x2F
10
0x60
0x67
2
0x20
0x27
9
0x58
0x5F
1
0x18
0x1F
8
0x50
0x57
0
0x10
0x17
7
0x48
0x4F
Table 10. Channel Register Set Structure
Identifier Tag and Command
Registers
Reg. Name
Offset
Bit 7
Bit 6
Bit 5
Bit 4
ID_MASK
0x07
ID_MASK
0x06
(no register)
0x05
x
x
x
x
(no register)
0x04
x
x
x
x
MESS_L/
STA
0x03
MESS_PTR
0x02
ID_TAG/
CMD
0x01
ID_TAG
0x00
Bit 3
Bit 2
Bit 1
Bit 0
x
x
x
x
x
x
x
x
x
x
x
x
CHER
CHTx
CHRx
RAK
RNW
RTR
ID_M [3:0]
ID_M [11:4]
M_L [4:0]
DRACK
M_P [6:0]
ID_T [3: 0]
EXT
ID_T [11:4]
The identifier tag and command registers are located at the base_address and
base_address + 1. It allows the user to specify the full 12-bit identifier field of the ISO
standard and the 4-bit command.
•
7
6
5
4
3
2
1
0
ID_T 3
ID_T 2
ID_T 1
ID_T 0
EXT
RAK
RNW
RTR
7
6
5
4
3
2
1
0
ID_T 11
ID_T 10
ID_T 9
ID_T 8
ID_T 7
ID_T 6
ID_T 5
ID_T 4
base_address
+ 0x01
base_address
+ 0x00
Read/Write registers.
35
4193G–AUTO–12/04
ID_T [11:0]: Identifier Tag
Upon a reception hit (i.e, a good comparison between the identifier received and an
identifier specified, taking the comparison mask into account, as well as a status and
command indicating a message to be received, the identifier tag bits value will be rewritten with the identifier bits actually received.
EXT, RAK, RNW & RTR: (See
Section “Retries, Rearbitrate
and Abort”)
No comparison will be done on the command bits, except on EXT bit. The RAK, RNW
and RTR bits will be written into the first byte of the Message upon a reception hit.
The RNW and RTR bits, as well as the status bits in the length and status register, must
be in a valid position for reception or transmission. If not, the message corresponding to
this identifier is considered as inactive or invalid.
The way of knowing if an acknowledge sequence was requested or not is to check the
first byte of the Message.
Message Pointer Register
The message pointer register at address (base_address + 0x02) is 8 bits wide. It indicates where, in the Message DATA RAM area, the message buffer is located.
•
DRAK: Disable RAK (Used in
'Spy Mode')
7
6
5
4
3
2
1
0
DRAK
M_P 6
M_P 5
M_P 4
M_P 3
M_P 2
M_P 1
M_P 0
base_address
+ 0x02
Read/Write register
In reception: whatever is the RAK bit of the incoming valid frame, no ACK answer will be
set. If the message was successfully received, an IT is set (ROK or RNOK).
In transmission: no action.
One: disable active, 'spy' mode.
Zero: disable inactive, normal operation.
M_P [6:0]: Message Pointer
Since the Message DATA RAM area base address is 0x80, the value in this register is
the offset from that address. If the message buffer length value is illegal (i.e. zero), this
register is redefined as being a link pointer, thus containing the channel number of the
channel that contains the actual message pointer, message length and received status.
However, the identifier, mask, error and transmitted status used will be the originally
matched channel. In any case, if a link is intended, the three high bits of M_P [6:0]
should be set to 0.
This allows several channels to use the same actual reception buffer in Message DATA
RAM, thus diminishing the memory usage.
Note that only 1 level of link is supported.
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TSS461C
4193G–AUTO–12/04
TSS461C
Message Length And Status
Register
The message length and status register at address (base_address + 0x03) is also 8 bits
wide. It indicates the length reserved for the message in the Message DATA RAM area.
•
M_L [4:0]: Message Length
7
6
5
4
3
2
1
0
M_L 4
M_L 3
M_L 2
M_L 1
M_L 0
CHER
CHTx
CHRx
base_address
+ 0x03
Read/Write register.
The 5 high bits of this register allow the user to specify either the length of the message
to be transmitted, or the maximum length of a message receivable in the pointed reception buffer.
Note that the first byte in this register does not contain data, but the length of the message received. This implies that the length value has to be equal to or greater than the
maximum length of a message to be received in this buffer (or the length of a message
to be transmitted) plus 1. Thus allowing a maximum length of 30 bytes and a minimum
length of 0 byte.
If the value of this field is illegal (i.e 0x00) then this message pointer is defined as being
a link (see section “Message Pointer Register” and Section “Linked Channels”).
M_L [4:0] = 0x00
Linked channel
M_L [4:0] = 0x01
Frame with no DATA field (*)
M_L [4:0] = 0x02
Frame with 1 DATA byte
-------
----------------------
M_L [4:0] = 0x1D
Frame with 28 DATA bytes
M_L [4:0] = 0x1E
Frame with 29 DATA bytes
M_L [4:0] = 0x1F
Frame with 30 DATA bytes
(*) Different of a reply request frame with no in-frame reply (deferred reply).
CHER: Channel Error Status
and Abort Command
As status, this bit is set by the TSS461C when error occurs in transmission or on a
received frame. The user must reset it.
To abort the transmission defined in the channel, this bit can be set to1 by the user (see
Section “Retries, Rearbitrate and Abort” and Section “Abort”).
CHTx: Channel Transmitted and
Transmit Enable Command
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4193G–AUTO–12/04
CHRx: Channel Received and
Receive Enable Command
The two low order bits of this register contain the message status. Together with the
RNW and RTR bits of the command register (base_address + 0x01), they define the
message type of this channel (seeSection “Messages Types”). As a general rule (see
Section “Abort”), the status bits are only set by the TSS461C, so the user must reset
them to perform a transmission (CHTx) or/and a reception (CHRx). The received and
transmitted bits are only set if the corresponding frame is without errors or if the retry
count has been exceeded.
Identifier Mask Registers
The Identifier Mask registers (base_address + 0x06 and base_address + 0x07) allow
bitwise masking of the comparison between the identifier received and the identifier
specified.
•
ID_M [11:0]: Identifier Mask
7
6
5
4
3
2
1
0
ID_M 3
ID_M 2
ID_M 1
ID_M 0
x
x
x
x
7
6
5
4
3
2
1
0
ID_M 11
ID_M 10
ID_M 9
ID_M 8
ID_M 7
ID_M 6
ID_M 5
ID_M 4
Read/Write registers
A value of 1 indicates comparison enabled.
A value of 0 indicates comparison disabled.
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TSS461C
4193G–AUTO–12/04
TSS461C
Mailbox
The mailbox contains all the messages received or to be transmitted. Each messages is
link to a channel. The Mailbox RAM area has 128 bytes and is mapped from 0x80 to
0xFF (see Section “Mapping”).
The message (or message buffer) is composed of:
•
1 byte of message status (only used in receiving)
•
Bytes of data. These data are the bytes of the DATA field of the frame with the same
organization.
The message is pointed by the Message Pointer Register of the channel, the length of
the message is given by the Message Length & Status Register of the channel
(Section “Message Pointer Register” and Section “Message Length And Status Register”). This area is a pure RAM, it contains a random value after reset.
Figure 21. Message Buffer Structure for Reception
Message Length & Status Register
Message Pointer Register
CHER CHTx CHRx
( M_L >= n + 2 )
M_L [4..0]
M_P [6..0]
DRAK
Message
Received DATA n
M_P + 0x80 + n + 2
received DATA 0
Note:
DATA n
FCS
ACK
DATA 0
M_P + 0x80
EOD
ID [11..0]
RTR
SOF
EXT
RAK
RNW
RAK RNW RTR
M_L [4..0] = n+1
receivedreceivedreceived
received
EOF
Received DATA Frame, immediate or deffered reply
39
4193G–AUTO–12/04
Figure 22. Message Buffer Structure for Transmission
Message Length & Status Register
Message Pointer Register
CHER CHTx CHRx
M_L [4..0]
DATA n
transmitted
DATA 0
M_P + 0x80 + n + 2
RTR
RNW
EXT
RAK
ID [11..0]
M_P + 0x80
DATA 0
DATA n
FCS
ACK
transmitted
EOD
( M_L >= n + 2 )
Message
(nothing)
SOF
M_P [6..0]
DRAK
EOF
Transmitted DATA Frame
Message Status (Pointed
by: Message Pointer
Register)
7
6
5
4
3
2
1
0
RRAK
RRNW
RRTR
RM_L4
RM_L3
RM_L2
RM_L1
RM_L0
(no significant value in case of message to be transmitted)
RRAK: Received RAK Bit
This bit is the RAK bit coming from the COM field of the received frame.
RRNW: Received RNW Bit
This bit is the RNW bit coming from the COM field of the received frame.
RRTR: Received RTR Bit
This bit is the RTR bit coming from the COM field of the received frame.
RM_L[4:0]: Message Length of
the Received Frame
If the DATA field of the received frame included DATA0 to DATAn, RM_L[4:0] = n+1,
even if the reserved length (Message Length & Status Register) is larger.
40
TSS461C
4193G–AUTO–12/04
TSS461C
Figure 23. Message Status Updating
Frame Type
Node x
Communication
I, P
Node A
C
Data Frame
Immediate
Reply
Deferred
Reply
Message Status on Node A after IT(*)
I, C
RAK
RNW
RTR
RAK
RNW
RTR
RAK
RNW
RTR
P
I, C
C
Deferred
Reply
Previous
Value
P
Previous
Value
I, P
Data Frame
Immediate
Reply
Length
previous values
P
I, C
P
RAK
RNW
RTR
Length
RAK
RNW
RTR
Length
I, C
P: Producer
I: Initiator
C: Consumer
(*) After IT ROK or RNOK. In case of IT RE, the values can be erroneous.
Message Data (String
Pointed by: Message
Pointer Register + 1)
7
6
5
4
3
2
1
0
---
---
-- - -
---
DATAn
---
---
---
--DATA0
DATA0 is the first received (or transmitted) byte, DATAn is the last one.
Notes:
1. If the length reserved (in the message length & status register) for an incoming frame
is 2 bytes greater or more, the TSS461C will write the 2 bytes of the CRC field in the
message string just after DATAn.
Because the VAN frame does not contain a message length, the only way for the
component to know the length of the DATA field is either the message length register
value, or the EOD field detection. When the reserved length is too large, at the
moment when it detects the EOD, the TSS461C has already written the 2 bytes of the
CRC field, considering these bytes as normal DATA.
2. The Mailbox RAM area is a circular buffer. The next location after 0xFF is 0x80.
41
4193G–AUTO–12/04
Messages Types
There are 5 basic message types defined in the TSS461C. Two of them (transmit and
receive message types) correspond to the normal frame, and the rest correspond to the
different versions of reply frames.
Transmit Message
RNW
RTR
CHTx
CHRx
Initial Setup
0
0
0
Don’t Care
After Transmission
0
0
1
Unchanged
To transmit a normal data frame on the VAN bus, the user must program an identifier as
a Transmit Message. The TSS461C will then transmit this message on the bus until it
has succeeded or the retry count is exceeded.
Receive Message
RNW
RTR
CHTx
CHRx
Initial Setup
0
1
Don’t Care
0
After Transmission
0
1
Unchanged
1
The opposite of the transmit message type is the Receive Message type. This message
type will not generate any frames on the bus. Instead, it will listen to the bus until a
frame passes that matches its identifier, with the mask taken into account, and then
receive the data in that frame.
The data received will be stored in the message buffer and the length of the message
received is stored in the first byte of the message buffer.
The actual identifier received is stored in the identifier register itself. This identifier may
differ from the identifier specified in the register due to the effect of the mask register.
Normally, this should not interfere with the next identifier comparison since the bits that
may differ are masked via the mask register.
Reply Request Message
RNW
RTR
CHTx
CHRx
Initial Setup
1
1
0
0
After Transmission
(Waiting for reply)
1
1
1
0
After Reception
(of reply)
1
1
1
1
The Reply Request Message type is a demand to transmit on the VAN bus a reply
request. When this message type is programmed, three things can happen.
First, no other modules on the bus responded with an in-frame reply, in this case the
TSS461C will set the message type to the after transmission state. When this message
type is programmed, the TSS461C will listen on the bus for a deferred reply frame
matching this identifier, without transmitting the reply request.
42
TSS461C
4193G–AUTO–12/04
TSS461C
Second, another module on the bus replies with an in-frame reply. In this case the message type will pass immediately into the after reception state, without passing the after
transmission state.
Reply Request Message Without Transmission
RNW
RTR
CHTx
CHRx
Initial Setup
1
1
Don’t Care
0
After Reception
1
1
Unchanged
1
Third, the TSS461C has not yet started to transmit the reply request, when another
module either requests a reply, and gets it, or transmits a deferred reply. Warning! This
should be avoided as it may result in an illegal message type (Illegal reply Request).
Immediate Reply Message
RNW
RTR
CHTx
CHRx
Initial Setup
1
0
0
0
After Transmission
1
0
1
1
The immediate Reply Message will attempt to transmit an in-frame reply, using the data
in the message buffer. A deferred Reply Message is shown below.
Deferred Reply Message
RNW
RTR
CHTx
CHRx
Initial Setup
1
0
0
1
After Reception
(of Reply Request)
1
0
1
1
This message type will immediately transmit a deferred reply frame.
Reply Request Detection Message
RNW
RTR
CHTx
CHRx
Initial Setup
1
0
1
0
After Reception
1
0
1
1
Finally, there is the Reply Request Detector Message type. Its purpose is to receive a
reply request frame and notify the processor, without transmitting an in-frame reply.
Inactive Message
RNW
RTR
CHTx
CHRx
Recommended
Don’t Care
Don’t Care
1
1
After Transmission
0
0
1
Don’t care
After Reception
0
1
Don’t Care
1
Illegal Reply Request
1
1
0
1
The table above shows all inactive messages types. The last combination will transmit a
reply request, but will not receive the reply since its buffer is tagged as occupied.
43
4193G–AUTO–12/04
Priority Among the
Different Channels
The priority handling on the VAN bus is already explained in the Line Interface section.
The priorities for the messages in the TSS461C is, however, slightly different.
For instance, it's possible that an identifier matches two or more of the identifiers programmed into the registers. In this case, it is the lowest identifier number that has
priority. i.e., if both identifier 5 and 10 match the identifier received, it is the identifier 5
that will receive the message.
However, since the identifier 5 will become an inactive message when it has received
the frame, the next time the same identifier is seen on the bus, the corresponding data
will be received by identifier 10.
The same is valid for messages to be transmitted, i.e., if two or more messages are
ready to be transmitted, it is the one with the lowest identifier number that will get
priority.
44
TSS461C
4193G–AUTO–12/04
TSS461C
Retries, Rearbitrate
and Abort
Retries and rearbitrate commands are located, in the Transmit Control Register and in
the Command Register, respectively. An abort command is located in each channel register set, in the Message Length & Status Register (base_address + 0x03). These three
commands are available only when the TSS461C is producer.
Figure 24. Transmit Function
Activate
Ch. Enabled in
Xmit Mode?
no
yes
Select the lowest
Ch. number and
load”Max - retries”
Disable of
current Ch.
Abort activated
on current Ch.?
yes
no
Wait for bus free
(EOF+IFS= 12 Timeslots)
Transmit frame
and wait for the end
Decrement
retry counter
abort
Abort required
on current Ch.
rearbitrate?
rearbitrate
no
yes
Retries
Retry needed?
no
The purpose of retries feature is to provide, the capability of retrying a transmit request
in case of failure, when a node tries to reach another node, either on normal DATA
frame or on REPLY REQUEST frame.
The maximum number of retries is programmable through MR[3:0] of the Transmit Control Register (0x01). When a channel is enable – bit CHTx = 0 of Message Length &
Status Register, a 4-bit counter is loaded with MR[3:0]. At each attempt, this counter will
be countdown. To 0, an IT TE is set in the Interrupt Status Register (0x09), and the
transmission is stopped.
MR[3:0] = 1 indicates 1 retry, hence 2 transmission attempts will be performed (see
Table 4). The number of retries performed, as well as the current channel number associated, can be read in the Transmission Status Register (0x05).
45
4193G–AUTO–12/04
The Last Error Status Register (0x07) informs about the trouble encountered:
•
•
Failure cases:
–
Code viol (CV error bit)
–
Acknowledge error (ACKE error bit)
–
CRC error (FCSE error bit)
It should be noticed that contention is considered as normal CSMA/CD protocol
and, therefore, is not taken into account in failure cases. So, an “infinite” number of
attempts can be performed if bus contention occurs continuously.
There is only one retry counter for all channels. When the user writes the Max_Retries
value, all channels start their transmission with this parameter.
Rearbitrate
The purpose of rearbitrate feature is to postpone a channel already in transmission in
order to authorize an higher priority (see Section “Priority Among the Different Channels”) message to be transmit.
Typical Example
•
Max_retries = 1 (2 transmissions attempts).
•
If Ch8 is in a the retry loop and the user wants to transmit the Ch5 without waiting
the end of the loop, the user can use the rearbitrate command.
•
Then, the TSS461C will wait the end of the current transmission, reload the retries
counter and enable the Ch5 to transmit.
•
At the end of this transmission Ch5, either when the attempt is successful or either
when the exceeded retry count is reached, the retries counter is reloaded and the
transmission is activated for the Ch8 again.
46
Set CHER & CHTx /Ch8,
and set ITTE
Ex: set FSCE status bit
Ex: FCS Error
(not seen by application)
Second attempt
Xmit Ch8
* (not seen by application means no IT generation)
Delay
Viol
(Retries - 1)
(Load Max-retries)
VCC
VCC
EOF+IFS
First attempt
Xmit Ch8
Xmit Ch5
First attempt
Xmit Ch8
Delay
V iol
Set CHTx/Ch5 & ITROK
(Load Max-retries)
Ex: FCS Error
* (not seen by application)
Rearbitrate
(Activate Ch5)
(Load Max-Retries)
Figure 25. Rearbitrate Example
stand-by
Delay
Viol
EOF+IFS: 8 + 4 Timeslots
Delay Viol: 12 Timeslots
TSS461C
4193G–AUTO–12/04
TSS461C
Set CHER & CHTx /Ch8,
and set ITTE
Ex: set FSCE status bit
Ex: FCS Error
(not seen by application)
(Retries - 1)
First Attempt
Xmit Ch8
* (not seen by application means no IT generation)
Second Attempt
Xmit Ch8
Delay
Viol
EOF+IFS
Xmit Ch5
First Attempt
Xmit Ch8
Delay
Viol
(Load Max-retries)
Set CHTx/Ch5 & ITROK
Idle command
(Load Max-retries)
Ex: FCS Error
* (not seen by application)
Rearbitrate
(Activate Ch5)
(Load Max-retries)
Figure 26. Idle and Rearbitrate Example
Idle
Delay
Viol
EOF+IFS: 8 + 4 Timeslots
Delay Viol: 12 Timeslots
If the user sets the idle bit anywhere (after rearbitrate), the idle mode is entered only at
the end of all the transmit attempts (for more information about idle command, see
Section “Activate, Idle and Sleep Modes”).
Disable Channel After
Rearbitrate
(Load Max-retries)
Ex: FCS Error
(not seen by application)
Disable Ch8(*)
(Activate Ch5)
Rearbitrate
(Load Max-retries)
Figure 27. Disable Channel After Rearbitrate Example
Delay
Viol
Ex: ACK Error
(not seen by application)
Set CHER & CHTx /Ch5,
and set ITTE
Ex: setACKE status bit
Delay
Viol
Delay
Viol
stand-by
(Retries - 1)
KO
Second attempt Xmit Ch5
Note:
First attempt
Xmit Ch5
First attempt
Xmit Ch8
Set CHTx/Ch5 & ITTOK
OK
EOF+IFS
stand-by
EOF+IFS: 8 + 4 Timeslots
Delay Viol: 12 Timeslots
(1) The disable is applied setting the CHTx/Ch8 bit to 1.
1. In this case, the TSS461C completes the current attempt (Ch8) and lets the transmission go to the new channel (Ch5 if validated); otherwise, it stops all attempts on the current channel.
47
4193G–AUTO–12/04
Abort
An abort command is dedicated to channels already enabled in transmission or in-frame
response. For example, this command can be used to break the retry procedure on one
channel.
Abort channel is done by setting the Error bit (CHER) in the Message Length & Status
Register (base_address + 0x02). This command is taken into account if the channel
aborted is not transmitted. When this abort command is really done, the TSS461C set to
1 the Transmitted bit (CHTx) of the Message Length & Status Register.
The abort mechanism is integrated into the transmit function. This means, abort, priority
and retries live together in the transmit function.
Set CHTx/Ch13
IT ROK
SetorCHTx
CHER/Ch6 &or IT RE
Set CHTx/Ch6 & ITROK
if Successful
Set CHTx/Ch6 & ITROK
if Successful
Set CHTx/Ch4 &ITROK
Abort Ch4 (during Xmit)
Abort Ch13 (before Xmit)
Activate
Abort Ch0 (before Xmit)
Set CHTx/Ch0
Ch s Initialization
Reset
Figure 28. Abort Example
48
Xmit Ch6
if Previously Fail
Xmit Ch6
if Previously Fail
Xmit Ch6
Xmit Ch4
12 Timeslots
TSS461C
4193G–AUTO–12/04
TSS461C
Activate, Idle and
Sleep Modes
Sleep, idle and activate commands are located in the Command Register (0x03). These
three commands are general commands for the TSS461C.
Idle and Activate
Commands
After reset, the TSS461C starts in idle mode. In this mode, the oscillator operates
(CKOUT pin active) but the circuit cannot transmit or receive anything on the VAN bus.
The TxD output (pin 18) is in three-state mode, a pull-up resistor must be provided
externally or by the line driver to avoid floating state on the VAN bus.
To activate the TSS461C, the user must set the activate bit (ACTI) and reset the idle bit
(IDLE).
Figure 29. Idle and Activate Timings
Idle Mode
Activate Mode
SOF
RxD
Activate Command
After Reset
SOF
TxD
8 TS
12 TS
3 TS
(max)
TS: Timeslot Period
Idle Mode
ACK
FCS
EOD
Activate Mode
RxD
Idle Command
INT
4 TS
5 TS
In both cases, the idle state can be verified by reading the Line Status register (0x04).
Sleep Command
If the user sets the sleep bit (SLEEP), the TSS461C enters in sleep mode, whatever are
the values of activate and idle bits. All non-user registers are setup to reduce the power
consumption and the internal oscillator is immediately stopped. However, all user registers (accessible by µP bus) are always available by the user
To exit from this mode, the user must set either the idle bit or the activate bit.
In a typical application (Figure 1) using the CKOUT feature (pin 12), if the TSS461C is
put in sleep mode, the clock provided to the microcontroller is stopped. So, the system
does not run and the only way to awake this application is an external reset.
49
4193G–AUTO–12/04
Linked Channels
The linkage feature allows two channels to share the same Message area, the message
pointer and the message length assumes the following property:
•
Zero value as message length (M_L [4:0] - base_address + 0x03) declares the
channel linked to another channel.
•
The number of this other channel is defined in the message pointer field (M_P [6:0]
- base_address + 0x02).
•
The pointer and the length values for the Message area are defined only once time,
in the register set of this other Channel.
Only one level of linkage can be created. For example, (see Figure 29) a Channel k can
be linked to the Channel i but not to Channel j, already defined as linked to Channel i.
All the others can be different between the two channels, for example the ID_Tag.
Figure 30. Linkage Mechanism
The Channel j linked
Channel i and j
....
share the same
Message area
to the Channel i
ID_Mask j (msb)
0x00
--- Message forChannels i & j ---
DATA n
CHER CHTx CHRx
i
DRAK
ID_Tag j (lsb)
EXT RAK RNW RTR
ID_Tag j (msb)
--- Channel i ---
Length = n+2
--- Channel j ---
ID_Mask j (lsb)
ID_Mask i (lsb)
ID_Mask i (msb)
Mess_Len = n+2CHER CHTx CHRx
Mess_Ptr
DRAK
ID_Tag i (lsb)
EXT RAK RNW RTR
DATA 0
Message Status
ID_Tag i (msb)
This Message Area sharing permits either optimizing the allocation of the 128 bytes of
DATA, performing some special communications between the different nodes of the
network.
50
TSS461C
4193G–AUTO–12/04
TSS461C
Electrical Characteristics
Absolute Maximum Ratings
Note:
Ambient temperature under Bias:
A = Automotive .................................................-40°C to 125°C
Storage Temperature ........................................-65°C to 150°C
Voltage on VCC to VSS .......................................... -0.5 to +7.0V
Voltage on any Pin to VSS ........................ -0.5V to VCC + 0.5V
DC Characteristics
Symbol
TA = -40°C to 125°C; VCC = 5V ± 10%; VSS = 0V
Parameter
Min
Max
Type
VIL
Input Low Voltage (except RESET and
XTAL1)
-0.5
0.8
V
VIH
Input High Voltage (except RESET and
XTAL1)
2.0
VCC+0.5
V
VIL1
Input Low Voltage (RESET and XTAL1)
-0.5
0.3·VCC
V
VIH1
Input High Voltage (RESET and XTAL1)
0.7 VCC
VCC+0.5
V
VOL
Output Low Voltage
0.4
V
VOH
Output High Voltage
IL
See Figure 2
IOL = 3.2 mA, VCC min
IOH = -3.2 mA, VCC min
0 < VIN < VCC
kΩ
0 < VIN < VCC
10
pF
Not tested
50
µA
(Note 1)
Power Supply Current
4
mA
(Notes 2, 4)
Idle or Active Mode
15
mA
(Notes 3, 4)
Input Pull-down Resistor
CIO
I/O Buffer Capacitance
ICCOP
Test Conditions
µA
RPD
1.
2.
3.
4.
5.
2.4
Input Leakage Current
ICCSB
Notes:
Stresses at or above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions exceeding those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions may affect
device reliability.
Power Supply Current
Sleep Mode
+5
110
Sleep Mode ICCSB is measured according to Figure 31 with a VSS Clock Signal.
Active mode ICCOP is measured at: XTAL = 1 MHz clock, VAN speed rate = 62.5 KTS/s.
Active mode ICCOP is measured at: XTAL = 16 MHz clock, VAN speed rate = 250 KTS/s.
ICC is a function of the Clock Frequency. Figure 32 displays a graph showing ICC versus Clock frequency.
RESET, RxD0, RxD1, RxD2 inputs.
51
4193G–AUTO–12/04
Figure 31. ICC
Icc
TXD
CLOCK SIGNAL
N.C.
Figure 32. ICC versus Clock Frequency at 250 KTimeslot/s
mA
12
11.5
11
10.5
MHz
2
52
4
6
8
TSS461C
4193G–AUTO–12/04
TSS461C
AC Characteristics
Microprocessor Interface
TA = -40°C to 125°C; VCC = 5V ± 10%; VSS = 0V
Symbol
TRESET
Characteristic
Min
Max
Unit
RESET High Pulse Width (For Power-up Reset)
15
ns
1
TLHLL
ALE High Pulse Width
10
ns
2
TAVLL
Address Valid to ALE Low Setup Time
10
ns
3
TLLAX
ALE Low to Address Invalid Hold Time
10
ns
4
TAVWL
Address Valid to Command Active Time
20
ns
5
TDVWH
Data Valid to Write Inactive Setup Time
10
ns
6
TWHDX
Write Inactive to Data Invalid Hold Time
12
ns
7
TWHLH
Write Inactive to ALE High Recovery Time
20
ns
8
TRLDV
Read Active to Data Valid Access Time
110
ns
9
TRHDZ
Read Inactive to Data Float Time
20
ns
10
TWHRLIZ
Write Inactive or Read Active to IRQ Float Time
90
ns
11
TIZIL
20
ns
IRQ Float Pulse Width
2
53
4193G–AUTO–12/04
Oscillator Characteristics
Figure 33. C2 versus Frequency
pF
200
100
33
1
Note:
External Clock Drive
Characteristics (XTAL1)
2
4
8
MHz
C1 (no capacitance needed) see Figure 1.
Symbol
Parameter
Min
Max
TCHCH
Oscillator Period
120
ns
TCHCX
High Time
20
ns
TCLCX
Low Time
20
ns
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
t CHCL
XTAL1
V IH
Unit
t CLCH
V IH
V IH
V IL
V IL
t CHCX
t CLCX
t CHCH
54
TSS461C
4193G–AUTO–12/04
TSS461C
Packaging Information
SO24
24
SO
MM
INCH
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
B
0.35
0.49
0.014
0.019
C
0.23
0.32
0.009
0.013
D
15.20
15.60
0.599
0.614
E
7.40
7.60
0.291
0.299
e
1.27
BSC
0.050
BSC
H
10.00
10.65
0.394
0.419
h
0.25
0.75
0.010
0.029
L
0.40
1.27
0.016
0.050
N
24
24
a
0°
0°
55
4193G–AUTO–12/04
Ordering Information
Part Number
Supply Voltage
Temperature
Range
Package
Packing
TSS461C
5V +10%
-40°C - +125°C
SO24
Tube
TSS461C:R
5V +10%
-40°C - +125°C
SO24
Tape & Reel
TSS461C-TDRZ(1)
5V +10%
-40°C - +125°C
SO24
Tube
Note:
56
1. These products are available in ROHS version.
TSS461C
4193G–AUTO–12/04
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