ATMEL ATF22V10C-10JI

Features
• Industry-standard Architecture
– Low-cost, Easy-to-use Software Tools
• High-speed, Electrically Erasable Programmable Logic Devices
– 5 ns Maximum Pin-to-pin Delay
• CMOS- and TTL-compatible Inputs and Outputs
– Latch Feature Holds Inputs to Previous Logic States
• Pin-controlled Standby Power (10 µA Typical)
• Advanced Flash Technology
•
•
•
•
– Reprogrammable
– 100% Tested
High-reliability CMOS Process
– 20-year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latch-up Immunity
Dual Inline and Surface Mount Packages in Standard Pinouts
PCI-compliant
True Input Transition Detection “Z” and “QZ” Version
Highperformance
EE PLD
ATF22V10C
ATF22V10CQ
Pin Configurations
See separate datasheet
for ATF22V10CZ and
ATF22V10CQZ options.
TSSOP
All Pinouts Top View
Pin Name
Function
CLK
Clock
IN
Logic Inputs
I/O
Bi-directional Buffers
GND
Ground
VCC
+5V Supply
PD
Power-down
CLK/IN
IN
IN
IN/PD
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
PLCC
IN
IN
CLK/IN
VCC*
VCC
I/O
I/O
4
3
2
1
28
27
26
25
24
23
22
21
20
19
12
13
14
15
16
17
18
5
6
7
8
9
10
11
Note:
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
DIP/SOIC
I/O
I/O
I/O
GND*
I/O
I/O
I/O
IN
IN
GND
GND*
IN
I/O
I/O
IN/PD
IN
IN
GND*
IN
IN
IN
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN/PD
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
For all PLCCs (except “-5”), pins 1, 8, 15 and 22 can be
left unconnected. However, if they are connected, superior performance will be achieved.
Rev. 0735P–PLD–01/02
1
Logic Diagram
Description
The ATF22V10C is a high-performance CMOS (electrically erasable) programmable
logic device (PLD) that utilizes Atmel’s proven electrically erasable Flash memory technology. Speeds down to 5 ns and power dissipation as low as 100 µA are offered. All
speed ranges are specified over the full 5V ± 10% range for industrial temperature
ranges, and 5V ± 5% for commercial temperature ranges.
Several low-power options allow selection of the best solution for various types of
power-limited applications. Each of these options significantly reduces total system
power and enhances system reliability.
Absolute Maximum Ratings*
Temperature under Bias .................................. -40°C to +85°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
during Programming .....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
1.
DC and AC Operating Conditions
Operating Temperature (Ambient)
VCC Power Supply
2
Commercial
Industrial
0°C - 70°C
-40°C - 85°C
5V ± 5%
5V ± 10%
ATF22V10C(Q)
0735P–PLD–01/02
ATF22V10C(Q)
Compiler Mode Selection
Synario
WINCUPL
Note:
PAL Mode
(5828 Fuses)
GAL Mode
(5892 Fuses)
Power-down Mode(1)
(5893 Fuses)
ATF22V10C (DIP)
ATF22V10C (PLCC)
ATTF22V10C DIP (UES)
ATF22C10C PLCC (UES)
ATF22V10C DIP (PWD)
ATF22V10C PLCC (PWD)
P22V10
P22V10LCC
G22V10
G22V10LCC
G22V10CP
G22V10CPLCC
1. These device types will create a JEDEC file which when programmed in ATF22V10C devices will enable the power-down
mode feature. All other device types have the feature disabled.
DC Characteristics
Symbol
Parameter
Condition
IIL
Input or I/O Low
Leakage Current
0 ≤ VIN ≤ VIL (Max)
IIH
Input or I/O High
Leakage Current
3.5 ≤ VIN ≤ VCC
ICC
ICC2
Power Supply Current,
Standby
Clocked Power Supply
Current
Min
Typ
Max
Units
-35.0
-10.0
µA
10.0
µA
C-5, 7, 10
Com.
85.0
130.0
mA
C-10
Ind.
90.0
140.0
mA
C-15
Com.
65.0
90.0
mA
C-15
Ind.
65.0
115.0
mA
CQ-15
Com.
35.0
55.0
mA
CQ-15
Ind.
35.0
70.0
mA
C-5, 7, 10
Com.
150.0
mA
C-10
Ind.
160.0
mA
C-15
Com.
70.0
90.0
mA
C-15
Ind.
70.0
90.0
mA
CQ-15
Com.
40.0
60.0
mA
CQ-15
Ind.
40.0
80.0
mA
VCC = Max
Com.
10.0
100.0
µA
VIN = 0, Max
Ind.
10.0
100.0
µA
-130.0
mA
VCC = Max,
VIN = Max,
Outputs Open
VCC = Max, Outputs Open,
f = 15 MHz
IPD
Power Supply Current,
PD Mode
IOS(1)
Output Short Circuit
Current
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC+0.75
V
VOL
VOH
Note:
Output Low Voltage
Output High Voltage
VOUT = 0.5V
VIN = VIH or VIL,
VCC = Min
VIN = VIH or VIL,
VCC = Min
IOL = 16 mA
Com.,
Ind.
0.5
V
IOL = 12 mA
Mil.
0.5
V
IOH = -4.0 mA
2.4
V
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
3
0735P–PLD–01/02
AC Waveforms (1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics(1)
-5
-7
-10
-15
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Units
tPD
Input or Feedback to Combinatorial
Output
1.0
5.0
3.0
7.5
3.0
10.0
3.0
15.0
ns
tCO
Clock to Output
1.0
4.0
2.0
4.5(2)
2.0
6.5
2.0
8.0
ns
tCF
Clock to Feedback
2.5
ns
tS
Input or Feedback Setup Time
tH
Hold Time
2.5
2.5
3.0
3.5
0
0
4.5
10.0
ns
0
0
ns
90.0
55.5
MHz
External Feedback 1/(tS + tCO)
142.0
Internal Feedback 1/(tS + tCF)
166.0
142.0
117.0
80.0
MHz
No Feedback 1/(tWH + tWL)
166.0
166.0
125.0
83.3
MHz
tW
Clock Width (tWL and tWH)
3.0
3.0
3.0
6.0
ns
tEA
Input or I/O to Output Enable
2.0
6.0
3.0
7.5
3.0
10.0
3.0
15.0
ns
tER
Input or I/O to Output Disable
2.0
5.0
3.0
7.5
3.0
9.0
3.0
15.0
ns
tAP
Input or I/O to Asynchronous Reset of
Register
3.0
7.0
3.0
10.0
3.0
12.0
3.0
20.0
ns
tAW
Asynchronous Reset Width
5.5
7.0
8.0
15.0
ns
tAR
Asynchronous Reset Recovery Time
4.0
5.0
6.0
10.0
ns
tSP
Setup Time, Synchronous Preset
4.0
4.5
6.0
10.0
ns
tSPR
Synchronous Preset to Clock
Recovery Time
4.0
5.0
8.0
10.0
ns
fMAX
Notes:
4
125.0
(3)
2.5
1. See ordering information for valid part numbers.
2. 5.5 ns for DIP package devices.
3. 111 MHz for DIP package devices.
ATF22V10C(Q)
0735P–PLD–01/02
ATF22V10C(Q)
Power-down AC Characteristics(1)(2)(3)
-5
-7
Min
Max
Min
-15
Symbol
Parameter
Min
tIVDH
Valid Input before PD High
5.0
7.5
10.0
15.0
ns
tGVDH
Valid OE before PD High
0
0
0
0
ns
tCVDH
Valid Clock before PD High
0
0
0
tDHIX
Input Don’t Care after PD High
5.0
7.0
10.0
15.0
ns
tDHGX
OE Don’t Care after PD High
5.0
7.0
10.0
15.0
ns
tDHCX
Clock Don’t Care after PD High
5.0
7.0
10.0
15.0
ns
tDLIV
PD Low to Valid Input
5.0
7.5
10.0
15.0
ns
tDLGV
PD Low to Valid OE
15.0
20.0
25.0
30.0
ns
tDLCV
PD Low to Valid Clock
15.0
20.0
25.0
30.0
ns
tDLOV
PD Low to Valid Output
20.0
25.0
30.0
35.0
ns
Notes:
Max
-10
Max
Min
Max
Units
ns
1. Output data is latched and held.
2. High-Z outputs remain high-Z.
3. Clock and input transitions are ignored.
Input Test Waveforms and Measurement Levels
Commercial Output Test Loads
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
Max
Units
Conditions
CIN
5
8
pF
VIN = 0V
COUT
6
8
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
5
0735P–PLD–01/02
Power-up Reset
The registers in the ATF22V10Cs are designed to reset during power-up. At a point
delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The
output state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. However, due to the asynchronous
nature of reset and the uncertainty of how VCC actually rises in the system, the following
conditions are required:
1. The VCC rise must be monotonic, and starts below 0.7V,
2. After reset occurs, all input and feedback setup times must be met before driving
the clock pin high, and
3. The clock must remain stable during tPR.
V R ST
POWER
t PR
REGISTERED
OUTPUTS
tS
tW
CLOCK
Preload of Registered
Outputs
The ATF22V10C’s registers are provided with circuitry to allow loading of each register
with either a high or a low. This feature will simplify testing since any state can be forced
into the registers to control test sequencing. A JEDEC file with preload is generated
when a source file with vectors is compiled. Once downloaded, the JEDEC file preload
sequence will be done automatically by most of the approved programmers after the
programming.
Electronic Signature
Word
There are 64 bits of programmable memory that are always available to the user, even if
the device is secured. These bits can be used for user-specific data.
Security Fuse Usage
Parameter
Description
Typ
Max
Units
tPR
Power-up Reset Time
600
1,000
ns
VRST
Power-up Reset Voltage
3.8
4.5
V
A single fuse is provided to prevent unauthorized copying of the ATF22V10C fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit
User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
Programming/
Erasing
6
Programming/erasing is performed using standard PLD programmers. See “CMOS PLD
Programming Hardware & Software Support” for information on software/programming.
ATF22V10C(Q)
0735P–PLD–01/02
ATF22V10C(Q)
Input and I/O Pinkeeper Circuits
The ATF22V10C contains internal input and I/O pin-keeper circuits. These circuits allow
each ATF22V10C pin to hold its previous value even when it is not being driven by an
external source or by the device’s output buffer. This helps to ensure that all logic array
inputs are at known valid logic levels. This reduces system power by preventing pins
from floating to indeterminate levels. By using pin-keeper circuits rather than pull-up
resistors, there is no DC current required to hold the pins in either logic state (high or
low).
These pin-keeper circuits are implemented as weak feedback inverters, as shown in the
Input Diagram below. These keeper circuits can easily be overdriven by standard TTLor CMOS-compatible drivers. The typical overdrive current required is 40 µA.
Input Diagram
I/O Diagram
7
0735P–PLD–01/02
Power-down Mode
The ATF22V10C includes an optional pin-controlled power-down feature. When this
mode is enabled, the PD pin acts as the power-down pin (Pin 4 on the DIP/SOIC packages and Pin 5 on the PLCC package). When the PD pin is high, the device supply
current is reduced to less than 100 mA. During power-down, all output data and internal
logic states are latched and held. Therefore, all registered and combinatorial output data
remain valid. Any outputs that were in an undetermined state at the onset of powerdown will remain at the same state. During power-down, all input signals except the
power-down pin are blocked. Input and I/O hold latches remain active to ensure that
pins do not float to indeterminate levels, further reducing system power. The powerdown pin feature is enabled in the logic design file. Designs using the power-down pin
may not use the PD pin logic array input. However, all other PD pin macrocell resources
may still be used, including the buried feedback and foldback product term array inputs.
PD pin configuration is controlled by the design file, and appears as a separate fuse bit
in the JEDEC file. When the power-down feature is not specified in the design file, the
IN/PD pin will be configured as a regular logic input.
Note:
8
Some programmers list the 22V10 JEDEC compatible 22V10C (no PD used) separately
from the non-22V10 JEDEC compatible 22V10CEX (with PD used).
ATF22V10C(Q)
0735P–PLD–01/02
ATF22V10C(Q)
Functional Logic Diagram ATF22V10C
9
0735P–PLD–01/02
ATF22V10C/CQ SUPPLY CURRENT VS.
SUPPLY VOLTAGE (T A = 25°C)
ATF22V10C/CQ NORMALIZED ICC VS.
TEMPERATURE
1.1
140.0
120.0
C-15
80.0
NORMALIZED I
I CC (mA)
100.0
CC
C-5, -7, -10
CQ-15
60.0
40.0
20.0
0.0
4.50
4.75
5.00
5.25
1.0
0.9
0.8
-40.0
5.50
0.0
ATF22V10C/CQ SUPPLY CURRENT VS.
INPUT FREQUENCY (V CC = 5V, TA = 25°C)
C-15
I OH (mA)
ICC (mA)
C-5, 7, 10
CQ-15
40.0
0.0
0.0
10.0
20.0
50.0
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
0.0
0.5
1.0
1.5
2.0
FREQUENCY (MHz)
2.5
3.0
3.5
4.0
4.5
5.0
VOH (V)
ATF22V10C/CQ OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (V OH = 2.4V)
0.0
-5.0
-10.0
-15.0
-20.0
-25.0
-30.0
-35.0
-40.0
-45.0
-50.0
ATF22V10C/CQ OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (V OL = 0.5V)
140.0
120.0
100.0
I OL (mA)
I OH (mA)
75.0
ATF22V10C/CQ OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
120.0
80.0
25.0
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
80.0
60.0
40.0
20.0
4.0
4.5
5.0
5.5
6.0
0.0
0.0
SUPPLY VOLTAGE (V)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
ATF22V10C/CQ INPUT CLAMP CURRENT VS.
INPUT VOLTAGE (V CC = 5V, TA = 35°C)
46.0
45.0
44.0
43.0
42.0
41.0
40.0
39.0
38.0
37.0
0.0
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
6.0
INPUT CURRENT mA)
I OL (mA)
ATF22V10C/CQ OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (V OL = 0.5V)
-20.0
-40.0
-60.0
-80.0
-100.0
-120.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
INPUT VOLTAGE (V)
10
ATF22V10C(Q)
0735P–PLD–01/02
ATF22V10C(Q)
ATF22V10C/CQ NORMALIZED TCO VS.
TEMPERATURE
ATF22V10C/CQ NORMALIZED TPD VS. VCC
1.1
CO
1.1
NORMALIZED T
NORMALIZED T
PD
1.2
1.0
0.9
0.8
4.50
4.75
5.00
5.25
1.0
0.9
0.8
-40.0
5.50
0.0
1.1
CO
1.2
NORMALIZED T
NORMALIZED T
CO
1.3
1.1
1.0
0.9
4.75
5.00
5.25
1.0
0.9
0.8
-40.0
5.50
0.0
SUPPLY VOLTAGE (V)
DELTA T PD (ns)
NORMALIZED T
SU
8.0
1.1
1.0
0.9
6.0
4.0
2.0
0.0
-2.0
4.75
5.00
5.25
0
5.50
50
100
150
200
250
300
OUTPUT LOADING (pF)
SUPPLY VOLTAGE (V)
ATF22V10C/CQ DELTA TPD VS.
NUMBER OF OUTPUT SWITCHING
ATF22V10C/CQ NORMALIZED T PD VS.
TEMPERATURE
0.0
DELTA T PD (ns)
PD
1.1
NORMALIZED T
75.0
ATF22V10C/CQ DELTA TPD VS.
OUTPUT LOADING
1.2
1.0
0.9
0.8
-40.0
25.0
TEMPERATURE (°C)
ATF22V10C/CQ NORMALIZED T SU VS. VCC
0.8
4.50
75.0
ATF22V10C/CQ NORMALIZED T SU VS.
TEMPERATURE
ATF22V10C/CQ NORMALIZED TCO VS. VCC
0.8
4.50
25.0
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
-0.1
-0.2
-0.3
-0.4
-0.5
0.0
25.0
TEMPERATURE (°C)
75.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
11
0735P–PLD–01/02
ATF22V10C/CQ DELTA TCO VS.
NUMBER OF SWITCHING
ATF22V10C/CQ DELTA TCO VS.
OUTPUT LOADING
0.0
8.0
-0.1
6.0
DELTA T CO (ns)
DELTA T CO (ns)
7.0
5.0
4.0
3.0
2.0
1.0
-0.3
-0.4
-0.5
-0.6
0.0
50
100
150
200
NUMBER OF OUTPUTS LOADING
12
-0.2
250
300
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
ATF22V10C(Q)
0735P–PLD–01/02
ATF22V10C(Q)
ATF22V10C(Q) Ordering Information
tPD (ns)
tS (ns)
tCO (ns)
Ordering Code
Package
5
3
4
ATF22V10C-5JC
28J
Commercial
(0°C to 70°C)
7.5
3.5
4.5
ATF22V10C-7JC
ATF22V10C-7PC
ATF22V10C-7SC
ATF22V10C-7XC
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
ATF22V10C-7JI
28J
ATF22V10C-10JC
ATF22V10C-10PC
ATF22V10C-10SC
ATF22V10C-10XC
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
ATF22V10C-10JI
ATF22V10C-10PI
ATF22V10C-10SI
ATF22V10C-10XI
28J
24P3
24S
24X
Industrial
(-40°C to 85°C)
ATF22V10C-15JC
ATF22V10C-15PC
ATF22V10C-15SC
ATF22V10C-15XC
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
ATF22V10C-15JI
ATF22V10C-15PI
ATF22V10C-15SI
ATF22V10C-15XI
28J
24P3
24S
24X
Industrial
(-40°C to 85°C)
ATF22V10CQ-15JC
ATF22V10CQ-15PC
ATF22V10CQ-15SC
ATF22V10CQ-15XC
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
ATF22V10CQ-15JI
ATF22V10CQ-15PI
ATF22V10CQ-15SI
ATF22V10CQ-15XI
28J
24P3
24S
24X
Industrial
(-40°C to 85°C)
10
4.5
15
10
15
10
6.5
8
8
Operation Range
Industrial
(-40°C to 85°C)
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
28J
28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3
24-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24S
24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
24X
24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
13
0735P–PLD–01/02
Packaging Information
28J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
E
D2/E2
B1
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
COMMON DIMENSIONS
(Unit of Measure = mm)
45˚ MAX (3X)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AB.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
12.319
–
12.573
D1
11.430
–
11.582
E
12.319
–
12.573
E1
11.430
–
11.582
D2/E2
9.906
–
10.922
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
14
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
28J
B
ATF22V10C(Q)
0735P–PLD–01/02
ATF22V10C(Q)
24P3 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
eC
eB
Notes:
1. This package conforms to JEDEC reference MS-001, Variation AF.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
MIN
NOM
MAX
A
–
–
5.334
A1
0.381
–
–
D
31.623
–
32.131
SYMBOL
E
7.620
–
8.255
E1
6.096
–
7.112
B
0.356
–
0.559
B1
1.270
–
1.551
L
2.921
–
3.810
C
0.203
–
0.356
eB
–
–
10.922
eC
0.000
–
1.524
e
NOTE
Note 2
Note 2
2.540 TYP
09/28/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
24P3
REV.
C
15
0735P–PLD–01/02
24S – SOIC
Dimensions in Millimeters and (Inches)
Controlling dimension: Inches
JEDEC STANDARD MS-013
0.51 (0.020)
0.33 (0.013)
7.60(0.2992)
10.65(0.419)
7.40(0.2914)
10.00(0.394)
PIN 1 ID
PIN 1
1.27(0.050) BSC
15.60(0.6141)
15.20(0.5985)
2.65(0.1043)
2.35(0.0926)
0.30(0.0118)
0.10(0.0040)
0.32(0.0125)
0º ~ 8º
0.23(0.0091)
1.27(0.050)
0.40(0.016)
04/11/2001
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC)
DRAWING NO.
REV.
24S
A
ATF22V10C(Q)
0735P–PLD–01/02
ATF22V10C(Q)
24X – TSSOP
Dimensions in Millimeter and (Inches)*
JEDEC STANDARD MO-153 AD
Controlling dimension: millimeters
0.30(0.012)
0.19(0.007)
4.48(0.176)
6.50(0.256)
4.30(0.169)
6.25(0.246)
PIN 1
0.65(0.0256)BSC
7.90(0.311)
1.20(0.047)MAX
7.70(0.303)
0.15(0.006)
0.05(0.002)
0.20(0.008)
0º ~ 8º
0.09(0.004)
0.75(0.030)
0.45(0.018)
04/11/2001
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline
Package (TSSOP)
DRAWING NO.
REV.
24X
A
17
0735P–PLD–01/02
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0735P–PLD–01/02
0M