ATMEL AT90S4414-8PC

Features
• AVR® - High Performance and Low Power RISC Architecture
• 118 Powerful Instructions - Most Single Clock Cycle Execution
• 4K bytes of In-System Reprogrammable Flash
•
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•
•
•
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– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles
256 bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
256 bytes Internal SRAM
32 x 8 General Purpose Working Registers
32 Programmable I/O Lines
Programmable Serial UART
SPI Serial Interface
VCC: 2.7 - 6.0V
Fully Static Operation
– 0 - 8 MHz, 4.0 - 6.0V
– 0 - 4 MHz, 2.7 - 4.0V
Up to 8 MIPS Throughput at 8 MHz
One 8-Bit Timer/Counter with Separate Prescaler
One 16-Bit Timer/Counter with Separate Prescaler
and Compare and Capture Modes
Dual PWM
External and Internal Interrupt Sources
Programmable Watchdog Timer with On-Chip Oscillator
On-Chip Analog Comparator
Low Power Idle and Power Down Modes
Programming Lock for Software Security
8-Bit
Microcontroller
with 4K bytes
In-System
Programmable
Flash
AT90S4414
Preliminary
Description
The AT90S4414 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the AT90S4414 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
The AVR core is based on an enhanced RISC architecture that combines a rich
instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
(continued)
Pin Configurations
Rev. 0840DS–07/98
Note: This is a summary document. For the complete 76 page
datasheet, please visit our web site at www.atmel.com or e1
mail at literature@atmel.com and request literature #0840D.
Block Diagram
Figure 1. The AT90S4414 Block Diagram
The AT90S4414 provides the following features: 4K bytes
of In-System Programmable Flash, 256 bytes EEPROM,
256 bytes SRAM, 32 general purpose I/O lines, 32 general
purpose working registers, flexible timer/counters with
compare modes, internal and external interrupts, a programmable serial UART, programmable Watchdog Timer
with internal oscillator, an SPI serial port and two software
selectable power saving modes. The Idle Mode stops the
CPU while allowing the SRAM, timer/counters, SPI port
and interrupt system to continue functioning. The power
down mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next
interrupt or hardware reset.
2
AT90S4414
The device is manufactured using Atmel’s high density
non-volatile memory technology. The on-chip In-System
Programmable Flash allows the program memory to be
reprogrammed in-system through an SPI serial interface or
by a conventional nonvolatile memory programmer. By
combining an enhanced RISC 8-bit CPU with In-System
Programmable Flash on a monolithic chip, the Atmel
AT90S4414 is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embedded control applications.
The AT90S4414 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, incircuit emulators, and evaluation kits.
AT90S4414
Pin Descriptions
VCC
Supply voltage
GND
Ground
Port A (PA7..PA0)
Port A is an 8-bit bidirectional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The
Port A output buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs
and are externally pulled low, they will source current if the
internal pull-up resistors are activated.
Port A serves as Multiplexed Address/Data input/output
when using external SRAM.
Port B (PB7..PB0)
Port B is an 8-bit bidirectional I/O pins with internal pull-up
resistors. The Port B output buffers can sink 20 mA. As
inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port B also serves the functions of various special features
of the AT90S4414 as listed on page 45.
Port C (PC7..PC0)
Port C is an 8-bit bidirectional I/O port with internal pull-up
resistors. The Port C output buffers can sink 20 mA. As
inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port C also serves as Address output when using external
SRAM.
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pull-up
resistors. The Port D output buffers can sink 20 mA. As
inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port D also serves the functions of various special features
of the AT90S4414 as listed on page 51.
RESET
Reset input. A low on this pin for two machine cycles while
the oscillator is running resets the device.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
ICP
ICP is the input pin for the Timer/Counter1 Input Capture
function.
OC1B
OC1B is the output pin for the Timer/Counter1 Output
CompareB function
ALE
ALE is the Address Latch Enable used when the External
Memory is enabled. The ALE strobe is used to latch the
low-order address (8 bits) into an address latch during the
first access cycle, and the AD0-7 pins are used for data
during the second access cycle.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an
inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 3.
Figure 2. Oscillator Connections
Figure 3. External Clock Drive Configuration
3
AT90S4414 Architectural Overview
The fast-access register file concept contains 32 x 8-bit
general purpose working registers with a single clock cycle
access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two
operands are output from the register file, the operation is
executed, and the result is stored back in the register file in one clock cycle. Six of the 32 registers can be used as
three 16-bits indirect address register pointers for Data
Space addressing - enabling efficient address calculations.
One of the three address pointers is also used as the
address pointer for the constant table look up function.
These added function registers are the 16-bits X-register,
Y-register and Z-register.
Figure 4. The AT90S4414 AVR Enhanced RISC Architecture
The ALU supports arithmetic and logic functions between
registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4
shows the AT90S4414 AVR Enhanced RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as
well. This is enabled by the fact that the register file is
assigned the 32 lowermost Data Space addresses ($00 $1F), allowing them to be accessed as though they were
ordinary memory locations.
The I/O memory space contains 64 addresses for CPU
peripheral functions as Control Registers, Timer/Counters,
4
AT90S4414
A/D-converters, and other I/O functions. The I/O Memory
can be accessed directly, or as the Data Space locations
following those of the register file, $20 - $5F.
The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a two stage pipeline. While
one instruction is being executed, the next instruction is
pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle.
The program memory is in-system In-System Programmable Flash memory.
With the relative jump and call instructions, the whole 2K
address space is directly accessed. Most AVR instructions
AT90S4414
have a single 16-bit word format. Every program memory
address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or inter-
rupts are executed). The 16-bit stack pointer SP is
read/write accessible in the I/O space.
The 256 bytes data SRAM can be easily accessed through
the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear
and regular memory maps.
Figure 5. Memory Maps
A flexible interrupt module has its control registers in the
I/O space with an additional global interrupt enable bit in
the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the
beginning of the program memory. The different interrupts
have priority in accordance with their interrupt vector position. The lower the interrupt vector address the higher priority.
5
AT90S4414 Register Summary
6
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
$3F ($5F)
$3E ($5E)
$3D ($5D)
$3C ($5C)
$3B ($5B)
$3A ($5A)
$39 ($59)
$38 ($58)
$37 ($57)
$36 ($56)
$35 ($55)
$34 ($54)
$33 ($53)
$32 ($52)
$31 ($51)
$30 ($50)
$2F ($4F)
$2E ($4E)
$2D ($4D)
$2C ($4C)
$2B ($4B)
$2A ($4A)
$29 ($49)
$28 ($48)
$27 ($47)
$26 ($46)
$25 ($45)
$24 ($44)
$23 ($43)
$22 ($42)
$21 ($41)
$20 ($40)
$1F ($3F)
$1E ($3E)
$1D ($3D)
$1C ($3C)
$1B ($3B)
$1A ($3A)
$19 ($39)
$18 ($38)
$17 ($37)
$16 ($36)
$15 ($35)
$14 ($34)
$13 ($33)
$12 ($32)
$11 ($31)
$10 ($30)
$0F ($2F)
$0E ($2E)
$0D ($2D)
$0C ($2C)
$0B ($2B)
$0A ($2A)
$09 ($29)
$08 ($28)
…
$00 ($20)
SREG
SPH
SPL
Reserved
GIMSK
GIFR
TIMSK
TIFR
Reserved
Reserved
MCUCR
Reserved
TCCR0
TCNT0
Reserved
Reserved
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1AH
OCR1AL
OCR1BH
OCR1BL
Reserved
Reserved
ICR1H
ICR1L
Reserved
Reserved
WDTCR
Reserved
Reserved
EEAR
EEDR
EECR
PORTA
DDRA
PINA
PORTB
DDRB
PINB
PORTC
DDRC
PINC
PORTD
DDRD
PIND
SPDR
SPSR
SPCR
UDR
USR
UCR
UBRR
ACSR
Reserved
Reserved
I
SP15
SP7
T
SP14
SP6
H
SP13
SP5
S
SP12
SP4
V
SP11
SP3
N
SP10
SP2
Z
SP9
SP1
C
SP8
SP0
19
20
20
INT1
INTF1
TOIE1
TOV1
INT0
INTF0
OCIE1A
OCF1A
-
-
-
-
-
-
OCIE1B
OCF1B
-
TICIE1
ICF1
-
TOIE0
TOV0
-
25
25
25
26
SRE
SRW
SE
SM
ISC11
ISC10
ISC01
ISC00
27
-
-
-
CS02
CS01
CS00
30
31
CTC1
CS12
PWM11
CS11
PWM10
CS10
33
34
35
35
36
36
36
36
Timer/Counter0 (8 Bit)
COM1A1
COM1A0
COM1B1
COM1B0
ICNC1
ICES1
Timer/Counter1 - Counter Register High Byte
Timer/Counter1 - Counter Register Low Byte
Timer/Counter1 - Output Compare Register A High Byte
Timer/Counter1 - Output Compare Register A Low Byte
Timer/Counter1 - Output Compare Register B High Byte
Timer/Counter1 - Output Compare Register B Low Byte
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
-
-
EEPROM Address Register
EEPROM Data Register
PORTA7
PORTA6
DDA7
DDA6
PINA7
PINA6
PORTB7
PORTB6
DDB7
DDB6
PINB7
PINB6
PORTC7
PORTC6
DDC7
DDC6
PINC7
PINC6
PORTD7
PORTD6
DDD7
DDD6
PIND7
PIND6
SPI Data Register
SPIF
WCOL
SPIE
SPE
UART I/O Data Register
RXC
TXC
RXCIE
TXCIE
UART Baud Rate Register
ACD
-
36
36
-
WDTOE
WDE
WDP2
WDP1
WDP0
-
-
-
-
-
-
PORTA5
DDA5
PINA5
PORTB5
DDB5
PINB5
PORTC5
DDC5
PINC5
PORTD5
DDD5
PIND5
PORTA4
DDA4
PINA4
PORTB4
DDB4
PINB4
PORTC4
DDC4
PINC4
PORTD4
DDD4
PIND4
PORTA3
DDA3
PINA3
PORTB3
DDB3
PINB3
PORTC3
DDC3
PINC3
PORTD3
DDD3
PIND3
EEMWE
PORTA2
DDA2
PINA2
PORTB2
DDB2
PINB2
PORTC2
DDC2
PINC2
PORTD2
DDD2
PIND2
EEWE
PORTA1
DDA1
PINA1
PORTB1
DDB1
PINB1
PORTC1
DDC1
PINC1
PORTD1
DDD1
PIND1
EERE
PORTA0
DDA0
PINA0
PORTB0
DDB0
PINB0
PORTC0
DDC0
PINC0
PORTD0
DDD0
PIND0
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
UDRE
UDRIE
FE
RXEN
OR
TXEN
CHR9
RXB8
TXB8
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
AT90S4414
39
40
40
41
54
54
54
56
56
56
61
61
61
63
63
63
46
45
45
49
49
50
52
53
AT90S4414
AT90S4414 Instruction Set Summary
Mnemonics
Operands
Description
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
ADC
Rd, Rr
Add with Carry two Registers
ADIW
Rdl,K
Add Immediate to Word
SUB
Rd, Rr
Subtract two Registers
SUBI
Rd, K
Subtract Constant from Register
SBC
Rd, Rr
Subtract with Carry two Registers
SBCI
Rd, K
Subtract with Carry Constant from Reg.
SBIW
Rdl,K
Subtract Immediate from Word
AND
Rd, Rr
Logical AND Registers
ANDI
Rd, K
Logical AND Register and Constant
OR
Rd, Rr
Logical OR Registers
ORI
Rd, K
Logical OR Register and Constant
EOR
Rd, Rr
Exclusive OR Registers
COM
Rd
One’s Complement
NEG
Rd
Two’s Complement
SBR
Rd,K
Set Bit(s) in Register
CBR
Rd,K
Clear Bit(s) in Register
INC
Rd
Increment
DEC
Rd
Decrement
TST
Rd
Test for Zero or Minus
CLR
Rd
Clear Register
SER
Rd
Set Register
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
IJMP
Indirect Jump to (Z)
RCALL
k
Relative Subroutine Call
ICALL
Indirect Call to (Z)
RET
Subroutine Return
RETI
Interrupt Return
CPSE
Rd,Rr
Compare, Skip if Equal
CP
Rd,Rr
Compare
CPC
Rd,Rr
Compare with Carry
CPI
Rd,K
Compare Register with Immediate
SBRC
Rr, b
Skip if Bit in Register Cleared
SBRS
Rr, b
Skip if Bit in Register is Set
SBIC
P, b
Skip if Bit in I/O Register Cleared
SBIS
P, b
Skip if Bit in I/O Register is Set
BRBS
s, k
Branch if Status Flag Set
BRBC
s, k
Branch if Status Flag Cleared
BREQ
k
Branch if Equal
BRNE
k
Branch if Not Equal
BRCS
k
Branch if Carry Set
BRCC
k
Branch if Carry Cleared
BRSH
k
Branch if Same or Higher
BRLO
k
Branch if Lower
BRMI
k
Branch if Minus
BRPL
k
Branch if Plus
BRGE
k
Branch if Greater or Equal, Signed
BRLT
k
Branch if Less Than Zero, Signed
BRHS
k
Branch if Half Carry Flag Set
BRHC
k
Branch if Half Carry Flag Cleared
BRTS
k
Branch if T Flag Set
BRTC
k
Branch if T Flag Cleared
BRVS
k
Branch if Overflow Flag is Set
BRVC
k
Branch if Overflow Flag is Cleared
BRIE
k
Branch if Interrupt Enabled
BRID
k
Branch if Interrupt Disabled
Operation
Flags
#Clocks
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Rd ← Rd v Rr
Rd ← Rd v K
Rd ← Rd ⊕ Rr
Rd ← $FF − Rd
Rd ← $00 − Rd
Rd ← Rd v K
Rd ← Rd • ($FF - K)
Rd ← Rd + 1
Rd ← Rd − 1
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← $FF
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PC ← PC + k + 1
PC ← Z
PC ← PC + k + 1
PC ← Z
PC ← STACK
PC ← STACK
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
Rd − Rr − C
Rd − K
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
None
None
None
None
None
I
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
2
2
3
3
4
4
1/2
1
1
1
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
7
Mnemonics
Operands
Description
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
LDI
Rd, K
Load Immediate
LD
Rd, X
Load Indirect
LD
Rd, X+
Load Indirect and Post-Inc.
LD
Rd, - X
Load Indirect and Pre-Dec.
LD
Rd, Y
Load Indirect
LD
Rd, Y+
Load Indirect and Post-Inc.
LD
Rd, - Y
Load Indirect and Pre-Dec.
LDD
Rd,Y+q
Load Indirect with Displacement
LD
Rd, Z
Load Indirect
LD
Rd, Z+
Load Indirect and Post-Inc.
LD
Rd, -Z
Load Indirect and Pre-Dec.
LDD
Rd, Z+q
Load Indirect with Displacement
LDS
Rd, k
Load Direct from SRAM
ST
X, Rr
Store Indirect
ST
X+, Rr
Store Indirect and Post-Inc.
ST
- X, Rr
Store Indirect and Pre-Dec.
ST
Y, Rr
Store Indirect
ST
Y+, Rr
Store Indirect and Post-Inc.
ST
- Y, Rr
Store Indirect and Pre-Dec.
STD
Y+q,Rr
Store Indirect with Displacement
ST
Z, Rr
Store Indirect
ST
Z+, Rr
Store Indirect and Post-Inc.
ST
-Z, Rr
Store Indirect and Pre-Dec.
STD
Z+q,Rr
Store Indirect with Displacement
STS
k, Rr
Store Direct to SRAM
LPM
Load Program Memory
IN
Rd, P
In Port
OUT
P, Rr
Out Port
PUSH
Rr
Push Register on Stack
POP
Rd
Pop Register from Stack
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
CBI
P,b
Clear Bit in I/O Register
LSL
Rd
Logical Shift Left
LSR
Rd
Logical Shift Right
ROL
Rd
Rotate Left Through Carry
ROR
Rd
Rotate Right Through Carry
ASR
Rd
Arithmetic Shift Right
SWAP
Rd
Swap Nibbles
BSET
s
Flag Set
BCLR
s
Flag Clear
BST
Rr, b
Bit Store from Register to T
BLD
Rd, b
Bit load from T to Register
SEC
Set Carry
CLC
Clear Carry
SEN
Set Negative Flag
CLN
Clear Negative Flag
SEZ
Set Zero Flag
CLZ
Clear Zero Flag
SEI
Global Interrupt Enable
CLI
Global Interrupt Disable
SES
Set Signed Test Flag
CLS
Clear Signed Test Flag
SEV
Set Twos Complement Overflow.
CLV
Clear Twos Complement Overflow
SET
Set T in SREG
CLT
Clear T in SREG
SEH
Set Half Carry Flag in SREG
CLH
Clear Half Carry Flag in SREG
NOP
No Operation
SLEEP
Sleep
WDR
Watchdog Reset
8
AT90S4414
Operation
Flags
#Clocks
Rd ← Rr
Rd ← K
Rd ← (X)
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
(X) ← Rr
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
(Z) ← Rr
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
(k) ← Rr
R0 ← (Z)
Rd ← P
P ← Rr
STACK ← Rr
Rd ← STACK
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
1
1
2
2
I/O(P,b) ← 1
I/O(P,b) ← 0
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Rd(n) ← Rd(n+1), n=0..6
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C←1
C←0
N←1
N←0
Z←1
Z←0
I←1
I←0
S←1
S←0
V←1
V←0
T←1
T←0
H←1
H←0
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
AT90S4414
Ordering Information
Speed (MHz)
Power Supply
Ordering Code*
Package
4
2.7 - 6.0V
AT90S4414-4AC
AT90S4414-4JC
AT90S4414-4PC
44A
44J
40P6
Commercial
(0°C to 70°C)
AT90S4414-4AI
AT90S4414-4JI
AT90S4414-4PI
44A
44J
40P6
Industrial
(-40°C to 85°C)
AT90S4414-8AC
AT90S4414-8JC
AT90S4414-8PC
44A
44J
40P6
Commercial
(0°C to 70°C)
AT90S4414-8AI
AT90S4414-8JI
AT90S4414-8PI
44A
44J
40P6
Industrial
(-40°C to 85°C)
8
4.0 - 6.0V
Operation Range
Package Type
44A
44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
44J
44-Lead, Plastic J-Leaded Chip Carrier (PLCC)
40P6
40-Lead, 0.600” Wide, Plastic Dual Inline Package (PDIP)
9
AT90S4414
Packaging Information
44A, 44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad
Flat Package (TQFP)
Dimensions in Millimeters and (Inches)*
44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
12.21(0.478)
SQ
11.75(0.458)
PIN 1 ID
0.45(0.018)
0.30(0.012)
0.80(0.031) BSC
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.045(1.14) X 30° - 45°
.032(.813)
.026(.660)
.695(17.7)
SQ
.685(17.4)
.500(12.7) REF SQ
.021(.533)
.013(.330)
.043(1.09)
.020(.508)
.120(3.05)
.090(2.29)
.180(4.57)
.165(4.19)
1.20(0.047) MAX
0˚
7˚
0.20(.008)
0.09(.003)
.630(16.0)
.590(15.0)
.656(16.7)
SQ
.650(16.5)
.050(1.27) TYP
10.10(0.394)
SQ
9.90(0.386)
.012(.305)
.008(.203)
.022(.559) X 45° MAX (3X)
0.75(0.030)
0.45(0.018)
0.15(0.006)
0.05(0.002)
*Controlling dimension: millimeters
40P6, 40-Lead, 0.600" Wide,
Plastic Dual Inline Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AC
2.07(52.6)
2.04(51.8)
PIN
1
.566(14.4)
.530(13.5)
.090(2.29)
MAX
1.900(48.26) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.110(2.79)
.090(2.29)
.012(.305)
.008(.203)
.065(1.65)
.041(1.04)
.630(16.0)
.590(15.0)
0 REF
15
.690(17.5)
.610(15.5)
10