ATMEL AT49LW040-33JC

Features
• Low Pin Count (LPC) BIOS Device
• Functions as Firmware Hub for Intel 810, 810E, 820, 840 Chipsets
• 8M or 4M Bits of Flash Memory for Platform Code/Data Storage
•
•
•
•
•
– Uniform, 64-Kbyte Memory Sectors
– Available in 8M Bits (AT49LW080) and 4M Bits (AT49LW040)
– Automated Byte-program and Sector-erase Operations
Two Configurable Interfaces
– Firmware Hub (FWH) Interface for In-System Operation
– Address/Address Multiplexed (A/A Mux) Interface for Programming during
Manufacturing
Firmware Hub Hardware Interface Mode
– 5-signal Communication Interface Supporting x8 Reads and Writes
– Read and Write Protection for Each Sector Using Software-controlled Registers
– Two Hardware Write-protect Pins: One for the Top Boot Sector, One for All Other
Sectors
– Five General-purpose Inputs, GPIs, for Platform Design Flexibility
– Operates with 33 MHz PCI Clock and 3.3V I/O
Address/Address Multiplexed (A/A Mux) Interface
– 11-pin Multiplexed Address and 8-pin Data Interface
– Supports Fast On-board or Out-of-system Programming
Power Supply Specifications
– VCC: 3.3V ± 0.3V
– VPP: 3.3V and 12V for Fast Programming
Industry-standard Packages
– (40-lead TSOP or 32-lead PLCC)
8-megabit and
4-megabit
Firmware Hub
Flash Memory
AT49LW080
AT49LW040
Description
The AT49LW080 and the AT49LW040 are Flash memory devices designed to be compatible with the Intel 82802AC and the Intel 82802AB Firmware Hub (FWH) devices
for PC-Bios Application. A feature of the AT49LW080/040 is the nonvolatile memory
core. The high-performance memory is arranged in eight (AT49LW040) or sixteen
(AT49LW080) 64-Kbyte sectors (see page 13).
Pin Configurations
TSOP
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
5
6
7
8
9
10
11
12
13
IC (VIL) [IC(VIH)]
GNDa [GNDa]
VCCa [VCCa]
GND [GND]
VCC [VCC]
INIT [OE]
FWH4 [WE]
RFU [RY/BY]
RFU [I/O7]
[I/O1] FWH1
[I/O2] FWH2
[GND] GND
[I/O3] FWH3
[I/O4] RFU
[I/O5] RFU
[I/O6] RFU
[A7] FGPI1
[A6] FGPI0
[A5] WP
[A4] TBL
[A3] ID3
[A2] ID2
[A1] ID1
[A0] ID0
[I/O0] FWH0
4
3
2
1
32
31
30
FGPI2 [A8]
FGPI3 [A9]
RST [RST]
VPP [VPP]
VCC [VCC]
CLK [R/C]
FGPI4 [A10]
PLCC
(NC) NC
[IC (VIH)] IC (VIL)
[NC] NC
[NC] NC
[NC] NC
[NC] NC
[A10] FGPI4
[NC] NC
[R/C] CLK
[VCC] VCC
[VPP] VPP
[RST] RST
[NC] NC
[NC] NC
[A9] FGPI3
[A8] FGPI2
[A7] FGPI1
[A6] FGPI0
[A5] WP
[A4] TBL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GNDa [GNDa]
VCCa [VCCa]
FWH4 [WE]
INIT [OE]
RFU [RY/BY]
RFU [I/O7]
RFU [I/O6]
RFU [I/O5]
RFU [I/O4]
VCC [VCC]
GND [GND]
GND [GND]
FWH3 [I/O3]
FWH2 [I/O2]
FWH1 [I/O1]
FWH0 [I/O0]
ID0 [A0]
ID1 [A1]
ID2 [A2]
ID3 [A3]
[ ] Designates A/A Mux Mode
[ ] Designates A/A Mux Mode
Rev. 1966C–FLASH–03/02
1
The AT49LW080/040 supports two hardware interfaces: Firmware Hub (FWH) for insystem operation and Address/Address Multiplexed (A/A Mux) for programming during
manufacturing. The IC (Interface Configuration) pin of the device provides the control
between the interfaces. The interface mode needs to be selected prior to power-up or
before return from reset (RST or INIT low to high transition).
An internal Command User Interface (CUI) serves as the control center between the two
device interfaces (FWH and A/A Mux) and internal operation of the nonvolatile memory.
A valid command sequence written to the CUI initiates device automation.
Specifically designed for 3V systems, the AT49LW080/040 supports read operations at
3.3V and sector erase and program operations at 3.3V and 12V VPP . The 12V V PP
option renders the fastest program performance which will increase factory throughput,
but is not recommended for standard in-system FWH operation in the platform. With the
3.3V VPP option, VCC and VPP should be tied together for a simple, low-power 3V design.
In addition to the voltage flexibility, the dedicated VPP pin gives complete data protection when VPP ≤ V PPLK. Internal V PP detection circuitry automatically configures the
device for sector erase and program operations. Note that, while current for 12V programming will be drawn from VPP, 3.3V programming board solutions should design
such that VPP draws from the same supply as VCC, and should assume that full programming current may be drawn from either pin.
Firmware Hub Interface
The Firmware Hub (FWH) interface is designed to work with the I/O Controller Hub
(ICH) during platform operation.
The FWH interface consists primarily of a five-signal communication interface used to
control the operation of the device in a system environment. The buffers for this interface are PCI compliant. To ensure the effective delivery of security and manageability
features, the FWH interface is the only way to get access to the full feature set of the
device. The FWH interface is equipped to operate at 33 MHz, synchronous with the PCI
bus.
Address/Address
Multiplexed Interface
The A/A Mux interface is designed as a programming interface for OEMs to use during
motherboard manufacturing or component pre-programming.
The A/A Mux refers to the multiplexed row and column addresses in this interface. This
approach is required so that the device can be tested and programmed quickly with
automated test equipment (ATE) and PROM programmers in the OEM’s manufacturing
flow. This interface also allows the device to have an efficient programming interface
with potentially large future densities, while still fitting into a 32-pin package. Only basic
reads, programming, and erase of the nonvolatile memory sectors can be performed
through the A/A Mux interface. In this mode FWH features, security features and registers are unavailable. A row/column (R/C) pin determines which set of addresses “rows
or columns” are latched.
2
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
Block Diagram
WP
TBL
FGPI (4:0)
ID (3:0)
FWH (4:0)
CLK
INIT
OE
R/C
WE
RY/BY
FWH
INTERFACE
A/A MUX
INTERFACE
FLASH
ARRAY
CONTROL
LOGIC
A10 - A0
I/O7 - I/O0
RST
Pin Description
IC
Table 1 details the usage of each of the device pins. Most of the pins have dual functionality, with functions in both the Firmware Hub and A/A Mux interfaces. A/A Mux
functionality for pins is shown in bold in the description box for that pin. All pins are
designed to be compliant with voltage of VCC + 0.3V max, unless otherwise noted.
Table 1. Pin Description
Interface
Symbol
Type
FWH
A/A Mux
IC
Name and Function
INPUT
X
X
INTERFACE CONFIGURATION PIN: This pin determines which interface
is operational. This pin is held high to enable the A/A Mux interface. This
pin is held low to enable the FWH interface. This pin must be set at
power-up or before return from reset and not changed during device
operation. This pin is pulled down with an internal resistor, with value
between 20 and 100 kΩ. With IC high (A/A Mux mode), this pin will exhibit
a leakage current of approximately 200 µA. This pin may be floated,
which will select FWH mode.
RST
INPUT
X
X
INTERFACE RESET: Valid for both A/A Mux and FWH interface
operations. When driven low, RST inhibits write operations to provide
data protection during power transitions, resets internal automation, and
tri-states pins FWH [3:0] (in FWH interface mode). RST high enables
normal operation. When exiting from reset, the device defaults to read
array mode.
INIT
INPUT
X
PROCESSOR RESET: This is a second reset pin for in-system use. This
pin is internally combined with the RST pin. If this pin or RST is driven
low, identical operation is exhibited. This signal is designed to be
connected to the chipset INIT signal (Max voltage depends on the
processor. Do not use 3.3V.)
A/A Mux = OE
3
1966C–FLASH–03/02
Table 1. Pin Description (Continued)
Interface
Symbol
Type
CLK
INPUT
X
33 MHz CLOCK for FWH INTERFACE: This input is the same as the PCI
clock and adheres to the PCI specification.
A/A Mux = R/C
I/O
X
FWH I/Os: I/O Communication.
A/A Mux = I/O[3:0]
FWH4
INPUT
X
FWH INPUT: Input Communication.
A/A Mux = WE
ID[3:0]
INPUT
X
IDENTIFICATION INPUTS: These four pins are part of the mechanism
that allows multiple parts to be attached to the same bus. The strapping
of these pins is used to identify the component. The boot device must
have ID[3:0] = 0000 and it is recommended that all subsequent devices
should use a sequential up-count strapping (i.e., 0001, 0010, 0011, etc.).
These pins are pulled down with internal resistors, with values between
20 and 100 kΩ when in FWH mode. Any ID pins that are pulled high will
exhibit a leakage current of approximately 200 µA. Any pins intended to
be low may be left to float. In a single FWH system, all may be left
floating.
A/A Mux = A[3:0]
FGPI[4:0]
INPUT
X
FWH GENERAL PURPOSE INPUTS: These individual inputs can be
used for additional board flexibility. The state of these pins can be read
through FWH registers. These inputs should be at their desired state
before the start of the PCI clock cycle during which the read is attempted,
and should remain at the same level until the end of the read cycle. They
may only be used for 3.3V signals. Unused FGPI pins must not be
floated.
A/A Mux = A[10:6]
TBL
INPUT
X
TOP SECTOR LOCK: When low, prevents programming or sector erase
to the highest addressable sector (7 in a 4-Mbit, 15 in an 8-Mbit
component) regardless of the state of the lock registers TBL high disables
hardware write protection for the top sector, though register-based
protection still applies. The status of TBL does not affect the status of
sector-locking registers.
A/A Mux = A4
WP
INPUT
X
WRITE-PROTECT: When low, prevents programming or sector erase to
all but the highest addressable sectors (0 - 6 in a 4-Mbit, 0 - 14 in an
8-Mbit component), regardless of the state of the corresponding lock
registers. WP-high disables hardware write protection for these sectors,
though register-based protection still applies. The status of TBL does not
affect the status of sector-locking registers.
A/A Mux = A5
A0 - A10
INPUT
FWH[3:0]
4
FWH
A/A Mux
X
Name and Function
LOW-ORDER ADDRESS INPUTS: Inputs for low-order addresses during
read and write operations. Addresses are internally latched during a write
cycle. For the A/A Mux interface these addresses are latched by R/C and
share the same pins as the high-order address inputs.
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
Table 1. Pin Description (Continued)
Interface
Symbol
Type
FWH
I/O0 - I/O7
I/O
X
DATA INPUT/OUTPUTS: These pins receive data and commands during
write cycles and transmit data during memory array and identifier code
read cycles. Data pins float to high-impedance when the chip is
deselected or outputs are disabled. Data is internally latched during a
write cycle.
OE
INPUT
X
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
R/C
INPUT
X
ROW-COLUMN ADDRESS SELECT: For the A/A Mux interface, this pin
determines whether the address pins are pointing to the row addresses,
A0 - A10, or to the column addresses, A11 - A18 (AT49LW040) or
A11 - A19 (AT49LW080).
WE
INPUT
X
WRITE ENABLE: Controls writes to the array sectors. Addresses and
data are latched on the rising edge of the WE pulse.
VPP
SUPPLY
X
X
SECTOR ERASE/PROGRAM POWER SUPPLY: For erasing array
sectors or programming data. V PP = 3.3V or 12V. With VPP ≤ VPPLK,
memory contents cannot be altered. Sector erase or program with an
invalid V PP (see DC Characteristics) produces spurious results and
should not be attempted. VPP may only be held at 12V for 80 hours over
the lifetime of the device.
VCC
SUPPLY
X
X
DEVICE POWER SUPPLY: Internal detection automatically configures
the device for optimized read performance. Do no float any power pins.
With VCC ≤ VLKO, all write attempts to the flash memory are inhibited.
Device operations at invalid VCC voltages (see DC Characteristics)
produce spurious results and should not be attempted.
GND
SUPPLY
X
X
GROUND: Do not float any ground pins.
VCCa
SUPPLY
X
X
ANALOG POWER SUPPLY: This supply should share the same system
supply as VCC.
GNDa
SUPPLY
X
X
ANALOG GROUND: Should be tied to same plane as GND.
RFU
X
NC
X
RY/BY
OUTPUT
A/A Mux
Name and Function
RESERVED FOR FUTURE USE: These pins are reserved for future
generations of this product and should be connected accordingly. These
pins may be left disconnected or driven. If they are driven, the voltage
levels should meet VIH and VIL requirements.
A/A Mux = I/O[7:4]
X
NO CONNECT: Pin may be driven or floated. If it is driven, the voltage
levels should meet VIH and VIL. No connects appear only on the 40-lead
TSOP package.
X
READY/BUSY: Valid only in A/A Mux Mode. This output pin is a reflection
of bit 7 in the status register. This pin is used to determine sector erase or
program completion.
5
1966C–FLASH–03/02
Firmware Hub
Interface (FWH)
Table 2 lists the seven required signals used for the FWH interface.
Table 2. FWH Required Signal List
Direction
Signal
Peripheral
Master
I/O
I/O
Multiplexed command, address and data
FWH4
I
O
Indicates start of a new cycle, termination of broken
cycle.
RST
I
I
Reset: Same as PCI Reset on the master. The master
does not need this signal if it already has PCIRST on
its interface.
CLK
I
I
Clock: Same 33 MHz clock as PCI clock on the
master. Same clock phase with typical PCI skew. The
master does not need this signal if it already has
PCICLK on its interface.
FWH[3:0]
Description
FWH[3:0]: The FWH[3:0] signal lines communicate address, control, and data information o ver th e LPC bu s betw een a mas te r an d a p eriph era l. The info rmatio n
communicated are: start, stop (abort a cycle), transfer type (memory, I/O, DMA), transfer direction (read/write), address, data, wait states, DMA channel, and bus master
grant.
FWH4: FWH4 is used by the master to indicate the start of cycles and the termination of
cycles due to an abort or time-out condition. This signal is to be used be by peripherals
to know when to monitor the bus for a cycle.
The FWH4 signal is used as a general notification that the FWH[3:0] lines contain information relative to the start or stop of a cycle, and that peripherals must monitor the bus
to determine whether the cycle is intended for them. The benefit to peripherals of FWH4
is, it allows them to enter lower power states internally.
When peripherals sample FWH4 active, they are to immediately stop driving the
FWH[3:0] signal lines on the next clock and monitor the bus for new cycle information.
RESET: RST or INIT at VIL initiates a device reset. In read mode, RST or INIT low
deselects the memory, places output drivers in a high-impedance state, and turns off all
internal circuits. RST or INIT must be held low for time tPLPH (A/A Mux and FWH operation). The FWH resets to read array mode upon return from reset, and all sectors are set
to default (locked) status regardless of their locked state prior to reset.
Driving RST or INIT low resets the device, which resets the sector lock registers to their
default (write-locked) condition. A reset time (tPHQV A/A Mux) is required from RST or
INIT switching high until outputs are valid. Likewise, the device has a wake time (tPHRH
A/A Mux) from RST or INIT high until writes to the CUI are recognized. A reset latency
will occur if a reset procedure is performed during a programming or erase operation.
During sector erase or program, driving RST or INIT low will abort the operation underway, in addition to causing a reset latency. Memory contents being altered are no longer
valid, since the data may be partially erased or programmed.
It is important to assert RST or INIT during system reset. When the system comes out of
reset, it will expect to read from the memory array of the device. If a system reset occurs
with no FWH reset (this will be hardware dependent), it is possible that proper CPU initialization will not occur (the FWH memory may be providing status information instead
of memory array data).
6
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
C Y C L E T YP E S : T h e r e a r e tw o t y p e s o f c y cl e s t h a t a r e s u p p o r te d b y t h e
AT49LW080/040: FWH Memory Read and FWH Memory Write. FWH Memory Read or
Write cycles start with a preamble.
PREAMBLE: The preamble consists of a START, IDSEL, 28-bit Address and MSIZE
fields. The preamble is shown in Figure 1. The preamble begins with FWH4 going low
and a START field driven on FWH[3:0]. For FWH Memory Read cycles, the START field
must be 1101b; for FWH Memory Write cycles, the START field must be 1110b. Following the START field is the IDSEL field. This field acts like a chip select in that it indicates
which device should respond to the current transaction. The next seven clocks are the
28-bit address, which tell from where to begin reading or writing in the selected device.
Next, an MSIZE value of 0 indicates the master is requesting a single byte.
Figure 1. FWH Memory Cycle Preamble
CLK
FWH4
FWH3 - FWH0
START
IDSEL
28-BIT ADDRESS
MSIZE
START: This one-clock field indicates the start of a cycle. It is valid on the last clock that
FWH4 is sampled low. The two start fields that are used for the cycle are shown in Table
3. If the start field that is sampled is not one of these values, then the cycle attempted is
not an FWH memory cycle. It may be a valid memory cycle that the FWH component
may wish to decode, i.e., it may be of the LPC memory cycle variety.
Table 3. Start Fields
FWH[3:0]
Indication
1101b
FWH Memory Read
1110b
FWH Memory Write
IDSEL (DEVICE SELECT): This one-clock field is used to indicate which FWH component is being selected. The four bits transmitted over FWH[3:0] during this clock are
compared with values strapped onto pins [ID3:ID0] on the FWH component. If there is a
match, the FWH component will continue to decode the cycle to determine which bytes
are requested on a read or which bytes to update on a write. If there isn’t a match, the
FWH component may discard the rest of the cycle and go into a standby power state.
MADDR (MEMORY ADDRESS): This is a seven-clock field, which gives a 28-bit memory address. This allows for up to 256 MB per memory device, for a total of a 4 GB
addressable space. The address is transferred with the most significant nibble first.
MSIZE (MEMORY SIZE): “0000b” will be sent in this field. A value of “0000b” corresponds to a single byte transfer.
7
1966C–FLASH–03/02
Device Operation
READ: Read operations consist of preamble, TAR, SYNC and data fields as shown in
Figure 2 and described in Table 5. TAR and SYNC fields are described below. Commands using the read mode include the following functions: reading memory from the
array, reading the identifier codes, reading the lock bit registers and reading the GPI
registers. Memory information, identifier codes, or the GPI registers can be read independent of the VPP voltage. Upon initial device power-up or after exit from reset mode,
the device automatically resets to read array mode.
READ CYCLE, SINGLE BYTE: For read cycles, after the preamble, the master drives a
TAR field to give ownership of the bus to the FWH. After the second clock of the TAR
phase the FWH assumes the bus and begins driving SYNC values. When it is ready, it
drives the low nibble, then the high nibble of data, followed by a TAR field to give control
back to the master.
Figure 2 shows a device that requires three SYNC clocks to access data. Since the
access time can begin once the address phase has been completed, the two clocks of
the TAR phase can be considered as part of the access time of the part. For example, a
device with a 120 ns access time could assert “0101b” for clocks 1 and 2 of the SYNC
phase and “0000b” for the last clock of the SYNC phase. This would be equivalent to
five clocks worth of access time if the device started that access at the conclusion of the
preamble phase. Once SYNC is achieved, the device then returns the data in two clocks
and gives ownership of the bus back to the master with a TAR phase.
TURN-AROUND (TAR): This field is two clocks wide, and is driven by the master when
it is turning control over to the FWH, (for example, to read data), and is driven by the
FWH when it is turning control back over to the master. On the first clock of this
two-clock-wide field, the master or FWH drives the FWH[3:0] lines to “1111b”. On the
second clock of this field, the master or peripheral tri-states the FWH[3:0] lines.
SYNC: This field is used to add wait states. It can be several clocks in length. On target
or DMA cycles, this field is driven by the FWH. If the FWH needs to assert wait states, it
does so by driving “0101b” (short SYNC) on FWH[3:0] until it is ready. When ready, it
will drive “0000b”. Valid values for this field are shown in Table 4.
Table 4. Valid SYNC Values
Bits[3:0]
Indication
0000
Ready: SYNC achieved with no error.
0101
Short Wait: Part indicating wait states.
Figure 2. FWH Single-byte Read Waveforms
CLK
FWH4
FWH[3:0]
START IDSEL
MADDR
MSIZE
TAR
SYNC(3)
DATA
TAR
PREAMBLE
8
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
Table 5. FWH Read Cycle
Clock Cycle
Field Name
Field Contents(1)
FWH[3:0]
FWH[3:0]
Direction
1
START
1101b
IN
FWH4 must be active (low) for the part to respond.
Only the last start field (before FWH4 transitioning
high) should be recognized. The START field contents
indicate an FWH memory read cycle.
2
IDSEL
0000b
to
1111b
IN
Indicates which FWH device should respond. If the
IDSEL (ID select) field matches the value ID[3:0],
then that particular device will respond to subsequent
commands.
3-9
MADDR
YYYY
IN
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most significant nibble first.
10
MSIZE
0000b (1 byte)
IN
The FWH will only support single-byte transfers.
11
TAR0
1111b
IN
then float
12
TAR1
1111b (float)
Float then OUT
The FWH takes control of the bus during this cycle.
During the next clock cycle, it will be driving “sync
data”.
13 - 14
WSYNC
0101b (WAIT)
OUT
The FWH outputs the value 0101, a wait-sync
(WSYNC, a.k.a. “short-sync”), for two clock cycles.
This value indicates to the master (ICH) that data is
not yet available from the part. This number of waitsyncs is a function of the device’s access time.
15
RSYNC
0000b (READY)
OUT
During this clock cycle, the FWH will generate a
“ready-sync” (RSYNC) indicating that the least
significant nibble of the least significant byte will be
available during the next clock cycle.
16
DATA
YYYY
OUT
YYYY is the least significant nibble of the least
significant data byte.
17
DATA
YYYY
OUT
YYYY is the most significant nibble of the least
significant data byte.
18
TAR0
1111b
OUT
then float
The FWH Flash memory drives FWH0 - FWH3 to
1111b to indicate a turnaround cycle.
19
TAR1
1111b (float)
Float then
IN
The FWH Flash memory floats its outputs, the master
(ICH) takes control of FWH3 - FWH0.
Note:
Comments
In this clock cycle, the master (ICH) has driven the
bus to all 1s and then floats the bus, prior to the next
clock cycle. This is the first part of the bus “turnaround
cycle”.
1. Field contents are valid on the rising edge of the present clock cycle.
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1966C–FLASH–03/02
WRITE: Write operations consist of preamble, data, TAR and SYNC fields as shown in
Figure 3 and described in Table 6.
WRITE CYCLES, SINGLE BYTE: All devices that support FWH Memory Write cycles
must support single-byte writes. FWH Memory Write cycles use the same preamble as
FWH Memory Read cycles.
For write cycles, after the preamble, the master writes the low nibble, then the high nibble of data. After that the master drives a TAR field to give ownership of the bus to the
FWH. After the second clock of the TAR phase, the target device assumes the bus and
begins driving SYNC values. A TAR field to give control back to the master follows this.
Figure 3. FWH Single-byte Write Waveforms
CLK
FWH4
FWH[3:0]
START IDSEL
MADDR
MSIZE
DATA
TAR
SYNC
TAR
PREAMBLE
Table 6. FWH Write Cycle
Clock Cycle
Field Name
Field
Contents(1)
FWH[3:0]
1
START
1110b
IN
FWH4 must be active (low) for the part to respond. Only the last
start field (before FWH4 transitioning high) should be recognized.
The START field contents indicate an FWH memory write cycle.
2
IDSEL
0000b
to
1111b
IN
Indicates which FWH device should respond. If the IDSEL (ID
select) field matches the value ID[3:0], then that particular device
will respond to subsequent commands.
3-9
MADDR
YYYY
IN
These seven clock cycles make up the 28-bit memory address.
YYYY is one nibble of the entire address. Addresses are
transferred most significant nibble first.
10
MSIZE
0000b (1 byte)
IN
The FWH only supports single-byte writes.
11
DATA
YYYY
IN
This field is the least significant nibble of the data byte. This data
is either the data to be programmed into the Flash memory or
any valid Flash command.
12
DATA
YYYY
IN
This field is the most significant nibble of the data byte.
13
TAR0
1111b
IN
then float
In this clock cycle, the master (ICH) has driven the bus to all 1s
and then floats the bus prior to the next clock cycle. This is the
first part of the bus “turnaround cycle”.
14
TAR1
1111b (float)
Float then
OUT
The FWH takes control of the bus during this cycle. During the
next clock cycle it will be driving the “sync” data.
15
RSYNC
0000b
OUT
16
TAR0
1111b
OUT
then Float
The FWH Flash memory drives FWH0 - FWH 3 to 1111b to
indicate a turnaround cycle.
17
TAR1
1111b (float)
Float then
IN
The FWH Flash memory floats its outputs, the master (ICH)
takes control of FWH3 - FWH0.
Note:
10
FWH[3:0]
Direction
Comments
The FWH outputs the values 0000, indicating that it has received
data or a Flash command.
1. Field contents are valid on the rising edge of the present clock cycle.
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
OUTPUT DISABLE: When the FWH is not selected through a FWH read or write cycle,
the FWH interface outputs (FWH[3:0]) are disabled and will be placed in a high-impedance state.
Response to Invalid
Fields
During FWH operations, the FWH will not explicitly indicate that it has received invalid
field sequences. The response to specific invalid fields or sequences is as follows:
•
Address out of range: The FWH address sequences is seven fields long (28 bits),
but only the last five address fields (20 bits) will be decoded by an 8-Mbit FWH. (For
a 4-Mbit density, the most significant bit (FWH3) in the third address field also will be
ignored.) The FWH will respond to these lower addresses, regardless of the value of
the more-significant address bits. Address A22 has the special function of directing
reads and writes to the Flash core (A22 = 1) or to the register space (A22 = 0).
•
Invalid MSIZE field: If the FWH receives an invalid size field during a read or write
operation, the internal state machine will reset and no operation will be attempted.
The FWH will generate no response of any kind in this situation. Invalid-size fields
for a read cycle are anything but 0000. Invalid-size fields for a write cycle are
anything but 0000. When accessing register space, invalid field sizes are anything
but 0000.
Once valid START, IDSEL, and MSIZE fields are received, the FWH always will
respond to subsequent inputs as if they were valid. As long as the states of FWH
[3:0] and FWH4 are known, the response of the FWH to signals received during the
FWH cycle should be predictable. The FWH will make no attempt to check the validity of incoming Flash operation commands.
Bus Abort
The Bus Abort operation can be used to immediately abort the current bus operation. A
Bus Abort occurs when FWH4 is driven Low, VIL, during the bus operation; the memory
will tri-state the Input/Output Communication pins, FWH3 - FWH0 and the FWH state
machine will reset. During a write cycle, there is the possibility that an internal Flash
write or erase operation is in progress (or has just been initiated). If the FWH4 is
asserted during this time frame, the internal operation will not abort. The software must
send an explicit Flash command to terminate or suspend the operation. The internal
FWH state machine will not initiate a Flash write or erase operation until it has received
the last nibble from the chipset. This means that FWH4 can be asserted as late as cycle
12 (Table 6) and no internal Flash operation will be attempted.
HARDWARE WRITE-PROTECT PINS TBL AND WP: Two pins are available with the
FWH to provide hardware write-protect capabilities.
The Top Sector Lock (TBL) pin is a signal, when held low (active), prevents program or
sector erase operations in the top sector of the device (sector 7 – AT49LW040 and sector 15 – AT49LW080) where critical code can be stored. When TBL is high, hardware
write protection of the top sector is disabled. The write-protect (WP) pin serves the same
function for all the remaining sectors except the top sector. WP operates independently
from TBL and does not affect the lock status of the top sector.
The TBL and WP pins must be set to the desired protection state prior to starting a program or erase operation since they are sampled at the beginning of the operation.
Changing the state of TBL or WP during a program or erase operation may cause
unpredictable results.
11
1966C–FLASH–03/02
If the state of TBL or WP changes during a program suspend or erase suspend state,
the changes to the device’s locking status do not take place immediately. The suspended operation may be resumed to successfully complete the program or erase
operation. The new lock status will take place after the program or erase operation
completes.
These pins function in combination with the register-based sector locking (to be
explained later). These pins, when active, will write-protect the appropriate sector(s),
regardless of the associated sector locking registers. (For example, when TBL is active,
writing to the top sector is prevented, regardless of the state of the Write Lock bit for the
top sector’s locking register. In such a case, clearing the write-protect bit in the register
will have no functional effect, even though the register may indicate that the sector is no
longer locked. The register may still be set to read-lock the sector, if desired.)
12
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
Device Memory Map with FWH Hardware Lock Architecture
AT49LW040
Sector
Size (Bytes)
Address Range
Hardware Write-protect Pin
SA0
64K
00000 - 0FFFF
WP
SA1
64K
10000 - 1FFFF
WP
SA2
64K
20000 - 2FFFF
WP
SA3
64K
30000 - 3FFFF
WP
SA4
64K
40000 - 4FFFF
WP
SA5
64K
50000 - 5FFFF
WP
SA6
64K
60000 - 6FFFF
WP
SA7
64K
70000 - 7FFFF
TBL
Sector
Size (Bytes)
Address Range
Hardware Write-protect Pin
SA0
64K
00000 - 0FFFF
WP
SA1
64K
10000 - 1FFFF
WP
SA2
64K
20000 - 2FFFF
WP
SA3
64K
30000 - 3FFFF
WP
SA4
64K
40000 - 4FFFF
WP
SA5
64K
50000 - 5FFFF
WP
SA6
64K
60000 - 6FFFF
WP
SA7
64K
70000 - 7FFFF
WP
SA8
64K
80000 - 8FFFF
WP
SA9
64K
90000 - 9FFFF
WP
SA10
64K
A0000 - AFFFF
WP
SA11
64K
B0000 - BFFFF
WP
SA12
64K
C0000 - CFFFF
WP
SA13
64K
D0000 - DFFFF
WP
SA14
64K
E0000 - EFFFF
WP
SA15
64K
F0000 - FFFFF
TBL
AT49LW080
13
1966C–FLASH–03/02
Register-based
Locking and Generalpurpose Input
Registers
A series of registers are available in the FWH to provide software read and write locking
and GPI feedback. These registers are accessible through standard addressable memory space.
REGISTERS: The AT49LW040/080 has two types of registers: sector-locking registers
and general-purpose input registers. The two types of registers appear at their respective address locations in the 4 GB system memory map.
SECTOR-LOCKING REGISTERS: The AT49LW040 and the AT49LW080 have 8 (LR0
- LR7) and 16 (LR0 - LR15) sector-locking registers, respectively. Each sector-locking
register controls the lock protection for 64K bytes of memory as shown in Table 7
(AT49LW040) and Table 8 (AT49LW080). The sector-locking registers are accessible
through the register memory address shown in the third column of Table 7 and Table 8.
The sector-locking registers are read/write as shown in the last column of Table 7 and
Table 8. Each sector has three dedicated locking bits as shown in Table 9 and Table 10.
Table 7. Sector-locking Registers for AT49LW040
Register Name
Sector Size
Register Memory Address
Default Value
Type
LR0
64K
FFB80002H
01H
R/W
LR1
64K
FFB90002H
01H
R/W
LR2
64K
FFBA0002H
01H
R/W
LR3
64K
FFBB0002H
01H
R/W
LR4
64K
FFBC0002H
01H
R/W
LR5
64K
FFBD0002H
01H
R/W
LR6
64K
FFBE0002H
01H
R/W
LR7
64K
FFBF0002H
01H
R/W
FFBC0100H
N/A
RO
FGPI-REG
14
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
Table 8. Sector-locking Registers for AT49LW080
Register Name
Sector Size
Register Memory Address
Default Value
Type
LR0
64K
FFB00002H
01H
R/W
LR1
64K
FFB10002H
01H
R/W
LR2
64K
FFB20002H
01H
R/W
LR3
64K
FFB30002H
01H
R/W
LR4
64K
FFB40002H
01H
R/W
LR5
64K
FFB50002H
01H
R/W
LR6
64K
FFB60002H
01H
R/W
LR7
64K
FFB70002H
01H
R/W
LR8
64K
FFB80002H
01H
R/W
LR9
64K
FFB90002H
01H
R/W
LR10
64K
FFBA0002H
01H
R/W
LR11
64K
FFBB0002H
01H
R/W
LR12
64K
FFBC0002H
01H
R/W
LR13
64K
FFBD0002H
01H
R/W
LR14
64K
FFBE0002H
01H
R/W
LR15
64K
FFBF0002H
01H
R/W
FFBC0100H
N/A
RO
FGPI-REG
Table 9. Function of Sector-locking Bits
Bit
Function
7:3
Reserved
2
Read Lock
1 = Prevents read operations in the sector where set.
0 = Normal operation for reads in the sector where clear. This is the default state.
1
Lock-down
1 = Prevents further set or clear operations to the Write Lock and Read Lock bits. Lock-down can only be set, but
not cleared. The sector will remain locked-down until reset (with RST or INIT), or until the device is power-cycled.
0 = Normal operation for Write Lock and Read Lock bits altering in the sector where clear. This is the default state.
0
Write Lock
1 = Prevents program or erase operations in the sector where set. This is the default state.
0 = Normal operation for programming and erase in the sector where clear.
15
1966C–FLASH–03/02
Table 10. Register-based Locking Value Definitions
Reserved
Data 7 - 3
Read Lock,
Data 2
Lock-down,
Data 1
Write Lock,
Data 0
00
00000
0
0
0
Full access
01
00000
0
0
1
Write locked. Default state at power-up
02
00000
0
1
0
Locked open (full access locked down)
03
00000
0
1
1
Write locked down
04
00000
1
0
0
Read locked
05
00000
1
0
1
Read and write locked
06
00000
1
1
0
Read locked down
07
00000
1
1
1
Read and write locked down
Data
Note:
Resulting Sector State(1)
1. The Write Lock bit must be set to the desired protection state prior to starting a program or erase operation since it is sampled at the beginning of the operation. Changing the state of the Write Lock bit during a program or erase operation may
cause unpredictable results. If the state of the Write Lock bit changes during a program suspend or erase suspend state, the
changes to the sector’s locking status do not take place immediately. The suspended operation may be resumed successfully. The new lock status will take place after the program or erase operation completes. The individual bit functions are
described in the following sections.
READ LOCK: The default read status of all sectors upon power-up is read-unlocked.
When a sector’s read-lock bit is set (1 state), data cannot be read from that sector. An
attempted read from a read-locked sector will result in data 00H being read. (Note that
failure is not reflected in the status register). The read-lock status can be unlocked by
clearing (0 state) the read-lock bit, provided the lock-down bit has not been set. The current read-lock status of a particular sector can be determined by reading the
corresponding read-lock bit.
WRITE LOCK: The default write status of all sectors upon power-up is write-locked (1
state). Any program or erase operations attempted on a locked sector will return an
error in the status register (indicating sector lock). The status of the locked sector can be
changed to unlocked (0 state) by clearing the write-lock bit, provided the lock-down bit is
not also set. The current write-lock status of a particular sector can be determined by
reading the corresponding write-lock bit. Any program or erase operations attempted on
a locked sector will return an error in the status register (indicating sector lock). The
write-lock functions in conjunction with the hardware write-lock pins, TBL and WP.
When active, these pins take precedence over the register-locking function and writelock the top sector or remaining sectors, respectively. Reading this register will not read
the state of the TBL or WP pins.
LOCK-DOWN: When in the FWH interface mode, the default lock-down status of all
sectors upon power-up is not-locked-down (0 state). The lock-down bit for any sector
may be set (1 state), but only once, as future attempted changes to that sector locking
register will be ignored. The lock-down bit is only cleared upon a device reset with RST
or INIT. The current lock-down status of a particular sector can be determined by reading the corresponding lock-down bit. Once a sector’s lock-down bit is set, the read- and
write-lock bits for that sector can no longer be modified and the sector is locked down in
its current state of read and write accessibility.
GENERAL-PURPOSE INPUTS REGISTER: This register reads the status of the
FGPI[4:0] pins on the FWH at power-up. Since this is a pass-through register, there is
no default value as shown in Table 7 and Table 8. It is recommended that the GPI pins
be in the desired state before FWH4 is brought low for the beginning of the next bus
cycle, and remain in that state until the end of the cycle.
16
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
Table 11. General-purpose Input Registers
Bit
Function
7:5
Reserved
4
FGPI[4]
Reads status of general-purpose input pin (PLCC-30/TSOP-7)
3
FGPI[3]
Reads status of general-purpose input pin (PLCC-3/TSOP-15)
2
FGPI[2]
Reads status of general-purpose input pin (PLCC-4/TSOP-16)
1
FGPI[1]
Reads status of general-purpose input pin (PLCC-5/TSOP-17)
0
FGPI[0]
Reads status of general-purpose input pin (PLCC-6/TSOP-18)
Command Definitions in (Hex)
1st Bus Cycle
Command Sequence
Read Array/Reset
Sector Erase
(2)(3)
Byte Program(2)(4)
Bus Cycles
Operation
Addr
Data
1
Write
XXXX
FF
2
Write
SA
2
Write
Sector Erase Suspend(2)
Program Suspend
(2)
Operation
Addr
Data
20
Write
SA
D0
Addr
40 or 10
Write
Addr
DIN
XXXX
B0
XXXX
D0
Write
1
Write
Sector Erase Resume(2)
Program Resume(2)
2nd Bus Cycle
Write
1
Write
Product ID Entry(5)
2
Write
XXXX
90
Read
AID(6)
DOUT
Read Status Register
2
Write
XXXX
70
Read
XXXX
SRD(7)
Clear Status Register
1
Write
XXXX
50
Notes:
1. X = Any valid address within the device
2. The sector must be not be write locked when attempting sector erase or program operations. Attempts to issue a sector
erase or byte program to a write locked sector will fail.
3. SA = Sector address. Any byte address within a sector can be used to designate the sector address (see page 13).
4. Either 40H or 10H is recognized as the program setup.
5. Following the Product ID Entry command, read operations access manufacture and device ID. See Table 12.
6. AID = Address used to read data for manufacture or device ID
7. SRD = Data Read from status register
17
1966C–FLASH–03/02
READ ARRAY: Upon initial device power-up and after exit from reset, the device
defaults to read array mode. This operation is also initiated by writing the Read Array
command. The device remains enabled for reads until another command is written.
Once the internal state machine (WSM) has started a block erase or program operation,
the device will not recognize the Read Array Command until the operation is completed,
unless the operation is suspended via an Erase Suspend or Program Suspend Command. The Read Array command functions independently of the VPP voltage.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel.
Following the Product ID Entry command, read cycles from the addresses shown in
Table 12 retrieve the manufacturer and device code. To exit the product identification
mode, any valid command can be written to the device. The Product ID Entry command
functions independently of the VPP voltage.
Table 12. Identifier Codes
Code
Address (AID)
Data
Manufacturer Code
000000
1F
AT49LW040
000001
E0
AT49LW080
000001
E1
Device Code
SECTOR ERASE: Before a byte can be programmed, it must be erased. The erased
state of the memory bits is a logical “1”. Since the AT49LW080/040 does not offer a
complete chip erase, the device is organized into multiple sectors that can be individually erased. The Sector Erase command is a two-bus cycle operation. The sector whose
address is valid at the second falling edge of the WE will be erased, provided the given
sector is not protected.
Successful sector erase requires that the corresponding sector’s Write Lock bit be
cleared and the corresponding write-protect pin (TBL or WP) be inactive. If sector erase
is attempted when the sector is locked, the sector erase will fail, with the reason for failure in the status register.
Successful sector erase only occurs when VPP = VPPH1 or VPPH2. If the erase operation is
attempted at VPP ≠ VPPH1 or VPPH2 erratic results may occur.
BYTE PROGRAMMING: The device is programmed on a byte-by-byte basis. Programming is accomplished via the internal device command register and is a two-bus cycle
operation. The programming address and data are latched in the second bus cycle. The
device will automatically generate the required internal programming pulses. Please
note that a “0” cannot be programmed back to a “1”; only an erase operation can convert
“0”s to “1”s.
After the program command is written, the device automatically outputs the status register data when read. When programming is complete, the status register may be
checked. If a program error is detected, the status register should be cleared before corrective action is taken by the software. The internal WSM verification Error Checking
only detects “1”s that do not successfully program to “0”s.
Reliable programming only occurs when VPP = VPPH1 or VPPH2. If the program operation
is attempted at VPP ≠ VPPH1 or VPPH2 erratic results may occur.
A successful program operation also requires that the corresponding sector’s Write Lock
bit be cleared, and the corresponding write-protect pin (TBL or WP) be inactive. If a program operation is attempted when the sector is locked, the operation will fail.
18
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
ERASE SUSPEND: The Erase Suspend command allows sector-erase interruption to
read or program data in another sector of memory. Once the sector erase process
starts, writing the sector erase suspend command requests that the WSM suspend the
sector erase sequence at a predetermined point in the algorithm. The device outputs
status register data when read after the sector erase suspend command is written. Polling the status register can help determine when the sector erase operation was
suspended. After a successful suspend, a Read Array command can be written to read
data from a sector other than the suspended sector. A program command sequence
may also be issued during erase suspend to program data in sectors other than the sector currently in the erase suspend mode.
The other valid commands while sector erase is suspended include Read Status Register and Sector Erase Resume. After a Sector Erase Resume command is written, the
WSM will continue the sector erase process. VPP must remain at VPPH1/2 (the same VPP
level initially used for sector erase) while sector erase is suspended. RST or INIT must
also remain at VIH. Sector erase cannot resume until program operations initiated during
sector erase suspend have completed.
PROGRAM SUSPEND: The Program Suspend command allows program interruption
to read data in other memory locations. Once the program process starts, writing the
Program Suspend Command requests that the WSM suspend the program sequence at
a predetermined point in the algorithm. The device continues to output status register
data when read after the program suspend command is written. Polling the status register can help determine when the program operation was suspended. After a successful
suspend, a Read Array command can be written to read data from locations other than
that which is suspended. The only other valid commands while program is suspended
are Read Status Register and Program Resume. VPP must remain at VPPH1/2 (the same
VPP level used for program) while in program suspend mode. RST or INIT must also
remain at VIH.
READ STATUS REGISTER: The status register may be read to determine when a sector erase or program completes and whether the operation completed successfully. The
status register may be read at any time by writing the Read Status Register command.
After writing this command, all subsequent read operations will return data from the status register until another valid command is written. The Read Status Register command
functions independently of the VPP voltage.
CLEAR STATUS REGISTER: Error flags in the status register can only be set to “1”s by
the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions. The Clear Status Register command functions
independently of the applied VPP voltage.
19
1966C–FLASH–03/02
Status Register Definition
B7
B6
B5
B4
B3
B2
B1
B0
Notes:
20
Write State Machine Status(1)
1
Ready
0
Busy
1
Sector Erase Suspended
0
Sector Erase in Progress/Completed
1
Error in Sector Erasure
0
Successful Sector Erase
1
Error in Program
0
Successful Program
1
VPP Low Detect, Operation Abort
0
VPP OK
1
Program Suspended
0
Program in Progress/Completed
1
Write Lock Bit, TBL Pin or WP Pin Detected, Operation Abort
0
Unlock
Erase Suspend Status
Erase Status(2)
Program Status
VPP Status(3)
Program Suspend Status
Device Protect Status(4)
Reserved for Future Enhancements(5)
1. Check B7 to determine sector erase or program completion. B6 - B0 are invalid while B7 = “0”.
2. If both B5 and B4 are “1”s after a sector erase attempt, an improper command sequence was entered.
3. B3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the VPP level only after a sector erase or program operation. B3 is not guaranteed to report accurate feedback only when VPP ≠ VPPH1/2.
4. B1 does not provide a continuous indication of Write Lock bit, TBL pin or WP pin values. The WSM interrogates the Write
Lock bit, TBL pin or WP pin only after a sector erase or program operation. Depending on the attempted operation, it informs
the system whether or not the selected sector is locked.
5. B0 is reserved for future use and should be masked out when polling the status register.
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
A/A Mux Interface
The following information applies only to the AT49LW040/080 when in A/A Mux Mode.
Information on FWH Mode (the standard operating mode) is detailed earlier in this document. Electrical characteristics in A/A Mux Mode are provided on pages starting from
page 27.
The AT49LW040/080 is designed to offer a parallel programming mode for faster factory
programming. This mode, called A/A Mux Mode, is selected by having this IC pin high.
The IC pin is pulled down internally in the AT49LW040/080, so a modest current should
be expected to be drawn (see Table 1 on page 3 for further information). Four control
pins dictate data flow in and out of the component: R/C, OE, WE, and RST. R/C is the
A/A Mux control pin used to latch row and column addresses. OE is the data output control pin (I/O0 - I/O7), drives the selected memory data onto the I/O bus, when active WE
and RST must be at VIH.
BUS OPERATION: All A/A Mux bus cycles can be conformed to operate on most automated test equipment and PROM programmers.
Bus Operations
Mode
Read(1)(2)(6)
Output Disable(6)
RST
OE
WE
Address
VPP
I/O0 - I/O7
VIH
VIL
VIH
X
X
DOUT
VIH
VIH
VIH
X
X
High-Z
X
Note 3
X
DIN
Product ID Entry
VIH
VIL
VIH
(3)
(4)(5)(6)
VIH
VIH
VIL
X
(6)
Write
Notes:
1. When VPP ≤ V PPLK, the memory contents can be read, but not altered.
2. X can be VIL or VIH for control and address input pins and VPPLK or V PPH1/2 for the VPP
supply pin. See the “DC Characteristics” for VPPLK and VPPH1/2 voltages.
3. See Table 12 on page 18 for Product ID Entry data and addresses.
4. Command writes involving sector erase or program are reliably executed when V PP =
VPPH1/2 and VCC = VCC ± 0.3V.
5. Refer to “A/A Mux Read-only Operations” for valid DIN during a write operation.
6. VIH and VIL refer to the DC characteristics associated with Flash memory output buffers: VIL min = 0.5V, VIL max = 0.8V, VIH min = 2.0V, VIH max = VCC + 0.5V.
OUTPUT DISABLE/ENABLE: With OE at a logic-high level (VIH), the device outputs are
disabled. Output pins I/O0 - I/O7 are placed in the high-impedance state. With OE at a
logic-low level (VIL), the device outputs are enabled. Output pins I/O0 - I/O7 are placed
in a output-drive state.
ROW/COLUMN ADDRESSES: R/C is the A/A Mux control pin used to latch row (A0 A10) and column addresses (A11 - A18) [AT49LW040], or (A11 - A19) [AT49LW080].
R/C latches row addresses on the falling edge and column addresses on the rising
edge.
RDY/BUSY: An open drain Ready/Busy output pin provides a hardware method of
detecting the end of a program or erase operation. RDY/Busy is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle.
21
1966C–FLASH–03/02
Absolute Maximum Ratings*
*NOTICE:
Voltage on Any Pin
(except VPP) .................................-0.5V to +VCC + 0.5V(1)(2)(4)
VPP Voltage ............................................ -0.5V to +13.0V(1)(2)(3)
Notes:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
1. All specified voltages are with respect to GND. Minimum DC voltage on the VPP pin is -0.5V. During transitions, this level may
undershoot to -2.0V for periods of <20 ns. During transitions, this level may overshoot to VCC + 2.0V for periods <20 ns.
2. Maximum DC voltage on VPP may overshoot to +13.0V for periods <20 ns.
3. Connection to supply of VHH is allowed for a maximum cumulative period of 80 hours.
4. Do not violate processor or chipset limitations on the INIT pin.
Operating Conditions
Temperature and VCC
Symbol
Parameter
Test Condition
(1)
TC
Operating Temperature
VCC
VCC Supply Voltage (3.3V ± 0.3V)
Note:
Case Temperature
Min
Max
Unit
0
+85
°C
3.0
3.6
V
1. This temperature requirement is different from the normal commercial operating condition of Flash memories.
FWH Interface DC Input/Output Specifications
Symbol
VIH
Parameter
(3)
Conditions
Input High Voltage
(5)
INIT Input High Voltage
(5)
INIT Input Low Voltage
VIH (INIT)
VIL (INIT)
VIL(3)
Input Low Voltage
IIL(4)
Input Leakage Current(1)
0 < VIN < VCC
VOH
Output High Voltage
IOUT = -500 µA
VOL
Output Low Voltage
IOUT = 1500 µA
CIN
Input Pin Capacitance
CCLK
CLK Pin Capacitance
L
pin(2)
Notes:
22
Recommended Pin Inductance
1.
2.
3.
4.
5.
Min
Max
Units
0.5 VCC
VCC + 0.5
V
1.35
VCC + 0.5
V
0.85
V
0.3 VCC
V
±10
µA
-0.5
0.9 VCC
3
V
0.1 VCC
V
13
pF
12
pF
20
nH
Input leakage currents include high-Z output leakage for all bi-directional buffers with tri-state outputs.
Refer to PCI spec.
Inputs are not “5-volt safe.”
IIL may be changed on IC and ID pins (up to 200 µA) if pulled against internal pull-downs. Refer to the pin descriptions
Do not violate processor or chipset specifications regarding the INIT pin voltage.
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
Power Supply Specifications – All Interfaces
Symbol
Parameter
VPPH1
Min
Max
Units
VPP Voltage
3.0
3.6
V
VPPH2
VPP Voltage
11.4
12.6
V
VPPLK
VPP Lockout Voltage
1.5
VLKO
VCC Lockout Voltage
ICCSL1
Conditions
VCC Standby Current (FWH Interface)
V
1.5
(2)
Voltage range of all inputs is
VIH to VIL, FWH4 = V IH,(3)
V
100
(4)
µA
VCC = 3.6V,
CLK f = 33 MHz
No internal operations in
progress
VCC Standby Current (FWH Interface)(2)
ICCSL2
FWH4 = VIL(3)
10(4)
mA
67(4)
mA
200
µA
40
mA
15
mA
VCC = 3.6V,
CLK f = 33 MHz
No internal operations in
progress
VCC Active Current(2)
ICCA
VCC = VCC Max,(3)
CLK f = 33 MHz
Any internal operation in
progress,
IOUT = 0 mA
VPP Read Current
IPPR
VPP Program or Erase Current
IPPWE
Notes:
(2)
1.
2.
3.
4.
VPP ≥ VCC
VPP = 3.0 - 3.6V
(2)
VPP = 11.4 - 12.6V (2)
All currents are in RMS unless otherwise noted. These currents are valid for all packages.
VPP = VCC.
VIH = 0.9 VCC, VIL = 0.1 VCC per the PCI output VOH and VOL spec.
This number is the worst case of IPP + ICC Memory Core + ICC FWH Interface.
23
1966C–FLASH–03/02
FWH Interface AC Input/Output Specifications
Symbol
Parameter
Condition
Min
Ioh(AC)
Switching Current High
0 < VOUT ≤ 0.3 V CC
0.3 VCC < VOUT <0.9 VCC
Iol(AC)
Max
-12 V CC
mA
-17.1 (VCC - VOUT)
mA
0.7 VCC < VOUT < VCC
Note 2
(Test Point)
VOUT = 0.7 VCC
-32 VCC
Switching Current Low
VCC > VOUT ≥ 0.6 VCC
0.6 VCC > VOUT > 0.1 VCC
mA
-17.1 (VCC - VOUT)
mA
Note 3
(Test Point)
VOUT = 0.18 VCC
38 VCC
Icl
Low Clamp Current
-3 < VIN ≤ -1
Ich
High Clamp Current
slewr
Output Rise Slew Rate
Notes:
Output Fall Slew Rate
mA
16 VCC
0.18 VCC > VOUT > 0
slewf
Units
mA
-25 + (VIN + 1)/0.015
mA
VCC + 4 > VIN ≥ V CC + 1
25 + (VIN - V CC - 1)/0.015
mA
0.2 VCC - 0.6 VCC load(1)
1
4
V/ns
(1)
1
4
V/ns
Min
Max
Units
30
∞
ns
0.6 VCC - 0.2 VCC load
1. PCI specification output load is used.
2. IOH = (98.0/VCC ) * (VOUT - VCC) *(VOUT + 0.4 VCC).
3. IOL = (256/VCC) * VOUT (VCC - VOUT).
FWH Interface AC Timing Specifications
Clock Specification
Symbol
Parameter
Condition
(1)
tCYC
CLK Cycle Time
tHIGH
CLK High Time
11
ns
tLOW
CLK Low Time
11
ns
-
CLK Slew Rate
Notes:
RST or INIT Slew Rate
peak-to-peak
1
(2)
4
V/ns
50
mV/ns
1. PCI components must work with any clock frequency between nominal DC and 33 MHz. Frequencies less than16 MHz may
be guaranteed by design rather than testing.
2. Applies only to rising edge of signal.
Clock Waveform
tCYC
tHIGH
0.6 VCC
tLOW
0.5 VCC
0.4 VCC
0.3 VCC
0.4 VCC, p-to-p
(minimum)
0.2 VCC
24
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
Signal Timing Parameters
Symbol
PCI Symbol
tval
tCHQX
tCHQX
Parameter
CLK to Data Out
ton
(1)
CLK to Active (Float to Active Delay)
(2)
Min
Max
Units
2
11
ns
2
ns
(2)
tCHQZ
toff
CLK to Inactive (Active to Float Delay)
tAVCH
tDVCH
tsu
Input Set-up Time(3)
7
ns
tCHAX
tCHDX
th
Input Hold Time(3)
0
ns
tVSPL
trst
Reset Active Time after Power Stable
1
ms
tCSPL
trst-clk
Reset Active Time after CLK Stable
100
µs
tPLQZ
Notes:
trst-off
Reset Active to Output Float Delay
28
(2)
48
ns
ns
1. Minimum and maximum times have different loads. See PCI spec.
2. For purposes of Active/Float timing measurements, the high-Z or “off” state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
3. This parameter applies to any input type (excluding CLK).
Output Timing Parameters
CLK
Vth
Vtl
Vtest
tval
FWH[3:0]
(Valid Output Data)
FWH[3:0]
(Float Output Data)
ton
toff
Input Timing Parameters
CLK
tsu
FWH[3:0]
(Valid Input Data)
Vth
Vtl
Vtest
Inputs Valid
th
Vmax
25
1966C–FLASH–03/02
Interface Measurement Condition Parameters
Symbol
Value
Units
(1)
0.6 V CC
V
(1)
0.2 V CC
V
Vtest
0.4 V CC
V
Vmax(1)
0.4 V CC
V
Vth
Vtl
Input Signal Edge Rate
Note:
1 V/ns
1. The input test environment is done with 0.1 VCC of overdrive over VIH and VIL. Timing parameters must be met with no more
overdrive than this. Vmax specifies the maximum peak-to-peak waveform allowed for measuring the input timing. Production
testing may use different voltage values, but must correlate results back to these parameters.
Reset Operations
Symbol
Parameter
Min
tPLPH(1)
RST or INIT Pulse Low Time (If RST or INIT is tied to VCC, this
specification is not applicable)
100
Note:
Max
Unit
ns
1. A reset latency of 20 µs will occur if a reset procedure is performed during a programming or erase operation.
AC Waveform for Reset Operation
RST
VIH
VIL
tPLPH
Sector Programming Times
3.3V VPP
Parameter
Typ(1)
Max
Typ (1)
Max
Unit
30.0
300
12.0
125
µs
2.0
20.0
0.8
8.0
sec
0.8
1.0
0.35
0.5
sec
Byte Program Time(2)
Sector Program Time
Sector Erase Time
Notes:
26
12V VPP
(2)
(2)
1. Typical values measured at TA = +25°C and nominal voltages.
2. Excludes system-level overhead.
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
ELECTRICAL CHARACTERISTICS IN A/A MUX MODE: Certain specifications differ
from the previous sections, when programming in A/A Mux Mode. The following subsections provide this data. Any information that is not shown here is not specific to A/A Mux
Mode and uses the FWH Mode specifications.
When the VPP voltage is ≤ VPPLK, read operations from memory or reading the Product
ID are enabled, but programming and erase functions are disabled. Placing VPPH1/2 on
VPP enables successful sector erase and program operations.
A/A Mux Mode Interface DC Input/Output Specifications
Symbol
Min
Max
Unit
Input High Voltage
0.5 VCC
VCC + 0.5
V
VIL(3)
Input Low Voltage
-0.5
0.8
V
IIL(4)
Input Leakage Current
+10
µA
VOH
Output High Voltage
VCC = VCC min, IOH = -2.5 mA
VCC = VCC min, IOH = -100 µA
VOL
Output Low Voltage
VCC = VCC min, IOL = 2 mA
CIN
Input Pin Capacitance
CCLK
CLK Pin Capacitance
VIH
Parameter
(3)
LPIN(2)
Notes:
Conditions
VCC = VCC max,
Vout = VCC or GND
0.85 VCC Min
VCC = 0.4
3
Recommended Pin Inductance
1.
2.
3.
4.
V
V
0.4
V
13
pF
12
pF
20
nH
Input leakage currents include high-Z output leakage for all bi-directional buffers with tri-state outputs.
Refer to PCI spec.
Inputs are not “5-volt safe.”
IIL may be changed on IC and ID pins (up to 200 µA) if pulled against internal pull-downs. Refer to the pin descriptions.
Reset Operations
Symbol
Parameter
Min
tPLPH
RST Pulse Low Time (If RST is tied to VCC, this specification is not
applicable.)
100
tPLRH
RST Low to Reset during Sector Erase or Program(1)(2)
Notes:
Max
Unit
ns
20
µs
1. If RST is asserted when the WSM is not busy (RY/BY = 1), the reset will complete within 100 ns.
2. A reset time, tPHAV, is required from the latter of RY/BY or RST going high until outputs are valid.
AC Waveforms for Reset Operations
RY/BY
VIH
VIL
tPLRH
RST
VIH
VIL
tPLPH
27
1966C–FLASH–03/02
A/A Mux Read-only Operations(1)(2)
Symbol
Parameter
Min
tAVAV
Read Cycle Time
250
ns
tAVCL
Row Address Setup to R/C Low
50
ns
tCLAX
Row Address Hold from R/C Low
50
ns
tAVCH
Column Address Setup to R/C High
50
ns
tCHAX
Column Address Hold from R/C High
50
ns
tCHQV
Max
(2)
R/C High to Output Delay
(2)
Units
150
ns
50
ns
tGLQV
OE Low to Output Delay
tPHAV
RST High to Row Address Setup
1
µs
tGLQX
OE Low to Output in Low-Z
0
ns
tGHQZ
OE High to Output in High-Z
tQXGH
Output Hold from OE High
Note:
50
0
ns
ns
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE may be delayed up to tCHQV - tGLQV after the rising edge of R/C without impact on tCHQV.
3. TC = 0°C to +85°C, 3.3V + 0.3V VCC.
A/A Mux Read Timing Diagram
tAVAV
ADDRESSES
VIH
VIL
Row Address
Stable
tAVCL
Column Address
Stable
tCLAX tAVCH
VIH
R/C
VIL
Next Address
Stable
tCHAX
tCHQV
tGLQV
tGHQZ
VIH
OE
VIL
I/O
28
VOH
VOL
WE
VIH
VIL
RST
VIH
VIL
tQXGH
tPHAV
High-Z
High-Z
Data Valid
tGLQX
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
A/A Mux Write Operations(1)(2)
Symbol
Parameter
tPHWL
RP High Recovery to WE Low
tWLWH
Write Pulse Width Low
tDVWH
Data Setup to WE High(1)
tWHDX
Data Hold from WE High
Min
(1)
(1)
tAVCL
Row Address Setup to R/C Low
tCLAX
Row Address Hold from R/C Low(1)
tAVCH
Column Address Setup to R/C High
(1)
(1)
Max
Units
1
µs
100
ns
50
ns
5
ns
50
ns
50
ns
50
ns
tCHAX
Column Address Hold from R/C High
50
ns
tWHWL
Write Pulse Width High
100
ns
tCHWH
R/C High Setup to WE High
50
ns
tVPWH
VPP1,2 Setup to WE High
100
ns
tWHGL
Write Recovery before Read
tWHRL
WE High to RY/BY Going Low
0
ns
tQVVL
VPP1,2 Hold from Valid SRD, RY/BY High
0
ns
Notes:
150
ns
1. Refer to “A/A Mux Read-only Operations” for valid AIN and DIN for sector erase or program, or other commands.
2. TC = 0°C to +85°C, 3.3V ± 0.3V VCC.
29
1966C–FLASH–03/02
A/A Mux Write Timing Diagram
R1
C1
tAVCL
R2
F









E


















D
C2
tAVCH
tCLAX
VIH
R/C
VIL
tPHWL
WE
C









B














A
VIH
ADDRESSES
VIL
tCHAX
tCHWH
tWHWL
tWLWH
VIH
VIL
tWHGL
OE
I/O
VIH
VIL
VOH
VOL
RY/BY
VIH
VIL
RST
VIH
VIL
VPP (V)
tWHDX
tDVWH
DIN
Valid
SRD
DIN
tWHRL
t
tVPWH
tQVVL
VPPH1,2
VIL
NOTES
A = VCC power-up and standby
B = Write sector erase or program setup
C = Write sector erase confirm or valid address and data
D = Automated erase or program delay
E = Read status register data
F = Ready to write another command
30
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
AT49LW040 Ordering Information
ICC (mA)
Active
Standby
Ordering Code
Package
Operation Range
67
0.10
AT49LW040-33JC
AT49LW040-33TC
32J
40T
Extended Commercial
(0° to 85°C)
AT49LW080 Ordering Information
ICC (mA)
Active
Standby
Ordering Code
Package
Operation Range
67
0.10
AT49LW080-33JC
AT49LW080-33TC
32J
40T
Extended Commercial
(0° to 85°C)
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier Package (PLCC)
40T
40-lead, Thin Small Outline Package (TSOP)
31
1966C–FLASH–03/02
Packaging Information
32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E1
E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
D2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
3.175
–
3.556
A1
1.524
–
2.413
A2
0.381
–
–
D
12.319
–
12.573
D1
11.354
–
11.506
D2
9.906
–
10.922
E
14.859
–
15.113
E1
13.894
–
14.046
E2
12.471
–
13.487
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
32
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
32J
B
AT49LW080/040
1966C–FLASH–03/02
AT49LW080/040
40T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation CD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
MIN
NOM
MAX
NOTE
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
Note 2
E
9.90
10.00
10.10
Note 2
L
0.50
0.60
0.70
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
0.50 BASIC
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
40T, 40-lead (10 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
40T
B
33
1966C–FLASH–03/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
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© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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Atmel ® is the registered trademark of Atmel. Other terms and product names may be trademarks
of others.
Printed on recycled paper.
1966C–FLASH–03/02
/xM