ATMEL U2741B

Features
• Very High Transmitting Frequency Accuracy Compared to SAW Solutions
(Enables Receivers at Lower Bandwidth than with SAW Resonators)
• Lower Cost than the Usual Discrete Solutions Using SAW and Transistors
• Supply Voltage 2.0V to 5.5V in the Temperature Range –20°C to +70°C
Supply Voltage 2.2 V to 5.5 V in the Temperature Range –40°C to +85°C
• XTO Output for Clocking the Microcontroller, Thereby Together with
•
•
•
•
•
•
the ATAR090 or ATAR890 Results in the Optimum System
Cost-effectiveness
One-chip Solution with Minimum External Circuitry
Very Small SSO16 Package, Pitch 0.635, 150 mil
“Single-ended Open-collector” Output (Same Antennas as in Discrete Solutions Can
Be Used, Simpler Adaptation of Magnetic Loop Antennas)
Very Large FSK Frequency Deviation Achievable by ±100 ppm Pulling of the Reference
Crystal
Enables Receivers at Lower Bandwidth than with SAW Resonators
ESD Protection According to MIL-STD.883 (4 KV HBM) Except Pins XTO1/ 2,
ANT and LF
UHF ASK/FSK
Transmitter
U2741B
Electrostatic sensitive device.
Observe precautions for handling.
1. Description
The U2741B is a PLL transmitter IC which has been especially developed for the
demands of RF low-cost data transmission systems at data rates up to 20 kBaud.
The transmitting frequency range is 300 MHz to 450 MHz. The device can be used in
both FSK and ASK systems.
Rev. 4733B–RKE–09/05
Figure 1-1.
System Block Diagram
UHF ASK/FSK
Remote control transmitter
UHF ASK/FSK
Remote control receiver
U3741BM
U2741B
Demod.
Keys
Encoder
ATARx9x
PLL
1...3
IF Amp
Antenna Antenna
XTO
VCO
PLL
Power
amp.
Figure 1-2.
Control
Microcontroller
1 Li cell
LNA
XTO
VCO
Block Diagram
ASK
DIVC
OR
FSK
PWRSET
Power
up
PWRVCC
VCC
VCO
PA
ANT
CLK
f
GND
PWRGND1
64
LFVCC
PWRGND2
f
XTO
n
LFGND
XTO1
LF
U2741B
2
XTO2
U2741B
4733B–RKE–09/05
U2741B
2. Pin Configuration
Figure 2-1.
Pinning SSO16
ASK
1
16
DIVIC
FSK
2
15
PWRSET
VCC
3
14
PWRVCC
CLK
4
13
ANT
U2741B
Table 2-1.
GND
5
12
PWRGND1
LFVCC
6
11
PWRGND2
LFGND
7
10
XTO1
LF
8
9
XTO2
Pin Description
Pin
Symbol
Function
1
ASK
Modulation input ASK
2
FSK
Modulation input FSK
3
VCC
Supply voltage
4
CLK
Clock output
5
GND
6
LFVCC
Supply voltage VCO
Ground
7
LFGND
VCO ground
8
LF
Circuit PLL loop
9
XTO2
FM modulation output
10
XTO1
Connection for crystal
11
PWRGND2
Power GND2
12
PWRGND1
Power GND1
13
ANT
14
PWRVCC
Supply voltage power amplifier
RF output
15
PWRSET
Applied to VCC
16
DIVIC
Pitch factor setting for crystal
L: high crystal frequency
H: low crystal frequency
3
4733B–RKE–09/05
3. General Description
The fully integrated VCO and the “single-ended open-collector” output allow particularly simple,
low-cost RF miniature transmitters to be assembled. The single-ended output enables a considerably simplified adaptation of both a magnetic loop antenna of any form or a λ/4 antenna. This
is because the load impedance must not be balanced as would be the case with a differential
output.
The XTO’s frequency can be selected at either 13.56 MHz (USA 9.844 MHz) or 6.78 MHz (USA
4.9219 MHz). Thus, it is possible to use not only exceptionally small SMD crystals at 13.56 MHz
but also very low-cost 6.78 MHz crystals in a wired metal package (e.g., in the HC49S housing).
The frequency is selected by connecting pin 16 (DIVC) to either GND or VS.
At high frequencies, crystals have a very fast start-up time (< 1.5 ms at 13.56 MHz, < 3 ms at
6.78 MHz), whereby a wait time of 5 to 10 ms is required until the transmitter IC is locked. This
means that the processor does not need to poll a lock detect output.
4. Functional Description
The IC can be switched on at both the FSK and the ASK input. The IC's ChipSelect is performed
by the logical OR operation of ASK and FSK input. In the case of VFSK, VASK ≤0.3V, the powerdown supply current is ISoff < 0.35 µA. The ASK input activates the power amplifier and the PLL.
The FSK input only activates the PLL and, if capacitor C3 is installed, pulls the crystal to the
lower frequency, whereby the transmitter is FSK modulated. After switching on at FSK, the VCO
locks onto the 32 or 64 times higher frequency of the crystal oscillator.
4.1
FSK Transmission
The U2741B is switched on by VFSK = VS. 5 ms later, VS is applied to VASK. The output can then
be modulated by means of pin FSK. This is done by connecting capacitor C3 in parallel to the
load capacitor C4.
4.2
ASK Transmission
The U2741B is activated by VFSK = VS. VASK remains 0V for 5 ms, then the output power can be
modulated by means of pin ASK. In this case, VFSK remains = VS during the message, the
capacitor C3 is not mounted.
4.3
Take-over of the Clock Pulse in the Microcontroller
The clock of the crystal oscillator can be used for clocking the microcontroller. The ATAR090
and ATAR890 have the special feature of starting with an integrated RC oscillator to switch on
the U2741B with VFSK = VS. 5 ms later, the 3.39-MHz clock frequency is present, so that the
message can be sent with crystal accuracy.
4
U2741B
4733B–RKE–09/05
U2741B
5. Application Circuit
The following component values are recommendations for a typical application. C5, C6, and C7
are block capacitors. The values of these capacitors depend on the board layout. C5 = 1 nF,
C6 = 1 nF, and C7 = 22 nF are typically used here. For C5, the impedance between f = 100 MHz
and f = 1 GHz should be as low as possible.
C3 is not needed in ASK transmitter applications. In the case of FSK, C3 is selected in such a
way that the desired transmission frequency deviation is achieved (typical ±30 kHz). The capacitance here depends upon the crystal's load capacity (C4) recommended by the manufacturer of
the crystal. C2 = 3.9 nF, C1 = 15 nF, and R4 = 220Ω.
CLoop1 and CLoop2 are selected so that the antenna oscillates in resonance and the adaptation to
the appropriate impedance transformation is possible.
LFeed is an inductor for the antenna's DC current supply. A typical value is LFeed = 220 nH. LFeed
can be either printed on the PC board or be a discrete component.
5.1
Output Power Measurement
The output network [as shown in Figure 5-1] can be used for output power evaluation, the exact
values of L10 and C10 depend on the layout.
L10 and C10 form the transformation network to adopt the output impedance of the IC to 50Ω.
Table 5-1 shows the values for an output power of 2 mW and an RPWRSET = 1.2 kΩ.
Table 5-1.
Transformation Network
f/MHz
C10/pF
L10/nH
ZLoad_opt/Ω
315
2.7
56
260 + j330
433.92
1.8
33
185 + j268
Figure 5-1.
Measurement Output Network
VS
PWRVCC
L10
ZLoad-opt
ANT
C10
50 Ω
5
4733B–RKE–09/05
Figure 5-2.
Application Circuit
+VS = 2.0 ... 5.5 V
DIVC
ASK
ASK
1
16
OR
15
2
VCC
3
C7
Power
up
CLK
CLK
PWRVCC
VCO
PA
5
n
PWRGND2
XTO
XTO1
13.56 MHz
10
7
8
CLoop1
11
f
LFGND
LF
LFeed
12
64
6
C1
C5
PWRGND1
f
LFVCC
R4
ANT
13
GND
C6
RPWRSET
14
4
3.39 MHz
CLoop2
PWRSET
FSK
FSK
U2741B
C4
XTO2
9
C3
C2
6
Antenna
U2741B
4733B–RKE–09/05
U2741B
6. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Max.
Unit
Supply voltage
Symbol
VS
6
V
Power dissipation
Ptot
250
mW
Tj
150
°C
Junction temperature
Min.
Storage temperature
Tstg
–55
125
°C
Ambient temperature
Tamb
–40
105
°C
7. Thermal Resistance
Parameters
Symbol
Value
Unit
RthJA
180
K/W
Junction ambient
8. Electrical Characteristics
All parameters are referred to GND (pin 5). The possible operating ranges refer to different circuit conditions:
VS = 2.0V to 5.5V at Tamb = –20°C to +70°C, VS = 2.2V to 5.5V at Tamb = –40°C to +85°C (typically 25°C, 3V)
Parameters
Test Conditions
Supply current (power down)
VASK, VFSK ≤ 0.3V, VS < 3.6V
Supply current (power up, output OFF) VASK = GND, VFSK = VS, Vs = 3V
Supply current (power up, output ON) VASK = VS, VS = 3V, RPWRSET = 1.2 kΩ
Output power
Output power variation for the full
temperature range
Output power variation for
f = 315 MHz compared to
f = 433.92 MHz
VS = 3V, Tamb = 25°C, f = 433.92 MHz
RPWRSET = 1.2 kΩ
RPWRSET = 1.8 kΩ
Symbol
Min.
Typ.
ISoff
Max.
Unit
0.35
µA
ISon
4.7
6.2
mA
IStransmit
10
12.5
mA
3
1
5
3
dBm
dBm
PRef
PRef
1.5
–0.5
Tamb = –40°C to +85°C, f = 433.92 MHz,
VS = 3.0V
VS = 2.4V
∆PRef
∆PRef
–1.5
–4.0
dB
dB
Tamb = –20°C to +85°C, f = 433.92 MHz,
VS = 2.0V
Pout = PRef + ∆PRef
∆PRef
–5.5
dB
f = 315 MHz
Pout = PRef + ∆PRef
Maximum peak output
antenna voltage
at Pout = 2.0 mW,
the load impedance must be selected to
meet the Vout maximum requirement
the supply current is not dependent on
the load impedance tolerance
Spurious emission
at Tamb = 25°C
fo ±(n × fPC) where fPC = 6.78 MHz
Load capacitance at CLK ≤ 3 pF
f = 230 MHz to 470 MHz
f < 230 MHz, f > 470 MHz
∆PRef
1.5
dB
Voutmax
VS – 0.7V
V(peak)
Em
Em
–40
–58
dBC
dBC
7
4733B–RKE–09/05
8. Electrical Characteristics (Continued)
All parameters are referred to GND (pin 5). The possible operating ranges refer to different circuit conditions:
VS = 2.0V to 5.5V at Tamb = –20°C to +70°C, VS = 2.2V to 5.5V at Tamb = –40°C to +85°C (typically 25°C, 3V)
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
M-version: at Tamb = 25°C
N-version: full temperature range
(monitoring)
Crystal frequency = 13.56 MHz
fXTO
13.56 –
30 ppm
13.56
13.56 +
30 ppm
MHz
Crystal frequency = 6.78 MHz
fXTO
6.78 –
30 ppm
6.78
6.78 +
30 ppm
MHz
Oscillator frequency XTO
Load capacity of the crystal must be
selected accordingly
Loop bandwidth
For best LO noise
Loop filter components:
C2 = 3.9 nF, C1 = 15 nF, R4 = 220Ω
BLoop
100
Phase noise PLL
Referring to the phase comparator
fPC = 6.78 MHz
PNPLL
–111
–105
dBC/Hz
Phase noise VCO
at 1 MHz
at 36 MHz
PNVCO
PNVCO
–91
–123
–87
–119
dBC/Hz
450
MHz
Frequency range of the VCO
fVCO
Clock output
(CMOS microcontroller compatible)
300
fout/128
Clkout
Load capacitance at CLK
kHz
MHz
CCLK
10
pF
Rs
Rs
Rs
Rs
80
100
150
225
Ω
Series resonance R of the crystal
fXTO = 13.56 MHz
fXTO = 9.84 MHz
fXTO = 6.78 MHz
fXTO = 4.90 MHz
FSK modulation frequency rate
Duty cycle of the
modulation signal = 50%
fmodFSK
0
20
kHz
ASK modulation frequency rate
Duty cycle of the
modulation signal = 50%
fmodASK
0
20
kHz
Iol
Iol
Ioh
Ioh
150
200
–150
–200
+100
µA
µA
µA
µA
ASK input
- Low level input voltage
- High level input voltage
- Input current High
VASKl
VASKh
IASKh
1.7
FSK input
- Low level input voltage
- High level input voltage
- Input current High
VFSKl
VFSKh
IFSKh
1.7
CLK output
- Output current Low
- Output current Low
- Output current High
- Output current High
8
VCLK = 0.2 ×
VCLK = 0.3 ×
VCLK = 0.8 ×
VCLK = 0.7 ×
VS
VS
VS
VS
0.3
140
0.3
140
V
V
µA
V
V
µA
U2741B
4733B–RKE–09/05
U2741B
9. Ordering Information
Extended Type Number
Package
Remarks
U2741B-NFBY
SSO16
Tube, optimized power-supply rejection, value of C4
differs from M-version, enhanced XTO stability, Pb-free
U2741B-NFBG3Y
SSO16
Taped and reeled, see above, Pb-free
10. Package Information
5 max.
0.6
1.4
1.7 max.
4.9±0.1
0.1+0.15
0.2
0.25
3.95 max.
0.635 nom.
5±0.2
7 x 0.635 = 4.445 nom.
6±0.2
16
9
Dimensions in mm
technical drawings
according to DIN
specifications
1
8
Drawing-No.: 6.543-5060.01-4
Drawing refers to following types: SSO16
Issue: 2; 05.02.99
Package acc. JEDEC MO 137 AB
9
4733B–RKE–09/05
11. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
10
Revision No.
History
4733B-RKE-09/05
• Put datasheet in a new template
• Pb-free Logo on page 1 added
• Ordering Information on page 9 changed
U2741B
4733B–RKE–09/05
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4733B–RKE–09/05