ATMEL U2731B

Features
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8.5 V Supply Voltage
Voltage Regulator for Stable Operating Conditions
Microprocessor-controlled Via a Simple Two-wire Bus
Two Addresses Selectable
Gain-controlled RF Amplifier with Two Inputs, Selectable Via a Simple Two-wire Bus
Control
Balanced RF Amplifier Inputs
Gain-controlled RF Mixer
Four-pin Voltage-controlled Oscillator
SAW Filter Driver with Differential Low-impedance Output
AGC Voltage Generation for RF Section, Available at Charge-pump Output
(Can Also Be Used to Control a PIN Diode Attenuator)
Gain-controlled IF Amplifier
Balanced IF Amplifier Inputs
Selectable Gain-controlled IF Mixer
Single-ended IF Output
AGC Voltage Generation for IF Section, Available at Charge-pump Output
Separate Differential Input for the IF AGC Block
All AGC Time Constants Adjustable
AGC Thresholds Programmable Via a Simple Two-wire Bus
Three AGC Charge Pump Currents Selectable (Zero, Low, High)
Reference Oscillator
Programmable 9-bit Reference Divider
Programmable 15-bit Counter 1:2048 to 1:32767 Effectively
Tristate Phase Detector with Programmable Charge Pump
Superior Phase-noise Performance
Deactivation of Tuning Output Programmable
Three Switching Outputs (Open Collector)
Three D/A Converters (Resolution: 8 Bits)
Lock Status Indication (Open Collector)
DAB One-chip
Front End
U2731B
Electrostatic sensitive device.
Observe precautions for handling.
Description
The U2731B is a monolithically integrated Digital Audio Broadcasting one-chip front
end circuit manufactured using Atmel’s advanced UHF5S technology. Its functionality
covers a gain-controlled RF amplifier with two selectable RF inputs, a gain-controlled
RF mixer, a VCO which provides the LO signal for the RF mixers, either directly or
after passing a frequency divider, a SAW filter driver, an AGC block for the RF section,
a gain-controlled IF amplifier, an IF mixer which can also be bypassed, an AGC block
for the IF section and a fractional-N frequency synthesizer. The frequency synthesizer
controls the VCO to synthesize frequencies in the range of 70 MHz to 500 MHz in a
16-kHz raster; within certain limits the reference divider factor is fully programmable.
The lock status of the phase detector is indicated at a special output pin; three switching outputs can be addressed. A reference signal which is generated by an on-chip
reference oscillator is available at an output pin. This reference signal is also used to
generate the LO signal for the IF mixer, either by doubling the frequency or by using
the reference frequency itself. Three D/A converters at a resolution of 8 bits provide a
digitally controllable output voltage. The thresholds inside the AGC blocks can be digitally controlled by means of on-chip 4-bit D/A converters. All functions of this IC are
controlled via a simple two-wire bus.
Rev. 4671C–DAB–06/04
Figure 1. Block Diagram
SAW1
SAW2
18
19
IFIN1
24
IFIN2
CPIF
23
28
26
IF
AGCIN2
27
CPRF
th1
16
IF
AGCIN1
th3
21
SLI
22
WAGC
V AGC
V AGC
th2
12
RFA1
13
RFA2
29
IFOUT
14
RFB1
15
RFB2
C1VCO
B2VCO
B1VCO
C2VCO
32
33
34
35
VCO
1/
2
x1/x2
20, 25, 38
D/A
D/A
VS
D/A
10, 11, 17, 30, 31,36, 37
GND
4-bit latch
4-bit latch
4-bit latch
4-bit latch
41
Lock
detector
PLCK
39
PD
42
Tristate
phase
detector
Programmable
charge pump
3-bit latch
8-bit latch
8-bit latch
8-bit latch
D/A
D/A
D/A
Reference
counter
OSCI
40
VD
43
OSCO
5
Fractional-N
control
FREF
Programmable
13-bit counter
N/N+1
9-bit latch
4-bit latch
15-bit latch
MUX
Simple two-wire bus interface/control
44
ADR
2
1
2
SCL
SDA
MUX
Switches
4
7
8
9
SWA SWC SWB
3
6
CAO
CCO
CBO
U2731B
4671C–DAB–06/04
U2731B
Pin Configuration
Figure 2. Pinning
SCL
1
44
ADR
SDA
2
43
OSCO
SWA
3
42
OSCI
SWB
4
41
PLCK
FREF
5
40
VD
SWC
6
39
PD
CAO
7
38
VS
CCO
8
37
GND
CBO
9
36
GND
GND
10
35
C2VC
GND
11
34
B1VCO
RFA1
12
33
B2VCO
RFA2
13
32
C1VC
RFB1
14
31 GND
RFB2
15
30
GND
CPRF
16
29
IFOUT
GND
17
28
CPIF
SAW1
18
27
IFAGCIN1
SAW2
19
26
IFAGCIN2
VS
20
25
VS
SLI
21
24
IFIN1
WAGC
22
23
IFIN2
3
4671C–DAB–06/04
Pin Description
4
Pin
Symbol
Function
1
SCL
Clock (simple two-wire bus)
2
SDA
Data (simple two-wire bus)
3
SWA
Switching output (open collector)
4
SWB
Switching output (open collector)
5
FREF
Reference frequency output (for U2731B)
6
SWC
Switching output (open collector)
7
CAO
Output of D/A converter A
8
CCO
Output of D/A converter B
9
CBO
Output of D/A converter C
10
GND
Ground
11
GND
Ground
12
RFA1
Input 1 of RF amplifier A (differential)
13
RFA2
Input 2 of RF amplifier A (differential)
14
RFB1
Input 1 of RF amplifier B (differential)
15
RFB2
Input 2 of RF amplifier B (differential)
16
CPRF
Charge-pump output (RF AGC block)
17
GND
Ground
18
SAW1
SAW driver output 1 (differential)
19
SAW2
SAW driver output 2 (differential)
20
VS
Supply voltage RF part
21
SLI
AGC mode selection (charge-pump current high)
22
WAGC
AGC mode selection (charge-pump current off)
23
IFIN2
Input 2 of IF amplifier (differential)
24
IFIN1
Input 1 of IF amplifier (differential)
25
VS
26
IFAGCIN2
27
IFAGCIN1
Input 1 of IF AGC block (differential)
28
CPIF
Charge-pump output (IF AGC block)
29
IFOUT
30
GND
Ground
31
GND
Ground
32
C1VC
Collector 1 of VCO
33
B2VCO
Base 2 of VCO
34
B1VCO
Base 1 of VCO
35
C2VC
Collector 2 of VCO
36
GND
Ground
37
GND
Ground
38
VS
Supply voltage IF part
Input 2 of IF AGC block (differential)
IF output (single ended)
Supply voltage PLL
39
PD
Tri-state charge pump output
40
VD
Active filter output
U2731B
4671C–DAB–06/04
U2731B
Pin Description (Continued)
Pin
Symbol
Function
41
PLCK
Lock-indicating output (open collector)
42
OSCI
Input of reference oscillator/buffer
43
OSCO
Output of reference oscillator/buffer
44
ADR
Address selection (simple two-wire bus)
Functional Description
The U2731B represents a monolithically integrated front end IC designed for applications in DAB receivers. It covers RF and IF signal processing, the PLL section and also
supporting functions such as D/A converters or switching outputs.
Two RF input ports offer the possibility of handling various input signals such as a downconverted L-band signal or band II and band III RF signals. The high dynamic range of
the RF inputs and the use of a gain-controlled amplifier and a gain-controlled mixer in
the RF section offer the possibility of handling even strong RF input signals. The LO
signal of the first mixer stage is derived from an on-chip VCO. The VCO frequency is
either divided by two or directly fed to the mixer. In this way band II and band III can be
covered easily.
In the IF section, it can be selected if the first IF signal is down-converted to a second,
lower IF or if it is simply amplified to appear at the IF output. If the down-conversion
option is chosen, it can be selected if the LO signal of the IF mixer is directly derived
from the reference signal of the PLL, or if it is generated by doubling its frequency. The
amplifiers in the IF section are gain-controlled in similar fashion to the RF section.
The RF and the IF part also contain AGC functional blocks which generate the AGC
control voltages. The AGC thresholds can be defined by means of three on-chip 4-bit
D/A converters.
The frequency of the VCO is locked to a reference frequency by an on-chip fractional-N
PLL circuit which guarantees a superior phase-noise performance. The reference
frequency is generated by an on-chip crystal oscillator which can also be overdriven by
an external signal. Starting from a minimum value, the reference scaling factor is freely
programmable.
Three switching outputs can be used for various switching tasks on the front end board.
Three 8-bit D/A converters providing an output voltage between 0 and 8.5 V are used to
improve the tuning voltages of the tuned preselectors which are derived from the tuning
voltage of the VCO.
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4671C–DAB–06/04
RF Part
RF Gain-controlled
Amplifier
In order to support two different channels, two identical input buffers with balanced
inputs (RFA1, RFA2; RFB1, RFB2) are integrated. By setting the two-wire bus bits M0
and M1 (see section “Simple Two-wire Bus Functions” on page 11), the active buffer
can be selected. The buffers are followed by a gain-controlled amplifier whose output
signal is fed to a gain-controlled mixer. The RF amplifiers are capable of handling input
signals up to a typical power of -6 dBm without causing third-order intermodulation components stronger than -40 dBc.
RF Gain-controlled
Mixer, VCO and LO
Divider
The purpose of the RF mixer is to down-convert the incoming signal (band II, band III) to
an IF frequency which is typically 38.912 MHz. This IF signal is fed to an AGC voltagegeneration block (which is described in the following section) and an output buffer stage.
This driver stage has a low output impedance and is capable of driving a SAW filter
directly via its differential output pins SAW1, SAW2. The mixer's LO signal is generated
by a balanced voltage-controlled oscillator whose frequency is stabilized by a fractional-N phase-locked loop. An example circuit of the VCO is shown in Figure 12 on
page 23. The oscillator's tank is applied to the pins B1VC, C1VC, B2VC, C2VC as
shown in the application circuit in Figure 8 on page 20. Before the VCO's signal is fed to
the RF mixer, it has to pass an LO divider block where the VCO frequency is either
divided by 1 or 2. The setting of this divider is defined by means of the two-wire bus bits
M0 and M1 as indicated in the section “Simple Two-wire Bus Functions” on page 11.
This feature offers the possibility of covering both band II and band III by tuning the VCO
frequency in the range between 200 MHz to 300 MHz.
RF AGC
In this functional block, the output signal of the RF mixer is amplified, weakly bandpass
Voltage-generation Block filtered (transition range: X8 MHz to X80 MHz), rectified and finally lowpass filtered. The
voltage derived in this power-measurement process is compared to a voltage threshold
(th1) which can be digitally controlled by an on-chip 4-bit D/A converter. The setting of
this converter is defined by means of the two-wire bus bits TAi (i = 1, 2, 3, 4). Depending
on the result of this comparison, a charge pump feeds a positive or negative current to
pin CPRF in order to charge or discharge an external capacitor. The voltage of this
external capacitor can be used to control the gain of an external preamplifier or attenuator stage. Furthermore, it is also used to generate the internal control voltages of an RF
amplifier and mixer. For this purpose, the voltage at pin CPRF is compared to a voltage
threshold (th2) which is also controlled by an on-chip 4-bit D/A converter whose setting
is fixed by the two-wire bus bits TBi (i =1, 2, 3, 4).
By means of the input pins WAGC and SLI the current of the RF AGC charge pump can
be selected according to the following table:
Table 1. Current of Charge Pump
WAGC
SLI
Charge-pump Current/µA
HIGH
X
off
LOW
LOW
50 µA (slow mode)
LOW
HIGH
190 µA (fast mode)
The function can be seen in Figure 11 on page 22.
6
U2731B
4671C–DAB–06/04
U2731B
IF Part
IF Gain-controlled
Amplifier
The signal applied to the balanced input pins IFIN1, IFIN2 is amplified by a gain-controlled IF amplifier. The gain-control signal is generated by an IF AGC voltagegeneration block which is described in the next section. To avoid offset problems, the
output of the gain-controlled amplifier is fed to an amplifier/mixer combination by AC
coupling.
IF Gain-controlled
Amplifier/Mixer
Combination
Depending on the setting of the two-wire bus bits M2, M3, the output signal of the gaincontrolled IF amplifier is either mixed down to a lower, second IF or, after passing an
output buffer stage, amplified before it appears at the single-ended output pin IFOUT. If
the down-conversion option is chosen this circuit still offers two possibilities concerning
the synthesis of the IF mixers LO signal. This LO signal is derived from the PLL's onchip reference oscillator. By means of the two-wire bus bits M2, M3, it can be decided
whether the reference frequency is doubled before it is given to the mixer's LO port, or if
it is used directly. The gain-control voltage of the amplifier/mixer combination is similar
to the gain-controlled IF amplifier generated by an internal gain-control circuit.
IF AGC
The purpose of this gain-control circuit in the IF part is to measure the power of the
Voltage-generation Block incoming signal at the balanced input pins IFAGCIN1, IFAGCIN2, to compare it with a
certain power level and to generate a control voltage for the IF gain-controlled amplifiers
and mixer. This architecture offers the possibility of ensuring an optimal use of the
dynamic range of the A/D converter which transforms the output signal at pin IFOUT
from the analog to the digital domain despite possible insertion losses of (anti-aliasing)
filters which are arranged in front of the converter. Such a constellation is indicated in
the application circuit in Figure 8 on page 20.
The incoming signal at the balanced input pins IFAGC1, IFAGC2 passes a power-measurement process similar to that described in the section “RF AGC Voltage-generation
Block” on page 6. For flexibility reasons, no bandpass filtering is implemented. The voltage derived in this process is compared to a voltage threshold (th3) which is defined by
an on-chip 4-bit D/A converter. The setting of this converter is defined by the two-wire
bus bits TCi (i = 1, 2, 3, 4). Depending on the result of this comparison, a charge pump
feeds a positive or negative current to pin CPIF in order to charge or discharge an external capacitor. By means of the pins WAGC and SLI the current of this charge pump can
be selected according to the following table:
Table 2. Current of Charge Pump
WAGC
SLI
Charge-pump Current/µA
HIGH
X
off
LOW
LOW
50 µA (slow mode)
LOW
HIGH
190 µA (fast mode)
The function can be seen in Figure 12 on page 23.
7
4671C–DAB–06/04
PLL Part
The purpose of the PLL part is to perform a phase lock of the voltage-controlled RF
oscillator to an on-chip crystal reference oscillator. This is achieved by means of a special phase-noise-shaping technique based on the fractional-N principle which is already
used in Atmel's U2733B frequency synthesizer series. It concentrates the phase detector's phase-noise contribution to the spectrum of the controlled VCO at frequency
positions where it does not impair the quality of the received DAB signal. A special property of the transmission technique which is used in DAB is that the phase-noiseweighting function which measures the influence of the LO's phase noise to the phase
information of the coded signal in a DAB receiver has zeros, i.e., if phase noise is concentrated in the position of such zeros as discrete lines, the DAB signal is not impaired
as long as these lines do not exceed a set limit. For DAB mode I, this phase-noiseweighting function is shown in Figure 3.
Figure 3. Phase-noise-weighting Function
1,80
1,60
1,40
PNWF
1,20
1,00
0,80
0,60
0,40
0,20
0,00
0
1000
2000
3000 4000
5000 6000
7000 8000
9000 10000
df/Hz
It is important to realize that this function shows zeros in all distances from the center
line which are multiples of the carrier spacing. The technique of concentrating the phase
noise in the positions of such zeros is patent protected.
Reference Oscillator
An on-chip crystal oscillator generates the reference signal which is fed to the reference
divider. As already described in the section “IF Gain-controlled Amplifier/Mixer Combination” on page 7, the LO signal for the mixer in the IF section is derived. By applying a
crystal to the pins OSCI, OSCO, see Figure 8 on page 20, this oscillator generates a
highly stable reference signal. If an external reference signal is available, the oscillator
can be used as an input buffer. In such an application, see Figure 9 on page 21, the
reference signal has to be applied to the pin OSCI and the pin OSCO must be left open.
Reference Divider
Starting from a minimum value, the scaling factor SFref of the 9-bit reference divider is
freely programmable by means of the two-wire bus bits ri (i = 0, ..., 8) according to
SF ref =
8
∑ri × 2
i
U2731B
4671C–DAB–06/04
U2731B
If, for example, a frequency raster of 16 kHz is requested, the scaling factor of the reference divider has to be specified in such a way that the division process results in an
output frequency which is four times higher than the desired frequency raster, i.e., the
comparison frequency of the phase detector equals four times the frequency raster. By
changing the division ratio of the main divider from N to N+1 in an appropriate way
(fractional-N technique), this frequency raster is interpolated to deliver a frequency
spacing of 16 kHz. So effectively a reference scaling divide factor
SF ref,eff = 4 ×
∑ri × 2
i
is achieved.
By setting, the two-wire bus bit T, a test signal representing the divided input signal can
be monitored at the switching output SWA.
Main Divider
The main divider consists of a fully programmable 13-bit divider which defines a division
ratio N. The applied division ratio is either N or N+1 according to the control of a special
control unit. On average, the scaling factors SF = N + k/4 can be selected where k = 0,
1, 2 or 3.
In this way, VCO frequencies fVCO = 4 × (N+k/4) × fref/(4 × SFref) can be synthesized
starting from a reference frequency fref. If we define SF e f f = 4 × N + k and
SFref,eff = 4 × SFref (previous section), then fVCO = SFeff × fref/SFref,eff, where SFeff is
defined by 15 bits.
In the following, this circuit is described in terms of SFeff and SFref,eff. SFeff has to be programmed via the two-wire bus interface. An effective scaling factor from 2048 to 32767
can be selected by means of the two-wire bus bits ni (i = 0, ..., 14) according to
SF eff =
∑ni × 2
i
By setting the two-wire bus bit T, a test signal representing the divided input signal can
be monitored at the switching output SWC.
When the supply voltage is switched on, both the reference divider and the programmable divider are kept in RESET state until a complete scaling factor is written onto the
chip. Changes in the setting of the programmable divider become active when the corresponding two-wire bus transmission is completed. An internal synchronization
procedure ensures that such changes do not become active while the charge pump is
sourcing or sinking current at its output pin. This behavior allows a smooth tuning of the
output frequency without restricting the controlled VCO's frequency spectrum.
Phase Comparator and
Charge Pump
The tri-state phase detector causes the charge pump to source or to sink current at the
output Pin PD depending on the phase relation of its input signals which are provided by
the reference and the main divider respectively. Four different values of this current can
be selected by means of the two-wire bus bits I50 and I100. By use of this option,
changes of the loop characteristics due to the variation of the VCO gain as a function of
the tuning voltage can be reduced. The charge-pump current can be switched off using
the two-wire bus bit TRI. A change in the setting of the charge pump current becomes
active when the corresponding two-wire bus transmission is completed. As described for
the setting of the scaling factor of the programmable divider, an internal synchronization
procedure ensures that such changes do not become active while the charge pump is
sourcing or sinking current at its output pin. This behavior allows a change in the charge
pump current without restricting the controlled VCO's frequency spectrum.
9
4671C–DAB–06/04
A high-gain amplifier (output pin: VD), which is implemented in order to construct a loop
filter, as shown in the application circuit, can be switched off by means of the two-wire
bus bit OS.
An internal lock detector checks if the phase difference of the input signals of the phase
detector is smaller than approximately 250 ns in seven subsequent comparisons. If
phase lock is detected, the open collector output pin PLCK is set to H (logical value). It
should be noted that the output current of this pin must be limited by external circuitry as
it is not limited internally. If the two-wire bus bit TRI is set to H, the lock detector function
is deactivated and the logical value of the PLCK output is undefined.
Switching Outputs
Three switching outputs controlled by the two-wire bus bits SWA, SWB, SWC can be
used for any switching task on the front-end board. The currents of these outputs are not
limited internally. They have to be limited by an external circuit.
D/A Converters
Three D/A converters, A, B and C, offer the possibility of generating three output voltages at a resolution of 8 bits. These voltages appear at the output pins CAO, CBO and
CCO. The converters are controlled via the two-wire bus interface by means of the control bits CA0, ..., CA7, CB0, ..., CB7 and CC0, ..., CC7 respectively as described in the
section “Two-wire Bus Instruction Codes”. The output voltages are defined as
V CAO
VM
= ---------- ×
128
7
∑CAj × 2
j
j=0
V CBO
VM
= ---------- ×
128
7
∑CBj × 2
j
j=0
V CCO
VM
= ---------- ×
128
7
∑CCj × 2
j
j=0
where VM = 4.25 V nominally. Due to the rail-to-rail outputs of these converters, almost
the full voltage range from 0 to 8.5 V can be used. A common application of these
converters is the digital synthesis of control signals for the tuning of preselectors. The
output pins CAU, CBO and CCO must be blocked externally with capacitors (100 nF) as
shown in the application circuit (see Figure 8 on page 20).
10
U2731B
4671C–DAB–06/04
U2731B
Simple Two-wire Bus
Interface
Via its two-wire bus interface, various functions can be controlled by a microprocessor.
These functions are outlined in the following table “Simple Two-wire Bus Instruction
Codes” on page 11 and in the section “Simple Two-wire Bus Functions” on page 11. The
programming information is stored in a set of internal registers. By means of the Pin
ADR, two different two-wire bus addresses can be selected as described in the section
“Electrical Characteristics”. In Figure 6 on page 19, the two-wire bus timing parameters
are explained, Figure 7 on page 20 shows a typical two-wire bus pulse diagram.
Table 3. Simple Two-wire Bus Instruction Codes
Description
MSB
LSB
Address
1
1
0
0
0
AS1
0
0
A byte 1
0
0
X
X
X
n14
n13
n12
A byte 2
X
X
n11
n10
n9
n8
n7
n6
A byte 3
X
X
n5
n4
n3
n2
n1
n0
B byte 1
0
1
X
r8
TA3
TA2
TA1
TA0
B byte 2
r7
r6
r5
r4
TB3
TB2
TB1
TB0
B byte 3
r3
r2
r1
r0
TC3
TC2
TC1
TC0
C byte 1
1
0
X
X
X
X
X
X
C byte 2
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
C byte 3
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
D byte 1
1
1
0
OS
T
TRI
I100
I50
D byte 2
SWA
SWB
SWC
X
M3
M2
M1
M0
D byte 3
CC7
CC6
CC5
CC4
CC3
CC2
CC1
CC0
Simple Two-wire Bus
Functions
AS1
Defines the two-wire bus address
ni
Deffective scaling factor (SFeff) of the main divider SF eff =
ri
Scaling factor (SFref,eff) of the reference divider SFref,eff = 4 × ri 2i
TAi
Define the setting of a 4-bit D/A converter controlling the threshold,
th1, of the RF AGC to adjust the controlled output power
TBi
Define the setting of a 4-bit D/A converter controlling the threshold,
th2, which determines the activation voltage for the internal RF AGC
TCi
Define the setting of a 4-bit D/A converter controlling the threshold,
th3, of the IF AGC to adjust the output power
CAi, CBi, CCi
OS
Define the setting of the three D/A converters A, B and C (i = 0, ..., 7)
OS = HIGH switches off the tuning output
T
For T = HIGH, reference signals describing the output frequencies of
the reference divider and programmable divider are monitored at
SWA (reference divider) and SWC (programmable divider).
TRI
TRI = HIGH switches off the charge pump
∑ni × 2
i
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4671C–DAB–06/04
I50 and I100 define the charge pump current:
Table 4. Current of Charge Pump
I50
I100
Charge-pump Current
(nominal)/µA
LOW
LOW
50
HIGH
LOW
100
LOW
HIGH
150
HIGH
HIGH
200
Mi defines the operation mode:
Table 5. Mode Selection
M3
M2
M1
M0
Mode
LOW
LOW
X
X
fLO,IFMIX = fref
LOW
HIGH
X
X
fLO,IFMIX = 2 × fref
HIGH
HIGH
X
X
IF mixer switched off
X
X
LOW
LOW
RF mixer A active, fLO,RFMIX = fVCO
X
X
HIGH
LOW
RF mixer B active, fLO,RFMIX = fVCO
X
X
HIGH
HIGH
RF mixer B active, fLO,RFMIX = fVCO/2
Note:
Simple Two-wire Bus
Data Transfer
SWα = HIGH switches on the output current (α = A, B, C)
Format:
START - ADR - ACK - <instruction set> - STOP
The <instruction set> consists of a sequence of A bytes, B bytes, C bytes and D bytes
each followed by ACK. Always a triplet of these bytes (A, B, C or D) has to be completed
before a new triplet is started. If no new triplet is started the transmission can be finished
before the current triplet is finished.
Examples:
START - ADR - ACK - DB1 - ACK - DB2 - ACK - DB3 - ACK - CB1 - ACK - CB2 - ACK CB3 - ACK - AB1 - ACK - AB2 - ACK - AB3 - ACK - BB1 - ACK - BB2 - ACK - BB3 - ACK
- STOP
START - ADR - ACK - CB1 - ACK - CB2 - ACK - STOP
However:
START - ADR - ACK - DB1 - ACK - CB1 -ACK - STOP is not allowed.
Description:
START
STOP
ACK
ADR
αBi
12
Start condition
Stop condition
Acknowledge
Address byte
α byte i (α = A, B, C, D; i = 1, 2, 3)
U2731B
4671C–DAB–06/04
U2731B
Simple Two-wire Bus
Timing
The values of the periods shown are specified in the table “Electrical Characteristics” on
page 15. More detailed information can be taken from the “Application Note 1.0 (Twowire Bus Description)”. Please note, that due to the two-wire bus specification, the MSB
of a byte is transmitted first, the LSB last.
Figure 4. Two-wire Bus Timing
Stop
Start
Start
Stop
SDA
t buf
tr
tf
t hdstat
SCL
t hdsta
t low
t hddat
thigh
t sudat
t susta
t sustp
Figure 5. Typical Pulse Diagram
START
ADDRESS BYTE
ACK
A BYTE 1
ACK
A BYTE 2
ACK
SDA
SCL
A BYTE 3
ACK
C BYTE 1
ACK
C BYTE 2
ACK STOP
SDA
SCL
13
4671C–DAB–06/04
Absolute Maximum Ratings
Parameters
Symbol
Min.
Max.
Unit
Supply voltage
VS
-0.3
+9.5
V
Junction temperature
Tj
150
°C
-40
+150
°C
Storage temperature
Tstg
Differential input RF amplifier, pins 12 and 13
VRFA1,2
500
mVrms
Pins 14 and 15
VRFB1,2
500
mVrms
Externally applied voltage at RF charge pump output, pin 16
VCPRF
0.5
6.75
V
Pin 28
VCPIF
0.5
6.25
V
WAGC input voltage, pin 22
VWAGC
-0.3
5.5
V
SLI input voltage, pin 21
VSLI
-0.3
5.5
V
Differential base input VCO, pins 33 and 34
VBiVC
500
mVrms
Differential input IF amplifier, pins 23 and 24
VIFIN
500
mVrms
VIFAGCIN
500
mVrms
VOSCI
1
Vpp
-0.3
5.5
V
Differential input IF AGC block, pins 26 and 27
Reference input voltage (AC), pin 42
Two-wire bus input/output voltage, pins 1 and 2
SCL, SDA
SDA output current, pin 2
SDA
5
mA
Address select voltage, pin 44
ADR
-0.3
5.5
V
Switch output voltage; pins 3, 4 and 6
SWα
-0.3
9.5
V
Switch output current
SWα
4
mA
PLCK output voltage, pin 41
PLCK
PLCK output current, pin 41
PLCK
-0.3
5.5
V
0.5
mA
Thermal Resistance
Parameters
Junction ambient (soldered on application board)
Symbol
Value
Unit
RthJA
40
K/W
Symbol
Value
Unit
VS
8.0 to 9.35
V
Tamb
-40 to +85
°C
Operating Range
Parameters
Supply voltage
Ambient temperature range
14
U2731B
4671C–DAB–06/04
U2731B
Electrical Characteristics
Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C
No. Parameters
1
Test Conditions
Overall Characteristics
Supply voltage
1.2
V(CPRF) = V(CPIF) < 0.8 V
M3 = M2 = HIGH
M1 = M0 = LOW
TAi = TCi = 0000; TBi = 1000
Minimum supply current
SWA = SWB = SWC = LOW
TRI = LOW; PLCK = LOW
I100 = I50 = LOW; V(ADR) = open
SLI = LOW; WAGC = HIGH
2
Maximum supply
current
Symbol
Min.
Typ.
Max.
Unit
VS
8.0
8.5
9.35
V
Type*
20, 25, 38
1.1
1.3
Pin
3.4 V < V(CPRF) = V(CPIF)
< 3.6 V; M3 = M2 = HIGH
M1 = M0 = LOW
TAi = TCi = 0000; TBi = 1000
SWA = LOW; SWB = LOW
SWC = LOW; TRI = LOW
PLCK = LOW; I100 = I50 = LOW
V(ADR) = open; SLI = LOW
WAGC = HIGH
IS,min
74
mA
B
IS,max
79
mA
B
RF Part
RFA1, RFA2; RFB1, RFB2) →
SAW1, SAW2
(see Figure 9 on page 21)
12 (14)
→18, 19
2.1
Voltage gain
2.2
AGC range RF
2.3
Noise figure
(double side band)
RFA1, (RFB1) →SAW1, SAW2;
RFA2, RFB2 blocked
12 (14)
→19
NFDSB,RF
2.4
Maximum input power
level
Differential, 3rd order
intermodulation distance ≥ 40 dBc, 12, 13
Pout = -19 dBm, TAi = 0000,
(14, 15)
RL (SAW1, SAW2) = 200 Ω
Pin,max,MIX
-10
2.5
Input frequency range
12, 13
(14, 15)
fin,RF
70
2.6
Input impedance
12 (14)
Zin,RF
2.7
Output frequency range
for AGC-voltage
generation
18, 19
fout,SAW
2.8
Output power, differential;
Maximum output power
RL (SAW1, SAW2) > 200 Ω,
level
TAi = 0000
18, 19
2.9
AGC threshold (th1)
TAi = ‘1000’
TAi = ‘1111’
TAi = ‘0000’
18, 19
Single ended
Output power, differential
controlled by two-wire bus bits TAi;
RL (SAW1, SAW2) = 200 Ω
GV,RF
pTH,RF
20
24
26
dB
A
23
27
29
dB
A
dB
D
dBm
A
MHz
B
1.3
kΩ
D
38,912
±5
MHz
D
-7
dBm
D
12
50
260
90
160
10
120
mVrms
A
B
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency
of the phase detector divided by 4 according to the fractional-N technique (regularly: 16 kHz).
15
4671C–DAB–06/04
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C
No. Parameters
Test Conditions
AGC threshold (th2)
Controlled by two-wire bus bits TBi;
(internal AGC)
2.10
upper limit (TBi = 1111) PIN,MAX = -25 dBm
lower limit (TBi = 0000)
2.11 Output impedance
3
Phase noise
3.2
Phase noise
Vint AGC,RF
18 (19)
Min.
Typ.
Max.
Unit
Type*
1.0
5.1
1.5
1.8
V
V
B
A
Zout,SAW
30
Ω
L(f)
-88
dBc/Hz
D
400
MHz
D
fLO
100
IF Part
4.1
Voltage gain
4.2
Voltage gain
IFIN2 blocked
(see Figure 9 on page 21)
IF mixer switched off
4.3
AGC range IF
4.4
Noise figure
(double side band)
IFIN2 blocked
4.5
Maximum input power
level
IFIN2 blocked, 3rd order
intermodulation distance ≥ 40 dBc;
RL(IFOUT) = 1 k; TCi = 0000;
R10 = 4.7 k, R11 = 1.8 k
4.6
Input frequency range
4.7
Input impedance
4.8
Output frequency range Single ended
5
16
∆f = 10 kHz
IFIN2 blocked
(see Figure 9 on page 21)
fLO,IFMIX = fref or
FLO,IFMIX = 2 × fref
4.9
Symbol
VCO
3.1
4
Single ended; f(SAW1) = 39 MHz
Pin
Output impedance
24 →29
GV,tot
42
44
48
dB
A
24 →29
GV,tot
45
47
51
dB
A
42
44
48
dB
A
dB
D
dBm
C
MHz
D
Ω
D
MHz
D
24 →29
NFDSB
24
Pin,max
-20
23, 24
fin,IFIN
10
23, 24
Zin,IFIN
29
fout,IFO
Single ended
fout,IFO (3 MHz)
fout,IFO (20 MHz)
fout,IFO (38.9 MHz)
29
Zout,IFOUT
IFIN2 blocked, fIF,IFIN = 38.912 MHz
11
60
600 j1000
1
45
Ω
Ω
Ω
20 + j50
65 + j35
58 - j25
D
RF AGC Unit
5.1
Positive charge pump
current, fast mode
VWAGC = LOW
VSLI = HIGH
16
ICPRFPOS,FM
145
180
220
µA
A
5.2
Negative charge pump VWAGC = LOW
current, fast mode
VSLI = HIGH
16
ICPRFNEG,FM
-220
-180
-145
µA
A
5.3
Positive charge pump
current, slow mode
VWAGC = LOW
VSLI = LOW
16
ICPRFPOS,SM
30
40
52
µA
A
5.4
Negative charge pump VWAGC = LOW
current, fast mode
VSLI = LOW
16
ICPRFNEG,FM
-52
-40
-30
µA
A
5.5
Minimum gain control
voltage
VAGCmin
0.75
V
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency
of the phase detector divided by 4 according to the fractional-N technique (regularly: 16 kHz).
16
U2731B
4671C–DAB–06/04
U2731B
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C
No. Parameters
5.6
6
Test Conditions
Pin
Maximum gain control
voltage
Symbol
Min.
VAGCmax
Typ.
Max.
6.6
Unit
Type*
V
C
IF AGC Unit
6.1
Positive charge pump
current, fast mode
VWAGC = LOW
VSLI = HIGH
28
ICPIFPOS,FM
145
180
220
µA
A
6.2
Negative charge pump VWAGC = LOW
current, fast mode
VSLI = HIGH
28
ICPIFNEG, FM
-220
-180
-145
µA
A
6.3
Positive charge pump
current, slow mode
VWAGC = LOW
VSLI = LOW
28
ICPIFPOS, SM
30
40
52
µA
A
6.4
Negative charge pump VWAGC = LOW
current, slow mode
VSLI = LOW
28
ICPIFNEG, SM
-52
-40
-30
µA
A
6.5
Window AGC mode
charge pump current
28
ICPIFWAGC
-4
0
+4
µA
A
6.6
Minimum gain control
voltage
28
VAGCIFmin
0.75
V
C
6.7
Maximum gain control
voltage
28
VAGCIFmax
5.9
V
C
6.8
Control voltage for
activated WAGC
WAGC = HIGH
22
VWAGCHigh
V
A
6.9
Control voltage for
deactivated WAGC
WAGC = LOW
22
VWAGCLow
V
A
6.10
Control voltage for
activated SLI
SLI = HIGH
21
VSLIHigh
V
A
6.11
Control voltage for
deactivated SLI
SLI = LOW
21
VSLILow
7
VWAGC = HIGH
2.0
0.7
2.0
0.7
A
PLL Part
7.1
Effective scaling factor
of programmable
divider
SFeff
2048
32766
D
7.2
Effective scaling factor
of reference divider
SFref,eff
144
2047
D
7.3
Tuning step
8
REF Input
16
Input frequency range
Internal oscillator overdriven
fref
8.2
Input sensitivity
Internal oscillator overdriven
vref,min
8.3
Maximum input signal
Internal oscillator overdriven
vref,max
8.4
Input impedance
Single ended
9
REF Output
Output voltage
D
30
MHz
B
50
mVrms
A
mVrms
D
2 || 2.5
kΩ/pF
D
100
mVrms
A
42
8.1
9.1
kHz
5
300
Zref
5
1.5 kΩ || 2.5 pF load
vout,ref
65
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency
of the phase detector divided by 4 according to the fractional-N technique (regularly: 16 kHz).
17
4671C–DAB–06/04
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C
No. Parameters
10
10.3
Symbol
Min.
Typ.
Max.
Unit
Type*
I100 = HIGH, I50 = HIGH
I PD4
160
200
240
µA
A
I100 = HIGH, I50 = LOW
I PD3
120
150
180
µA
A
I100 = LOW, I50 = HIGH
I PD2
80
100
120
µA
A
50
65
µA
A
100
nA
A
dBc/
Hz
C
Phase Detector
10.1
10.2
Test Conditions
Charge-pump current
Pin
39
10.4
I100 = LOW, I50 = LOW
I PD1
35
10.5 High impedance mode
TRI = HIGH
IPD,tri
-100
10.6 Effective phase noise(1) IPD = 203 mA
11
Lock Indication
VPLCK = 5.5 V
11.2 Saturation voltage
IPLCK = 0.25 mA
Switches
13
IPLCK,L
10
µA
A
VPLCK,sat
0.5
V
A
ISW,L
10
µA
A
VSW,sat
0.5
V
A
3, 4, 6
12.1 Leakage current
12.2 Saturation voltage
-159
41
11.1 Leakage current
12
LPD
ISW = 0.25 mA
Address Selection
44
13.1 AS1 = 0
0
0.1 VS
C
13.2 AS1 = 1
0.4
VS
0.6 VS
C
14
D/A Converters
7, 8, 9
14.1 Output voltage
Cα7 = HIGH
Cα0 to Cα6 = LOW
α = A, B, C
VM
4.05
14.2 Variation of VM
VS = 8.00 to 9.35 V
∆VM,VS
-50
14.3 Variation of VM
Tamb = -40 to +85° C
∆VM,temp
14.4 Accuracy
VCαn-n VM/128
n = 24 ... 232, α = A, B, C
14.5
15
∆VCαn
Simple Two-wire Bus
-70
A
50
mV
A
mV
C
mV
A
µA
C
5.5
V
D
1.5
V
D
0.4
V
D
100
kHz
D
70
20
3
15.2 Input voltage SCL/SDA LOW
Output voltage SDA
(open collector)
V
1, 2
15.1 Input voltage SCL/SDA HIGH
15.3
4.45
±20
ICAOmax
ICBOmax
ICCOmax
Maximum output
current
4.25
ISDA = 2 mA,
SDA = LOW
15.4 SCL clock frequency
0.1
15.5 Rise time (SCL, SDA)
tr
1
µs
D
15.6 Fall time (SCL; SDA)
tf
300
µs
D
µs
D
15.7
Time before new
transmission can start
tbuf
4.7
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency
of the phase detector divided by 4 according to the fractional-N technique (regularly: 16 kHz).
18
U2731B
4671C–DAB–06/04
U2731B
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
15.8 SCL HIGH period
thigh
4
µs
D
15.9 SCL LOW period
tlow
4.7
µs
D
15.10 Hold time START
thdsta
4
µs
D
15.11 Setup time START
tsusta
4.7
µs
D
15.12 Setup time STOP
tsustp
4.7
µs
D
15.13 Hold time DATA
thddat
0
µs
D
15.14 Setup time DATA
tsudat
250
ns
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency
of the phase detector divided by 4 according to the fractional-N technique (regularly: 16 kHz).
Figure 6. Application Circuit
8.5V
3.3n
22k
33k
51k
100p
microcontroller
BC846B
Miro crystal
16.384 MHz
CXAT-T1
2.2k
33k
4.7k
4.7k
27p
10n
68p
4.7k
3.3 µ
2.2p
8.5V
1.8k
8.5V
100p
47nH
10n
33p
43
AD-converter
VAGCIF
BB545
1.2n
18p
Address
select voltage 44
2.2k
Antialiasing
filter
3.3n
100p
10n
42
41
40
39
38
37
4.7p 2.2p 2.2p 4.7p
36
35
34
33
32
10n 10n
31
30
29
28
27
26
10n
25
24
23
SAW
filter
U2731B
S+M
X6922M
Microcontroller
680nH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SCL
SDA
76k 76k
76k
1n
1n
1n
1n
WAGC
SLI
100n
8.5V
100n
Switches
100n
9k
U2730B-N
8.5V
9k
10n 10n
1n
220n
3.3µ
9k
RFA
RFB
VAGCRF
Preselector
19
4671C–DAB–06/04
Application Circuits of the Reference Oscillator
Figure 7. Oscillator Operation
OSCI
68p
33p
Reference
divider
OSCO
18p
Figure 8. Oscillator Overdriven
Reference
signal
50
OSCI
1n
Reference
divider
OSCO
20
U2731B
4671C–DAB–06/04
U2731B
Figure 9. Measurement Circuit for Electrical Characteristics
8.5V
100p
51k
33k
3.3n
22k
Microcontroller
IFAD
1k
3.3n
4.7k
2.2k
BC846B
2.2k
VAGCIF
4.7k
BB545
4.7k
3.3 µ
47n
33k
1.2n
27p
2.2p
8.5V
1.8k
8.5V
10n
47nH
REF IN
10n
Address
select voltage
44
43
42
100p
10n
41
40
39
38
37
10n
4.7p 2.2p 2.2p 4.7p
36
35
34
33
10n
10n
IFIN
100p
10n
32
31
30
29
28
27
26
25
24
23
13
14
15
16
17
18
19
20
21
22
50
Microcontroller
U2731B
SCL
SDA
1
2
3
4
5
76k 76k
6
7
76k
8
9
10
11
12
1n
WAGC
1n
SLI
100n
8.5V
3.3 µ
100n
1n
Switches
100n
9k
U2730B-N
9k
1n
50
10n
10n
1n
220n
50
9k
100
51
8.5V
RFA
RFB
VAGCRF
O1SA
Preselector
21
4671C–DAB–06/04
Figure 10. RFAGC Voltage-generation Block Circuit
V REF
VAGC,INT
IDA
TBI
D/A
SAW1 SAW2
BUF_IN
AGC_BP
AGC_RECT
SLI WAGC
AGC_TP
V REF
AGCRF
voltage
R
CPRF
AGC_COMP
IDA
TAI
AGC_THRESH
CHARGE
PUMP
CAGC
D/A
Figure 11. IFAGC Voltage-generation Block Circuit
IFAMP
IFMX
IFAD
Antialiasing
filter
A/D
converter
VAGC
R1
IFAGC1
R2
IFAGC2
CHARGE
PUMP
VREF
CPRF
AGCIF
R
AGC_THRESH
IDA
SLI
WAGC
TCI
D/A
22
U2731B
4671C–DAB–06/04
U2731B
Figure 12. VCO Circuit
V Bias
VS
C1VC
V Tune
B2VC
B1VC
C2VC
Phase-noise
Performance
(Example: SFeff = 16899, SFref,eff = 1120, fref = 17.92 MHz, IPD = 200 mA,
spectrum analysis: HP7000)
Figure 13. Phase-noise Over Frequency
10.00 dB/DIV
10.00 dB/DIV
< -70 dBc/Hz
CENTER 270.384 MHz
RB 100 Hz
VB 100 Hz
SPAN 10.00 kHz
ST 3.050 sec
CENTER 270.384 MHz
RB 1.00 kHz VB 1.00 kHz
SPAN 200.0 kHz
ST 600.0 msec
23
4671C–DAB–06/04
Ordering Information
Extended Type Number
Package
Remarks
U2731B–NFN
SSO44
Tube
U2731B–NFNG1
SSO44
Taped and reeled
Package Information
9.15
8.65
Package SSO44
Dimensions in mm
18.05
17.80
7.50
7.30
2.35
0.3
0.25
0.10
0.8
16.8
44
0.25
10.50
10.20
23
technical drawings
according to DIN
specifications
1
24
22
U2731B
4671C–DAB–06/04
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Atmel Operations
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
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