ATMEL AT25320B-SSHL-T

Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet Describes Mode 0 Operation
• Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
– 1.8 (VCC = 1.8V to 5.5V)
20MHz Clock Rate (5V)
32-byte Page Mode
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
Self-timed Write Cycle (5ms max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
Description
The Atmel® AT25320B/640B provides 32768-/65536-bits of serial electrically-erasable
programmable read-only memory (EEPROM) organized as 4096/8192 words of 8-bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The AT25320B/640B is
available in space-saving 8-lead JEDEC SOIC, 8-lead UDFN, 8-lead XDFN, 8-lead
TSSOP, and 8-ball VFBGA packages.
SPI Serial
EEPROMs
32K (4096 x 8)
64K (8192 x 8)
Atmel
AT25320B
AT25640B
The AT25320B/640B is enabled through the Chip Select pin (CS) and accessed via a
three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no separate erase cycle is required before write.
Table 0-1.
Pin Configuration
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
8-lead SOIC
CS
SO
WP
GND
1
8
2
7
3
6
4
5
8-lead TSSOP
VCC
HOLD
SCK
SI
CS
1
8
SO
WP
GND
2
7
3
6
4
5
8-lead XDFN
8-lead UDFN
VCC
HOLD
SCK
SI
VCC
HOLD
SCK
SI
8
1 CS
7
2 SO
6
3 WP
5
4 GND
VCC
HOLD
SCK
SI
8
1 CS
7
2 SO
6
3 WP
5
4 GND
Bottom View
Bottom View
8-ball VFBGA
VCC
HOLD
SCK
SI
8
1
7
2
6
3
5
4
CS
SO
WP
GND
8535F–SEEPR–6/10
Bottom View
Block write protection is enabled by programming the status register with one of four blocks of write protection.
Separate program enable and program disable instructions are provided for additional data protection. Hardware
data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The
HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
1.
Absolute Maximum Ratings*
Operating Temperature ............................–55C to +125C
Storage Temperature ...............................–65C to +150C
Voltage on Any Pin
with Respect to Ground..............................–1.0V to +7.0V
Maximum Operating Voltage.................................... 6.25V
DC Output Current ................................................. 5.0 mA
Figure 1-1.
2
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the
device at these or any other conditions
beyond those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Block Diagram
Atmel AT25320B/640B
8535F–SEEPR–6/10
Atmel AT25320B/640B
Table 1-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0MHz, VCC = +5.0V (unless otherwise noted)
Symbol
Test Conditions
Max
Units
Conditions
COUT
Output Capacitance (SO)
8
pF
VOUT = 0V
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN = 0V
Note:
1. This parameter is characterized and is not 100% tested
Table 1-2.
DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Max
Units
1.8
5.5
V
Supply Voltage
2.5
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC1
Supply Current
VCC = 5.0V at 20MHz, SO = Open, Read
7.5
10.0
mA
ICC2
Supply Current
VCC = 5.0V at 20MHz, SO = Open, Read,
Write
4.0
10.0
mA
ICC3
Supply Current
VCC = 5.0V at 5MHz, SO = Open,
Read, Write
4.0
6.0
mA
ISB1
Standby Current
VCC = 1.8V, CS = VCC
< 0.1
6.0(2)
µA
(2)
µA
ISB2
Standby Current
Test Condition
Min
VCC = 2.5V, CS = VCC
Typ
0.3
10.0
(2)
ISB3
Standby Current
VCC = 5.0V, CS = VCC
IIL
Input Leakage
VIN = 0V to VCC
–3.0
3.0
µA
Output Leakage
VIN = 0V to VCC, TAC = 0°C to 70°C
–3.0
3.0
µA
IOL
2.0
7.0
µA
(1)
Input Low-voltage
–0.6
VCC x 0.3
V
VIH
(1)
Input High-voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low-voltage
0.4
V
VOH1
Output High-voltage
VOL2
Output Low-voltage
VOH2
Output High-voltage
VIL
Notes:
3.6V  VCC  5.5V
1.8V  VCC  3.6V
IOL = 3.0mA
IOH = 1.6mA
VCC - 0.8
IOL = 0.15mA
IOH = 100µA
V
0.2
VCC - 0.2
V
V
1. VIL min and VIH max are reference only and are not tested
2. Worst case measured at 85°C
3
8535F–SEEPR–6/10
Table 1-3.
AC Characteristics
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
fSCK
SCK Clock Frequency
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
20
10
5
MHz
tRI
Input Rise Time
4.5–5.5
2.5–5.5
1.8–5.5
2
2
2
µs
tFI
Input Fall Time
4.5–5.5
2.5–5.5
1.8–5.5
2
2
2
µs
tWH
SCK High Time
4.5–5.5
2.5–5.5
1.8–5.5
20
40
80
ns
tWL
SCK Low Time
4.5–5.5
2.5–5.5
1.8–5.5
20
40
80
ns
tCS
CS High Time
4.5–5.5
2.5–5.5
1.8–5.5
25
50
100
ns
tCSS
CS Setup Time
4.5–5.5
2.5–5.5
1.8–5.5
25
50
100
ns
tCSH
CS Hold Time
4.5–5.5
2.5–5.5
1.8–5.5
25
50
100
ns
tSU
Data In Setup Time
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
ns
tH
Data In Hold Time
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
ns
tHD
HOLD Setup Time
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
tCD
HOLD Hold Time
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
tV
Output Valid
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
tHO
Output Hold Time
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
4
ns
20
40
80
ns
ns
Atmel AT25320B/640B
8535F–SEEPR–6/10
Atmel AT25320B/640B
Table 1-3.
AC Characteristics (Continued)
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
tLZ
HOLD to Output Low Z
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
25
50
100
ns
tHZ
HOLD to Output High Z
4.5–5.5
2.5–5.5
1.8–5.5
40
80
200
ns
tDIS
Output Disable Time
4.5–5.5
2.5–5.5
1.8–5.5
40
80
200
ns
tWC
Write Cycle Time
4.5–5.5
2.5–5.5
1.8–5.5
5
5
5
ms
Endurance(1)
3.3V, 25°C, Page Mode
Note:
1. This parameter is characterized and is not 100% tested
2.
Serial Interface Description
1M
Write Cycles
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the Atmel® AT25320B/640B always operates as a
slave.
TRANSMITTER/RECEIVER: The AT25320B/640B has separate pins designated for data transmission (SO) and
reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25320B/640B, and the
serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will
reinitialize the serial communication.
CHIP SELECT: The AT25320B/640B is selected when the CS pin is low. When the device is not selected, data will
not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25320B/640B. When the device is
selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is
low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle
during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low
while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated,
WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when
the WPEN bit in the status register is “0”. This will allow the user to install the AT25320B/640B in a system with the
5
8535F–SEEPR–6/10
WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the
WPEN bit is set to “1”.
Figure 2-1.
SPI Serial Interface
AT25320B/640B
6
Atmel AT25320B/640B
8535F–SEEPR–6/10
Atmel AT25320B/640B
3.
Functional Description
The Atmel® AT25320B/640B is designed to interface directly with the synchronous serial peripheral interface (SPI)
of the 6805 and 68HC11 series of microcontrollers.
The AT25320B/640B utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 3-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-tolow CS transition.
Table 3-1.
Instruction Set for the Atmel AT25320B/640B
Instruction Name
Instruction Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
WRITE
0000 X010
Write Data to Memory Array
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly,
the Block Write Protection Bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 3-2.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
Table 3-3.
Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the write cycle
is in progress.
Bit 1 (WEN)
Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the
device is write enabled.
Bit 2 (BP0)
See Table 3-4 on page 8.
Bit 3 (BP1)
See Table 3-4 on page 8.
Bits 4–6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 3-5 on page 8.
Bits 0–7 are “1”s during an internal write cycle.
7
8535F–SEEPR–6/10
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The Atmel® AT25320B/640B is divided into four array segments. One-quarter, one-half, or all of the memory
segments can be protected. Any of the data within any selected segment will therefore be read only. The block
write protection levels and corresponding status register control bits are shown in Table 3-4 on page 8.
The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, tWC, RDSR).
Table 3-4.
Block Write Protect Bits
Status Register Bits
Level
Array Addresses Protected
BP1
BP0
Atmel AT25320B
Atmel AT25640B
0
0
0
None
None
1(1/4)
0
1
0C000FFF
18001FFF
2(1/2)
1
0
08000FFF
10001FFF
3(All)
1
1
00000FFF
00001FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit
is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the device
is hardware write protected, writes to the status register, including the block protect bits and the WPEN bit, and the
block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory that
are not block-protected.
Note:
When the WPEN bit is hardware write protected, it cannot be changed back to “0” as long as the WP pin is held low.
Table 3-5.
WPEN Operation
WPEN
WP
WEN
Protected
Blocks
Unprotected
Blocks
Status
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writeable
Writeable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writeable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writeable
Writeable
READ SEQUENCE (READ): Reading the AT25320B/640B via the Serial Output (SO) pin requires the following
sequence. After the CS line is pulled low to select a device, the read op-code is transmitted via the SI line followed
by the byte address to be read (A15–A0, see Table 3-6). Upon completion, any data on the SI line will be ignored.
The data (D7–D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The read sequence can be continued since the byte address is
automatically incremented and data will continue to be shifted out. When the highest address is reached, the
address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read
cycle.
8
Atmel AT25320B/640B
8535F–SEEPR–6/10
Atmel AT25320B/640B
WRITE SEQUENCE (WRITE): In order to program the Atmel® AT25320B/640B, two separate instructions must be
executed. First, the device must be write enabled via the WREN instruction. Then a write (WRITE) instruction
may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected
address field location selected by the block write protection level. During an internal write cycle, all commands will
be ignored except the RDSR instruction.
A write instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE
op-code is transmitted via the SI line followed by the byte address (A15–A0) and the data (D7–D0) to be programmed (see Table 3-6). Programming will start after the CS pin is brought high. The low-to-high transition of the
CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a read status register
(RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the
RDSR instruction is enabled during the write programming cycle.
The AT25320B/640B is capable of a 32-byte page write operation. After each byte of data is received, the five loworder address bits are internally incremented by one; the high-order bits of the address will remain constant. If
more than 32-bytes of data are transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25320B/640B is automatically returned to the write disable state at the completion of a write
cycle.
Note:
If the device is not write-enabled (WREN), the device will ignore the write instruction and will return to the standby
state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication.
Table 3-6.
Address Key
Address
Atmel AT25320B
Atmel AT25640B
AN
A11–A0
A12–A0
Don’t Care Bits
A15–A12
A15–A13
9
8535F–SEEPR–6/10
4.
Timing Diagrams
Figure 4-1.
Synchronous Data Timing (for Mode 0)
t CS
VIH
CS
VIL
t CSH
tCSS
VIH
t WH
SCK
t WL
VIL
tH
t SU
VIH
SI
VALID IN
VIL
tV
VOH
SO
t HO
t DIS
HI-Z
HI-Z
VOL
Figure 4-2.
WREN Timing
CS
SCK
SI
WREN OP-CODE
HI-Z
SO
Figure 4-3.
WRDI Timing
CS
SCK
SI
SO
10
WRDI OP-CODE
HI-Z
Atmel AT25320B/640B
8535F–SEEPR–6/10
Atmel AT25320B/640B
Figure 4-4.
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
8
9
10
11
12
13
14
15
MSB
Figure 4-5.
WRSR Timing
CS
0
1
2
3
4
5
6
7
SCK
DATA IN
SI
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
Figure 4-6.
7
INSTRUCTION
READ Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 20 21 22 23 24 25 26 27 28 29 30
SCK
BYTE ADDRESS
SI
INSTRUCTION
15 14 13 ... 3
2
1
0
DATA OUT
SO
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
MSB
11
8535F–SEEPR–6/10
Figure 4-7.
WRITE Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
BYTE ADDRESS
SI
SO
Figure 4-8.
15 14 13 ... 3
INSTRUCTION
2
DATA IN
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
HOLD Timing
CS
t CD
t CD
SCK
t HD
HOLD
t HD
t HZ
SO
tLZ
12
Atmel AT25320B/640B
8535F–SEEPR–6/10
Atmel AT25320B/640B
5.
Ordering Code Detail
AT 2 5 32 0 B - S S H L - B
Atmel Designator
Shipping Carrier Option
B or blank = Bulk (tubes)
T
= Tape and reel
Product Family
Operating Voltage
L
=
1.8V to 5.5V
Device Density
320 = 32-kilobit
640 = 64-kilobit
Device Revision
Packaged Device Grade or
Wafer/Die Thickness
H
=
U
=
11
=
Green, NiPdAu lead finish
Industrial Temperature range
(-40°C to +85°C)
Green, matte Sn lead finish
Industrial Temperature range
(-40°C to +85°C)
11 mil wafer thickness
Package Option
SS =
X
=
MA =
ME =
C
=
WWU =
WDT =
JEDEC SOIC
TSSOP
UDFN
XDFN
VFBGA
Wafer unsawn
Die in Tape and Reel
13
8535F–SEEPR–6/10
6.
Part Markings
6.1
Atmel AT25320B
AT25320B-SSHL
Top Mark
Seal Year
| Seal Week
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
|---|---|---|---|---|---|---|---|
5
B
B
L
@
|---|---|---|---|---|---|---|---|
* LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
@ = Country of
Y = SEAL YEAR
6: 2006
0:
7: 2007
1:
8: 2008
2:
9: 2009
3:
Ass’y
2010
2011
2012
2013
WW
02
04
::
::
50
52
=
=
=
:
:
=
=
SEAL
Week
Week
::::
::::
Week
Week
WEEK
2
4
:
::
50
52
WW
02
04
::
::
50
52
=
=
=
:
:
=
=
SEAL
Week
Week
::::
::::
Week
Week
WEEK
2
4
:
::
50
52
AT25320B-XHL
Top Mark
PIN 1 INDICATOR (DOT)
|
* |---|---|---|---|---|---|
A
T
H
Y
W
W
|---|---|---|---|---|---|
5
B
B
L
@
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
@ = Country of
Y = SEAL YEAR
8: 2008
2:
9: 2009
3:
0: 2010
4:
1: 2011
5:
Ass’y
2012
2013
2014
2015
AT25320B-MAHL
Top Mark
|---|---|---|
5
B
B
|---|---|---|
H
L
@
|---|---|---|
Y
X
X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
14
Y = YEAR OF ASSEMBLY
@ = Country of Ass’y
XX= ATMEL LOT NUMBER TO COORESPOND
WITH TRACE CODE LOG BOOK
(e.g. XX = AA, AB, AC,... AX, AY AZ)
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
1: 2011
8: 2008
2: 2012
9: 2009
3: 2013
Atmel AT25320B/640B
8535F–SEEPR–6/10
Atmel AT25320B/640B
AT25320B-MEHL
Top Mark
Y = YEAR OF ASSEMBLY
@ = Country of Ass’y
XX= ATMEL LOT NUMBER TO COORESPOND
WITH TRACE CODE LOG BOOK
(e.g. XX = AA, AB, AC,... AX, AY AZ)
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
1: 2011
8: 2008
2: 2012
9: 2009
3: 2013
|---|---|---|
5
B
B
|---|---|---|
H
L
@
|---|---|---|
Y
X
X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
AT25320B-CUL
Top Mark
|---|---|---|---|
5
B
B
U
|---|---|---|---|
B
Y
M
X
X
|---|---|---|---|---|
* <-- PIN 1 INDICATOR
B =
Y =
M =
XX=
Country of Origin
One Digit Year Code
One Digit Month Code
TRACE CODE (ATMEL LOT NUMBER TO
COORESPOND WITH TRACE CODE LOG BOOK)
(e.g. XX = AA, AB, AC,... YZ, ZZ)
Y = ONE DIGIT YEAR CODE
4: 2004
7: 2007
5: 2005
8: 2008
6: 2006
9: 2009
M = SEAL MONTH
(USE ALPHA DESIGNATOR A-L)
A = JANUARY
B = FEBRUARY
" " """"""""
J = OCTOBER
K = NOVEMBER
L = DECEMBER
15
8535F–SEEPR–6/10
6.2
Atmel AT25640B
AT25640B-SSHL
Top Mark
Seal Year
| Seal Week
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
|---|---|---|---|---|---|---|---|
5
C
B
L
@
|---|---|---|---|---|---|---|---|
* LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
@ = Country of
Y = SEAL YEAR
6: 2006
0:
7: 2007
1:
8: 2008
2:
9: 2009
3:
Ass’y
2010
2011
2012
2013
WW
02
04
::
::
50
52
=
=
=
:
:
=
=
SEAL
Week
Week
::::
::::
Week
Week
WEEK
2
4
:
::
50
52
WW
02
04
::
::
50
52
=
=
=
:
:
=
=
SEAL
Week
Week
::::
::::
Week
Week
WEEK
2
4
:
::
50
52
AT25640B-XHL
Top Mark
PIN 1 INDICATOR (DOT)
|
* |---|---|---|---|---|---|
A
T
H
Y
W
W
|---|---|---|---|---|---|
5
C
B
L
@
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
@ = Country of
Y = SEAL YEAR
8: 2008
2:
9: 2009
3:
0: 2010
4:
1: 2011
5:
Ass’y
2012
2013
2014
2015
AT25640B-MAHL
Top Mark
|---|---|---|
5
C
B
|---|---|---|
H
L
@
|---|---|---|
Y
X
X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
16
Y = YEAR OF ASSEMBLY
@ = Country of Ass’y
XX= ATMEL LOT NUMBER TO COORESPOND
WITH TRACE CODE LOG BOOK
(e.g. XX = AA, AB, AC,... AX, AY AZ)
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
1: 2011
8: 2008
2: 2012
9: 2009
3: 2013
Atmel AT25320B/640B
8535F–SEEPR–6/10
Atmel AT25320B/640B
AT25640B-MEHL
Top Mark
Y = YEAR OF ASSEMBLY
XX= ATMEL LOT NUMBER TO COORESPOND
WITH TRACE CODE LOG BOOK
(e.g. XX = AA, AB, AC,... AX, AY AZ)
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
1: 2011
8: 2008
2: 2012
9: 2009
3: 2013
|---|---|---|
5
C
B
|---|---|---|
Y
X
X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
AT25640B-CUL
Top Mark
|---|---|---|---|
5
C
B
U
|---|---|---|---|
B
Y
M
X
X
|---|---|---|---|---|
* <-- PIN 1 INDICATOR
B =
Y =
M =
XX=
Country of Origin
One Digit Year Code
One Digit Month Code
TRACE CODE (ATMEL LOT NUMBER TO
COORESPOND WITH TRACE CODE LOG BOOK)
(e.g. XX = AA, AB, AC,... YZ, ZZ)
Y = ONE DIGIT YEAR CODE
4: 2004
7: 2007
5: 2005
8: 2008
6: 2006
9: 2009
M = SEAL MONTH
(USE ALPHA DESIGNATOR A-L)
A = JANUARY
B = FEBRUARY
" " """"""""
J = OCTOBER
K = NOVEMBER
L = DECEMBER
17
8535F–SEEPR–6/10
7.
Ordering Codes
Atmel AT25320B Ordering Information
Ordering Code
Voltage
Package
Operation Range
AT25320B-SSHL-B (NiPdAu Lead Finish)
AT25320B-SSHL-T(2) (NiPdAu Lead Finish)
AT25320B-XHL-B(1) (NiPdAu Lead Finish)
AT25320B-XHL-T(2) (NiPdAu Lead Finish)
AT25320B-MAHL-T(2) (NiPdAu Lead Finish)
AT25320B-MEHL-T(2) (NiPdAu Lead Finish)
AT25320B-CUL-T(2) (SnAgCu Ball Finish)
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
8S1
8S1
8A2
8A2
8MA2
8ME1
8U2-1
Lead-free/Halogen-free/
Industrial Temperature
(40 to 85C)
AT25320B-WWU11L(3)
1.8V to 5.5V
Die Sale
Industrial Temperature
(40 to 85C)
(1)
Note:
1. Bulk delivery in tubes (SOIC and TSSOP 100/tube)
2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN, XDFN and VFBGA 5k/reel)
3. Contact Atmel Sales for Wafer sales
Package Type
18
8S1
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8MA2
8-lead, 2.00mm x 3.00mm Body, 0.50mm Pitch, Ultra Thin, Dual No Lead Package (UDFN)
8ME1
8-lead (1.8mm x 2.2mm Body) Ultra Leadframe Land Grid Array (XDFN)
8U2-1
8-lead, 8.35mm x 3.73mm Body, 0.75mm Pitch, VFBGA Package (VFBGA)
Atmel AT25320B/640B
8535F–SEEPR–6/10
Atmel AT25320B/640B
Atmel AT25640B Ordering Information
Ordering Code
Voltage
Package
Operation Range
AT25640B-SSHL-B (NiPdAu Lead Finish)
AT25640B-SSHL-T(2) (NiPdAu Lead Finish)
AT25640B-XHL-B(1) (NiPdAu Lead Finish)
AT25640B-XHL-T(2) (NiPdAu Lead Finish)
AT25640B-MAHL-T(2) (NiPdAu Lead Finish)
AT25640B-MEHL-T(2) (NiPdAu Lead Finish)
AT25640B-CUL-T(2) (SnAgCu Ball Finish)
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
8S1
8S1
8A2
8A2
8MA2
8ME1
8U2-1
Lead-free/Halogen-free/
Industrial Temperature
(40 to 85C)
AT25640B-WWU11L(3)
1.8V to 5.5V
Die Sale
Industrial Temperature
(40 to 85C)
(1)
Note:
1. Bulk delivery in tubes (SOIC and TSSOP 100/tube)
2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN, XDFN and VFBGA 5k/reel)
3. Contact Atmel Sales for Wafer sales
Package Type
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8MA2
8-lead, 2.00mm x 3.00mm Body, 0.50mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (UDFN), (MLP
2x3mm)
8ME1
8-lead (1.8mm x 2.2mm Body) Ultra Leadframe Land Grid Array (XDFN)
8U2-1
8-lead, 8.35mm x 3.73mm Body, 0.75mm Pitch, VFBGA Package (VFBGA)
19
8535F–SEEPR–6/10
8.
Packaging Information
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
A
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
D
SIDE VIEW
SYMBOL
MIN
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
MAX
NOM
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
5/19/10
TITLE
Package Drawing Contact:
8S1, 8-lead (0.150” Wide Body), Plastic Gull
[email protected] Wing Small Outline (JEDEC SOIC)
20
GPC
SWB
DRAWING NO.
8S1
REV.
F
Atmel AT25320B/640B
8535F–SEEPR–6/10
Atmel AT25320B/640B
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
D
A
b
e
2.90
E
A2
D
NOM
MAX
NOTE
3.00
3.10
2, 5
3, 5
6.40 BSC
E1
4.30
4.40
4.50
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
L
Side View
Notes:
MIN
L1
4
0.65 BSC
0.45
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall
not exceed 0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed
0.25 mm (0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess
of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
Minimum space between protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/19/10
TITLE
Package Drawing Contact:
8A2, 8-lead 4.4mm Body, Plastic Thin
[email protected] Shrink Small Outline Package (TSSOP)
GPC
TNR
DRAWING NO.
8A2
REV.
E
21
8535F–SEEPR–6/10
8MA2 - UDFN
E
8
1
Pin 1 ID
2
7
3
6
4
5
D
C
A2
A
A1
E2
b (8x)
8
1
Pin#1 ID
(R0.10)
7
0.35
COMMON DIMENSIONS
(Unit of Measure = mm)
2
D2
6
3
5
4
e (6x)
K
L (8x)
Notes: 1. This drawing is for general information only. Refer to
JEDEC Drawing MO-229 for proper dimensions,
tolerances, datums, etc.
2. The terminal #1 ID is a laser-marked feature.
3. Dimensions b applies to metalized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should not
be measured in that radius area.
SYMBOL
MIN
NOM
MAX
D
2.00 BSC
E
3.00 BSC
D2
1.40
1.50
1.60
E2
1.20
1.30
1.40
A
0.50
0.55
0.60
A1
0.00
0.02
0.05
A2
–
–
0.55
C
L
0.152 REF
0.30
e
b
K
NOTE
0.40
0.35
0.50 BSC
0.18
0.25
0.30
–
–
0.20
3
4/15/08
TITLE
Package Drawing Contact:
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
packagedrawin[email protected] Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
22
GPC
YNZ
DRAWING NO.
REV.
8MA2
A
Atmel AT25320B/640B
8535F–SEEPR–6/10
Atmel AT25320B/640B
8ME1 - XDFN
e1
D
8
7
6
b
5
L
E
PIN #1 ID
0.10
PIN #1 ID
0.15
1
2
3
4
A1
b
e
A
Top View
Side View
Bottom View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
A
–
–
0.40
A1
0.00
–
0.05
D
1.70
1.80
1.90
E
2.10
2.20
2.30
b
0.15
0.20
0.25
e
0.40 TYP
e1
L
NOTE
1.20 REF
0.26
0.30
0.35
8/3/09
TITLE
Package Drawing Contact:
[email protected]
8ME1, 8-lead (1.80 x 2.20 mm Body)
Extra Thin DFN (XDFN)
GPC
DTP
DRAWING NO.
REV.
8ME1
A
23
8535F–SEEPR–6/10
8U2-1 - VFBGA
// 0.10 C
0.10 (4X)
D
A1 Ball Pad Corner
0.08 C
C
A
Øb
Ø0.15 M C A B
Ø0.08 M C
e
A1
B
A2
A
Top View
Side View
A1 BALL PAD CORNER
2
1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
B
e
C
D
(e1)
d
SYMBOL
MIN
NOM
MAX
A
0.81
0.91
1.00
A1
0.15
0.20
0.25
A2
0.40
0.45
0.50
(d1)
b
0.25
0.30
0.35
Bottom View
D
2.35 BSC
8 SOLDER BALLS
E
3.73 BSC
e
0.75 BSC
e1
0.74 BSC
d
0.75 BSC
d1
0.80 REF
Notes: 1. This drawing is for general information.
2. Dimension 'b' is measured at the maximum solder
ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
NOTE
2/25/08
TITLE
8U2-1, 8 ball, 2.35 x 3.73 mm Body,
Package Drawing Contact:
[email protected] 0.75 mm pitch, VFBGA Package (dBGA2)
24
GPC
GWW
DRAWING NO.
REV.
8U2-1
C
Atmel AT25320B/640B
8535F–SEEPR–6/10
Atmel AT25320B/640B
9.
Revision History
Doc. Rev.
Date
Comments
8535F
6/2010
Update 8A2 and 8S1 package drawings
Remove Preliminary
8535E
4/2010
Update Ordering Code Detail, Ordering Information, template
8535D
8/2009
Change Catalog Numbering
Add new Part Marking Information
8535C
5/2009
Add Part Marking information; changed to Preliminary status.
8535B
7/2008
Modify ‘Endurance’ parameter on page 6.
8535A
4/2008
Initial document release.
25
8535F–SEEPR–6/10
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8535F–SEEPR–6/10