AN2095 Algorithm - Logarithmic Signal Companding - Not Just a Good Idea - It Is -Law Author: David Van Ess Associated Project: Yes Associated Part Family: CY8C27x43, CY28x43, CY28x45, CY28x52, CY8C29x66 ® Software Version: PSoC Designer™ 5.4 Related Application Notes: None AN2095 explains how logarithmic signal compression works. Routines are developed and an application is shown to implement a -Law compressor that converts an analog voice band signal and produces a digitized 8-bit compressed value. An expanding DAC is also developed that restores the compressed digital value back to an analog value. The Signal Introduction Virtually all telephony applications are becoming digital. Be it wireless or standard line, digitization of speech for transmission has advantages over traditional analog techniques. -Law (pronounced mu law) is a technique of data compression and expansion that allows for a greater dynamic range given the same signal bandwidth. This Application Note explains the logarithmic nature of the human ear’s response. Equations are developed to calculate the signal-to-noise ratio for variable input levels. A PSoC® implementation of a -Law compressor and expander (compandor) is developed. A project is included that accomplishes the following: The Phone Company The Ear The original analog speech must be accurately received. Accurate is such a fuzzy word. A better description is that an acceptable facsimile of the signal be transmitted to the ear. The definition of “acceptable” is as follows. Signal Transmits this data via a RS232 transmitter. For telephony applications this is voice or speech. Human speech has a range approximately 100 Hz to 9 kHz. It has roughly 40 dB of dynamic range, however normal conversation rarely exceeds 20 dB. (Heavy equipment operators, irate customers and pointy haired managers excluded.) Receives this data via a RS232 receiver. The Phone Company Expands this data and coverts it back to an analog value. The phone company limits the signal bandwidth to a range of 300 Hz to 3.5 kHz. This is not a problem for voice communication applications. A voice signal limited to this range is easily understood. Digitizes and compresses incoming data to an 8-bit value. ‘C’ callable companding routines are developed and presented. The Really Big Picture Figure 1 shows the block diagram for a typical telephony application: Figure 1. “The Really Big Picture” Block Diagram The Human Ear THE PHONE COMPANY Signal Ear It doesn’t get more basic than this. There are three different components to this system: www.cypress.com Digital systems require a sample rate of 8-kilo samples per second (ksps) with 8 bits of resolution and only 8 bits of resolution. No free “evening and weekend” bits or “anytime” bits. Just 8 bits. That’s all, no more. An upper limit of 3.5 kHz puts the signal bandwidth comfortably below the 8 kHz/2 Nyquist sampling limit. The human ear is an engineering marvel. It has a logarithmic response. That is, it has the ability to become more or less sensitive to sounds. The ear can hear sound pressure levels (SPL) as low as 0 dBSPL (a whisper) up to 120 dBSPL (a painfully loud rock concert). However, at any particular sound level, the dynamic range of the ear is only 40 dB. This means you can hear someone whisper and also enjoy a rock concert with same ears, just not at the same time. If you take your niece to a Britney Spears Document No. 001-38006 Rev. *D 1 Algorithm - Logarithmic Signal Companding - Not Just a Good Idea - It Is µ-Law concert she will not be able to hear you repeatedly mutter, “This is lame!” If the noise is kept 40 db below the signal, the ear does not detect it. Quantization Noise, Public Enemy #1 In a digitalized system the noise resulting from analog to digital conversion is one of the largest, if not the largest, noise contributor. Figure 2 is a visual example of an analog to digital (ADC) conversion. Figure 2. Example of an Analog Digital Conversion Signal 1 a (a sin(t )) 2 dt 0 2 Equation 3 The ratio of these two values is defined as the Signal-toNoise Ratio (SNR). It is normally expressed in dB as shown in Equation (4): a 12 Signal SNRdB 20 log 20 log Noise 2 Equation 4 Combining equations (1) and (4) results in simplified Equation (5): 3 6.02n 1.76 20 log( a) Equation 5 SNRdB 20 log a 2 n 2 Figure 3 is a plot of the SNR for an 8-bit ADC: Figure 3. SNR vs. Input for 8-Bit ADC SNR for 8 bit ADC 60 For the following mathematical models, use the following definitions: The ADC range is normalized to +/- 1. n An “n” bit ADC has 2 quantization levels. Equation (1) defines the ADC resolution. ADCRange 2 # Quantizati onLevels 2 n Equation 1 The quantization error is the difference between the actual signal and the quantized value. For a dynamic signal, this error averages to zero and is limited to +/- ½. It is evenly distributed between the limits of +/-½. Figure 2 defines the noise as the RMS value of this error. Noise RMS 2 2 1 2 1 d 3 12 2 3 40 30 20 10 0 The input signal is a sinusoid with amplitude “a” (where 0 ≤ a ≤ 1). 50 SNR(dB) The ADC output has finite resolution. The difference between these two signals is the quantization noise. Intuitively, an ADC with finer resolution levels results in less quantization noise. Equation 2 -10 -20 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 Input(dB) The SNR is as high as 50 dB for a full-scale input but falls to 40 dB for a -10 dB input. For a -20 dB input, the SNR is down to 30 dB. This SNR calculation only accounts for quantization noise. Other noise sources in the system reduce the actual SNR value even further. Equation (6) shows the dynamic range to be the ratio of the range to the resolution: ADCRange DRdB 20 log 6.02 n Equation 6 Non-Linear Quantization 2 The quantization noise is directly proportional to the ADC resolution. The signal is a sinusoid with amplitude of “a.” Equation (3) defines its RMS value: Figure 3 shows the SNR as a function of the relative amplitude of the input. It is 50 dB for a full-scale input but falls rapidly. More bits of resolution would allow a wider range of input signals but the phone company makes it pretty clear that this is not going to happen. An alternative is to make a function of input signal amplitude. If is made larger for large input signals and smaller for small signals, some of the excess SNR at the www.cypress.com Document No. 001-38006 Rev. *D 2 Algorithm - Logarithmic Signal Companding - Not Just a Good Idea - It Is µ-Law top of the input range can be used to boost the SNR for low-level inputs. This is called non-linear quantization. Most non-linear quantization techniques are based on some logarithmic transfer function. -Law Compression y 2 2n Equation 10 Substituting y for dy in Equation (9) results in Equation (11): x ( x) dx (1 x) North American and Japanese telephony applications use -Law compression. Equation (7) is the compression function. Where: Noise( x) x ( x) 12 is the compression factor. y sign( x) ln(1 | x |) ln(1 ) Equation 11 The resolution on the x-axis is shown to be a function of x. Equation (12) shows that the noise is also a function of x: The input in normalized (-1≤ x ≤ 1). y is the compressed output. ln(1 ) 2 n 2 (1 x) ln(1 ) 2 n 2 12 Equation 12 The total noise is the RMS of all the quantization noise of the input signal. Equation (13) defines the noise for a sinusoidal input with an amplitude of “a.” Equation 7 can be any positive value. The larger becomes, the greater the compression. For North American and Japanese applications, is set to 255. Figure 4 is the plot of Equation (7) with set to 255 and x limited to its positive range: Figure 4. -Law Plot = 255 1 NoiseRMS Noise(a sin( x)) 2 Equation 13 dx 0 Combining equations Equation (14): (12) and (13) ln(1 ) (1 a sin( x)) 1 dx n 0 2 12 2 results in 2 1 NoiseRMS dy Solving the integral Equation (15): dy dx NoiseRMS 0 dx Figure 4 graphically shows that for uniform quantization levels on the y-axis, the quantization levels on x-axis increase with amplitude. dy 1 dx ln(1 ) 1 x of Equation (7) results in ln(1 ) Equation 9 1 (a sin( x)) 0 results in Equation 15 2 dx a 2 Equation 16 Equation (17) takes equations (15) and (16) to calculate the SNR: SNR.u ( dB) dy (14) 2 n ln(1 ) a 2 2 4a 2 1 2 12 Signal Equation 8 Solving Equation (8) for dx results in Equation (9): dx 1 x Equation Equation (16) defines the RMS value for the same sinusoidal input: 1 Taking the derivative Equation (8): in Equation 14 ln( 1 ) 3 20 log a 2 n 2 2 2 a 4 a 1 2 Equation 17 Figure 5 is a plot of the SNR for a -Law compressed signal with n set to 8 and set to 255: Equation (10) defines a uniform resolution of the y-axis for an n bit ADC: www.cypress.com Document No. 001-38006 Rev. *D 3 Algorithm - Logarithmic Signal Companding - Not Just a Good Idea - It Is µ-Law Figure 5. Linear and -Law SNR Plot (n=8 =255) SNR vs Input Amplitude Building a -Law Compressor Figure 6 shows two possible ways to implement a -Law compressor: 60 50 Figure 6. Block Diagrams for -Law Compression SNR (dB) 40 Vin(t) 30 (t) 20 10 (n) Dout(n) 8 bit linear -10 Vin(t) -20 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 ADC >8 bits 0 Input (dB) (b) The math just described can be a bit overwhelming. The spreadsheet used to generate Figure 5 uLawSNRCalculation.xls, is located in the project file associated with this Application Note. It allows you to change the level of compression or digitization and view the results. The reader is encouraged to manipulate the values of n and to develop an intuitive feel for their effect on signal compression and SNR. Figure 5 also includes a plot of the SNR for an 8 bit. It is apparent that the compression allows for an acceptable SNR for much smaller inputs. It does so at the expense of peak SNR. But anything over 40 dB is a waste anyway. Equation (18) shows the dynamic range to be the ratio of the signal range to the smallest resolution: ADCRange 2 20 log DRu ( dB) 20 log min ( x ) x x (0) Equation 18 The resolution is smallest when x = 0. Combining equations (11) and (18) result in Equation (19): DRu ( dB) Dout(n) (a) 8 bit uLaw u=255 0 8 bit ADC 2 20 log ln(1 ) 2 2n Equation 19 20 log 2 n ln(1 ) With set to 255, Equation (19) reduces to a simplified Equation (20): DRu ( dB) 6.02 n 33.25 6.02 (n 5.52) Equation 20 Two different techniques are shown: Compress the signal and digitize with an 8-bit ADC. Digitize with a higher resolution ADC and compress the digitized signal down to 8 bits. Each technique has its own particular advantages and disadvantages. The first requires an ADC with only 8 bits of resolution but requires a logarithmic amplifier to implement the compression function. This technique is widely used in highly integrated single-chip designs for high volume consumer applications. The second technique requires an ADC with a higher resolution, but no logarithmic amplifier is required. Equation (19) shows that 13.5 bits is the most resolution required. As the cost of ADCs continues to decrease faster than the cost of logarithmic amplifiers, more -Law compression designs can be implemented using the second technique. The PSoC philosophy is to offer reconfigurable generalpurpose components. A logarithmic amplifier does not meet these guidelines. It is hard to make a logarithmic amplifier anything other than a logarithmic amplifier. The PSoC solution uses the second technique. It digitizes, then compresses. For an 8-ksps sample rate, the compression Equation (21) is calculated every 125 sec: y (n) sign( x(n)) ln(1 255 | x(n) |) ln( 256) Equation 21 The dynamic range for a -Law compressed signal is 33 dB or 5½ bits greater than the dynamic range for a linear signal, given the same sampling bandwidth. Three methods of calculating Equation (21) are: Again, an increase in dynamic range comes at the expense of peak SNR. Complete Mathematical Operation Linear Approximation Lookup Table www.cypress.com Document No. 001-38006 Rev. *D in 4 Algorithm - Logarithmic Signal Companding - Not Just a Good Idea - It Is µ-Law Complete Mathematical Solution requires: compression standard used for European telephony applications. It is similar to -Law with its key feature being that it is not American. Think of it as “Metric -Law.” Several tables can be stored to allow for different compression schemes within a single product. The only down side is storage space. Normalizing the Input Data Calculating a Logarithm At Least One Multiplication Several Additions Doing this all in just 125 sec requires a DSP or a processor with a fast mathematical engine. It is just not an option for a microcontroller. The Linear Approximation requires that the data be normalized to 14 bits. A bias value of 33 is added to this linear data and the five most significant bits and their position in the data word is used to calculate the compressed value. Figure 7 shows a table for a Linear Approximation to Equation (21): Figure 7. Linear to Compressed Format Chart Biased Linear Input Data S 12 11 10 9 8 7 6 5 4 1 0 S +/- 0 +/- 0 +/- 0 +/- 0 +/- 0 +/- 0 +/- 0 +/- 1 0 0 0 1 d c b a 0 0 1 d c b a 0 1 d c b a 1 d c b a d c b a c b a x b a x x a x x x x x x x x x +/+/+/+/+/- x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 1 d 0 0 0 0 0 1 d c 0 0 0 0 1 d c b 3 2 x x x 6 5 4 3 0 0 0 0 1 +/- 1 +/- 1 +/- 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 d c b a d c b a d d d d d d 2 c c c c c c 1 b b b b b b 0 a a a a a a This is the most popular -Law compression technique. It requires hardly any code to implement. So simple, in fact, that it has become the de-facto standard for -Law compression. The International Telecommunication Union standard, ITU-T G.711, defines this approximation as actual -Law compression. It somehow seems wrong that an approximation be elevated to a higher level than the real function (sort of like picking your target after shooting). Try reading ITU-T G.711. (Just try finding it) and you happily just accept it. Please note that this compression algorithm is done with 14-bit data. The dynamic range of a -Law compressed signal is no more than 13½ bits. Several software functions claim to compress 16-bit linear data to an 8-bit compressed value. They do so by discarding the least significant 2 bits before compressing. And they do so with no shame! How convenient, just throw them away. Do not fall into the trap of assuming a 16-bit compression routine requires a 16-bit ADC. Following this logic, one could easily build a 24-bit linear data to an 8-bit compressor merely by discarding the least significant 10 bits. A Lookup Table allows Equation (22) to be implemented: y f (x) Equation 22 f(x) can be any function you desire. It can be a table of mathematically calculated -Law compression values. Or it can be a table of values generated using the ITU-T G.711 algorithm. The table can compensate for any known ADC non-linearity or gain errors. Merely changing the tables easily allows A-Law compression. A-Law is the www.cypress.com f ( x) f ( x) Equation 23 So with only of half the data needed to construct a table, Table 1 shows the table size verses the input data resolution. Table 1. ADC Resolution vs. Table Size ADC Resolution Compressed Data Exponent Mantissa S = 0 for positive value S = 1 for negative value Equation (23) shows that only positive values of x need be in the table: Table Size 9 Bits 256 Bytes 10 Bits 512 Bytes 11 Bits 1024 Bytes 12 Bits 2046 Bytes 13 Bits 4096 Bytes 14 Bits 8096 Bytes 15 Bits 8096 Bytes 16 Bits 8096 Bytes Notice that the table allows for data with less than 14 bits of resolution. This is quite acceptable. The compression data has 13½ bits of dynamic range. Inputs with less resolution can be compressed. The over all dynamic range is either the resolution of the ADC or 13½ bits, whichever is smaller. Building a Law Expander Figure 8 shows a block diagram for implementing a -Law expander. Figure 8. Block Diagram for -Law Expander Din(n) (n) DAC Vout(n) The digital signal is expander fed to a DAC. Like the compressor, there are three ways to implement an expander: Complete Mathematical Operation Linear Approximation Lookup Table The Complete Mathematical Solution performing the calculation in Equation (24): Document No. 001-38006 Rev. *D requires 5 Algorithm - Logarithmic Signal Companding - Not Just a Good Idea - It Is µ-Law x(n) sign( x(n) 1 | y ( n)| 1 f ( x) Equation 24 PreAmp As with the compressor, this expansion requires a lot of mathematical operation in the 125-sec data sample time. The input signal is AC coupled to the input of PreAmp. It is a PGA User Module set for unity gain. Depending on the application, the gain can vary as much as +/- 24 dB. The output is brought outside the chip via an analog buffer. The Linear Approximation has a normalized output of 14 bits. It is shown in Figure 9: ADC Figure 9. Compressed to Linear Format Chart The signal is, again, AC coupled and brought to DELSIG11. Equation (26) defines the sample rate: Compressed Data Mantissa Biased Linear Input Data SampleRate Exponent S 6 5 4 3 0 0 0 0 1 +/- 1 +/- 1 +/- 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 d c b a +/- 0 0 0 d c b a +/- 0 0 0 d c b a +/- 0 0 0 d c b a +/- 0 0 0 d c b a +/- 0 0 0 d c b a +/- 0 0 1 d c b a +/- 0 1 d d c b a +/- 1 d c +/+/+/+/+/- 2 1 0 S 12 11 10 9 0 0 0 0 1 d c b 8 7 6 5 4 3 2 1 0 0 0 0 1 d c b a 0 0 1 d c b a 1 0 1 d c b a 1 1 d c b a 1 d c b a 1 c b a 1 b a 1 x a 1 x x 1 x x x x x x x x x x x x x x x x x x x x x x x x x Thirty-three is subtracted from the bias output value to produce the linear output. As with compression, this is the ITU-T G.711 standard for -Law data expansion. A Lookup Table allows Equation (25) to be implemented: x f 1 ( y) Equation 25 As with the compressor, this equation can implement any function you desire. It can be a table of mathematically calculated -Law compression values. Or it can be a table of values generated using the ITU-T G.711 algorithm. It can compensate for any system non-linearity. The actual output can be a 14-bit linear output or it can be the data required to control a DAC. The symmetry of the positive and negative values allows for only 128 words of table storage. With most likely two bytes per word, the storage requirement is 256 bytes. A PSoC -Law Compressor Figure 10. PSoC -Law Compressor Block Diagram PreAmp DELSIG11 P0.1 P0.3 P2.1 (n) Tx buf0 8ksps AGNDBuffer P0.5 buf1 It consists of the following sections: PreAmp 11-Bit Delta Sigma ADC -Law Compressor Serial Transmitter www.cypress.com 115.2k baud P1.4 Equation 26 For a maximum data clock of 8 MHz, the sample rate is only 7.81 ksps. This falls well below the required 8 ksps. The DELSIG11 uses a timer with a period of 256 to control its decimator. If its period is changed to 250 then Equation (27) defines the sample rate: SampleRate DataClock f ( x) f ( x) 1000 Equation 27 For a data clock of 8 MHz, the sample rate is now 8 ksps. Without going into details about delta-signal operation, the 2 gain is also reduced by (250/256) . The following code segment shows how to alter the ADC for 8 ksps operation: DELSIG11_StartAD(); DELSIG11_TimerDR1 = 0xF9;//set period to 250 -Law Compressor The compressor uses a lookup table. The table has a gain adjust factored into it to compensate for the ADC loss. It implements the ITU-T G.711 compression algorithm. It takes 11-bit signed output data from the DELSIG11 and converts it to an 8-bit compressed value. Example Code 1 is the actual routine: Code 1 Figure 10 shows a block diagram for a -Law compressor: Vin DataClock f ( x) f ( x) 1024 Serialout ;----------------------------------------;; cDS11_to_uLaw: ;; Takes an 11 linear value and ;; converts it to a uLaw Value ;; and mantissa. Updates DACs. ;; INPUTS: X, A ia an 11 bit integer ;; OUTPUTS: A is the uLaw Value ;;---------------------------------------cDS11_to_uLaw: _cDS11_to_uLaw: swap A,X and A,07h ;keep lower 3 bits add A,(>uLawData);point to uLawData Table romx ;uLaw Value returned in A ret Document No. 001-38006 Rev. *D 6 Algorithm - Logarithmic Signal Companding - Not Just a Good Idea - It Is µ-Law This function can be found in uLawStuff.asm, located in the project file associated with this Application Note. Also included is uLawStuff.h that makes it a fastcall ‘C’ function. Serial Transmitter It is just a 115.2 k-baud serial UART transmitter. For data having a bandwidth of 64 kbps, this transmission rate is adequate. A PSoC -Law Expander Figure 11 shows a block diagram for a Law expander: Figure 11. PSoC -Law Expander Block Diagram SallenKey Mantisa Exponent Vcc p0.4 Vref buf2 Serialin p1.6 Rx 115.2K baud add A,32 ;pos is neg * neg endif1: swap A,X and A,7fh ;mask out sign index ExponentData M8C_Stall mov reg[Exponent_cr0],A M8C_Unstall mov A,X mov reg[Mantissa_cr0],A ret As with the compression function, this expander function can be found in uLawStuff.asm, located in the project file associated with this Application Note. It also is defined as a fastcall ‘C’ function. p0.0 p0.2 Vout buf3 4 Pole (n) Low Pass Filter It consists of the following sections: The DAC output updates at 8 ksps. For a 300 Hz sinusoid this works out to 26.67 samples. Twenty-six points do make up something that resembles a sinusoid. But a 3 kHz sinusoid only has only 2.67 samples. Not much of a sinusoid. A reconstruction filter is required to produce a smooth output over 300 Hz - 3500 Hz bandwidth. This application uses a six-pole, low pass filter. Serial Receiver Four-Pole Switched Cap Filter -Law Expander Four of these poles are implemented with two LPF2 User Modules in series. They are switched capacitor bi-quad filters. Their component values can be viewed in the parameter section of each filter in the project associated with this Application Note. The output of these filters is brought outside the chip via an analog buffer. Four-Pole Switched Cap Filter Two-Pole Sallen Key Filter Serial Receiver It is just a 115.2 k-baud serial UART receiver. For data being received having a bandwidth of 64 kbps, this is adequate. -Law Expander The expander uses lookup tables to control the Matissa and Exponent multiplying DACs. The ITU-T G.711 expansion is implemented in these tables to provide an 11-bit signed linear output. Example Code 2 is the actual routine: Code 2 ;--------------------------------------;; WriteuLawDAC: ;; Takes an 8 bit signed value and ;; separates into sign, exponent ;; and mantissa. Updates DACs. ;; INPUTS: A contains the uLaw value ;; OUTPUTS: None. ;;-------------------------------------WriteuLawDAC: _WriteuLawDAC: mov X,A add A,80h if1: jnc else1 ;(is a neg value) index MantissaData jmp endif1 else1:;(A is a positive value) index (MantissaData - 128) www.cypress.com Two-Pole Sallen Key Filter This filter is built with a PGA User Module configured as a buffer, two external resistors, and two external capacitors. It completes the rest of six-pole response. It also removes switch noise generated by the previous filter. Appendix A has the values of the discrete components. It also shows User Module placement for the whole project. A Complete System Test Figure 12 is a block diagram of the compressor and expander figured as a compandor. Figure 12. Compressor and Expander Vin Dout -Law Compressor Din -Law Expander Vout Of course, for real applications, the compressor and expander would be separate applications in different chips, if not different products. Combining them allows the SNR of a complete compression, expansion to be measured. The code to do this is added into the DELSIG11 interrupt at the point marked for user code addition. It is shown in following example Code 3: Document No. 001-38006 Rev. *D 7 Algorithm - Logarithmic Signal Companding - Not Just a Good Idea - It Is µ-Law Code 3 ;;----------------------------------------------;; ;; here data is now in X,A The user's handler should be placed Figure 14 shows the same 1.0 kHz signal but at an input level of 100 mVp-p, 26 dB down from the input level of Figure 13. The harmonic levels and noise level drop along with the signal level to maintain essentially constant signal-to-noise ratio. The first sampling alias at 7.0 kHz remains at 65 dB below signal level: Figure 14. Spectral Plot for 1 kHz 100 mVpp Input call cDS11_to_uLaw call TX8_1_SendData include "RX8_1.inc" mov A,reg[RX8_1_CONTROL_REG] and A,RX8_RX_COMPLETE if_100: jz endif_100 ;(data available) mov A, reg[RX8_1_RX_BUFFER_REG] call WriteuLawDAC endif_100: is ;;-----------------------------------------------The 11-bit data is compressed and sent out the serial port. The serial receiver is polled for an available byte. If an available byte is found, it is retrieved, expanded, and converted back to an analog signal. Signals at 300 and 3.0 kHz and at 2.0 Vp-p and 100 mVp-p are shown in figures 15 through 18. Figure 15. Spectral Plot for 300 Hz 2 Vpp Input This works only if the data rates are exact. It only happens when they are generated with the same clock. For real applications, incoming data would be handled with its own interrupt or collected in a circular FIFO. The performance measures of a signal compression system are harmonic distortion and noise over the range of signal frequency and level. Figure 13 shows a 1 kHz mid-band signal at an input level of 2Vpp. The highest harmonic is 45 dB below the fundamental. Noise contributions are from broadband noise and sampling aliases. The first sampling alias (fsample-fsignal) is at 7.0 kHz (8 kHz1 kHz) is 65 dB below signal level: Figure 13. Spectral Plot for 1 kHz 2 Vpp Input Figure 16. Spectral Plot for 300 Hz 100 mVpp Input The nature of -Law compression is to generate essentially fixed SNR over a wide range of signal levels. www.cypress.com Document No. 001-38006 Rev. *D 8 Algorithm - Logarithmic Signal Companding - Not Just a Good Idea - It Is µ-Law Note The low harmonic distortion level is maintained. Figure 17. Spectral Plot for 3 kHz 2 Vpp Input Higher frequencies have harmonics out of the nominal voice band, but alias harmonics can wind up in the voice band. The largest alias, shown in figures 17 and 18, is the 6 kHz harmonic of the 3 kHz signal below the 8 kHz sample frequency or 2.0 kHz for a 3.0 kHz input. This represents the highest noise case, but in a practical system these alias levels almost certainly would not impact usable signal fidelity. Summary Figure 18. Spectral Plot for 3 kHz 100 mVpp Input www.cypress.com Logarithmic Data Compression makes acceptable quality voice communication with a greater reduced signal bandwidth. The PSoC architecture allows easy implementation of the ITU-T G.711 -Law compression/expansion format. The large amount of chip analog resources allows complete signal conditioning, digitization, filtering, and signal reconstruction with only a handful of additional passive components. Document No. 001-38006 Rev. *D 9 Algorithm - Logarithmic Signal Companding - Not Just a Good Idea - It Is µ-Law Appendix A. PSoC User Module Placement and Pin Interface Schematic Vin 0.1μF 1000pF 4700pF 18.1KΩ 39KΩ 15KΩ Pin 4 Pin 24 P01 Pin 8 P21 P05 P03 0.1μF 15KΩ Pin 3 470Ω AGND P02 P04 Pin 26 Pin 2 Pin 25 22μF Vout P16 Pin 18 Global In 6 Vcc 8.2KΩ P14 Pin 17 Global Out 4 www.cypress.com Document No. 001-38006 Rev. *D 10 Algorithm - Logarithmic Signal Companding - Not Just a Good Idea - It Is µ-Law Document History Document Title: Algorithm - Logarithmic Signal Companding - Not Just a Good Idea - It Is -Law – AN2095 Document Number: 001-38006 Revision ECN Orig. of Change Submission Date Description of Change ** 1520284 PFZ 10/09/2007 New application note *A 3110002 PFZ 12/14/2010 No Technical updates. Correct few typo errors. Added Document History details. *B 3658917 SAMP 6/28/2012 Updated Appendix A. PSoC User Module Placement and Pin Interface Schematic: Updated the Analog and Digital Block Diagrams to PD 5.2. Included all PSoC1 part numbers with 4 analog columns. Put in new application note template. *C 4224527 DCHE 12/18/2013 Updated in new template. Completing Sunset Review. *D 4609931 DCHE 12/29/2014 Updated example project to PSoC Designer 5.4 Removed references of AN2036 Rephrased application note abstract www.cypress.com Document No. 001-38006 Rev. *D 11 Algorithm - Logarithmic Signal Companding - Not Just a Good Idea - It Is µ-Law Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Interface cypress.com/go/interface Lighting & Power Control cypress.com/go/powerpsoc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/usb Wireless/RF cypress.com/go/wireless Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone Fax Website : 408-943-2600 : 408-943-4730 : www.cypress.com © Cypress Semiconductor Corporation, 2007-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. www.cypress.com Document No. 001-38006 Rev. *D 12

- Similar pages
- AN84783 - Accurate Measurement Using PSoC 3 and PSoC 5LP Delta-Sigma ADCs.pdf
- DELSIG11_001-13433.pdf
- CYPRESS CY8C21X34
- http://ecologylab.net/courses/sensoryInterfaces/resources/PSoCTRM.pdf
- CYPRESS CY8C21323
- AD AD8307ARZ-REEL
- AD SSM2122
- V07N2 - JUNE
- AN2017 PSoC 1 Temperature Measurement with Thermistor.pdf
- AN2239 PSoC 1 Selecting The Right ADC.pdf
- AN2099 - PSoC 1, PSoC 3, PSoC 4, and PSoC 5LP - Single-Pole Infinite Impulse Response (IIR) Filters.pdf
- STMICROELECTRONICS L7250
- ZMD ZMD31150
- V - Cypress
- STMICROELECTRONICS ETL9445
- PHILIPS P80C550EFAA